> From: E. Groenenberg <qua...@xs4all.nl> > > Any current & reasonably seasoned Unix or derivative has shmat() & shmdt() > (or equivalent) calls for attaching & detaching a segment of a given size. > > Also MS$ has this > [...] > so a common API for SIMH would be fairly easy. > >[ ...] > > With this feature, it would probably also easy to realize a PDP-11/74 > with 4 instances of SIMH.
Mapping shared memory segment into the address spaces of multiple SIMH instances is the straightforward part. More intricate parts are: 1) Mapping guest memory-consistency model to host memory-consistency model. Does legacy software expect to observe updates to the shared memory executed by simulated VCPU1 (or virtual IO processor) to become observable by VCPU2 in the same order they were executed by VCPU1? If yes, this would not work (without special handling by the simulator) on modern machines with weaker memory-consistency model. What is the cache coherency protocol of the simulated system and how does it map to the host system? Does simulated system have any system events (such as inter-processor interrupts or IO completion) that affect cache synchronization between VCPUs or VCPUs/VIOPs, and if yes, how this is to be mapped to the simulator? Ultimately it all depends on exact actual synchronization patterns utilized by legacy software. 2) Mapping memory atomicity. Does host machine provide the same memory access atomicity and separability as the simulated machine? For instance, if a simulated machine provides a way to update a byte at address A without interfering with concurrent updates to bytes at A-1 and A+1 by other VCPUs, then this would take a special effort to be implemented on a host machine that has let us say a 4-byte word as the minimum separable unit. Ditto for atomic and separable 2-byte word accesses (atomicity would mean that concurrent writes to the word do not result in resultant bytes values coming from different writes, separability would mean that concurrent writes to neighbor words do not interfere with each other). 3) Does a simulated system have any synchronization facilities such as interlocked instructions or machine-specific registers that affect cache coherency? 4) Mapping execution model. What happens if a host system thread simulating the execution of VCPU1 (or virtual IO processor) gets preempted, while VCPU2 is waiting for a response from VCPU1? Does the simulated system (specifically, its legacy software) rely on finite timeouts? _______________________________________________ Simh mailing list Simh@trailing-edge.com http://mailman.trailing-edge.com/mailman/listinfo/simh