I added my comments as follows:
The four VAX chips differ slightly in their interrupt behavior.
1.
MicroVAX II - and ONLY MicroVAX II - will mask the incoming
interrupt vector down to 10bits. Bit<1> is ignored, and bit<0> is
treated as the 'Qbus' flag; if set, it forces all device interrupts
to IPL 17.
2.
CVAX and Rigel use a WORD (16b) read to get the interrupt vector.
Bit<1> is ignored, and bit<0> is treated as the 'Qbus' flag; if set,
it forces all device interrupts to IPL 17. To quote the chip spec
about an interrupt acknowledge cycle:
|Bits <15:02> of the incoming data are used to create the vector
offset within the System Control Block. |
3.
NVAX uses a WORD (16b) read to get the interrupt vector. Bit<1>, if
set, forces a passive release, and bit<0> is treated as the 'Qbus'
flag; if set, it forces all device interrupts to IPL 17.
Thus the base VAX simulator, which is a CVAX (MicroVAX 3900), is
correct. When the interrupt and exception code incorporated into the
MicroVAX II simulator without change, it's not.
QVSS was probably only used on MicroVAX II systems; by the time CVAX
came out, there were dedicated VAX workstations and better graphics chips.
The "fix" would be to parameterize the interrupt mask in the 'model.h'
file and use that parameter in place of the fixed constant 0xFFFF in
module intexc.
The problem is moot on the 780. The SCB vectors are for Nexus interrupts
and are determined algorithmically. Unibus device vectors are read by
accessing registers in the UBA. No masking is needed. The 750 is very
similar, and it's likely that the 8600 behaved the same way.
I cannot speak for the 730 and MicroVAX I, which connected directly to
IO busses. The MicroVAX I technical manual says that read vector returns
a word, but it also says that vectors beyond 0x1FC (9 bits) are not allowed.
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