Whilst experimenting with a new device on VAX/VMS V4.5 I got a fatal bugcheck (exception whilst above ASTDEL). The problem turned out the be a reserved operand fault and I traced it back to the following code (shown here from the VMS 3.0 source listings):
MOVL PCB$L_PHD(R0),R0 ; Get PHD address MOVB PHD$B_ASTLVL(R0),R0 ; And fetch ASTLVL MTPR R0,#PR$_ASTLVL ; Update current value As you can see R0 will contain an S0 address after the first instruction, then only the lower byte is overwritten with the new AST level. The whole longword is then written to the ASTLVL IPR. Currently the test for this IPR in vax_cpu1.c is: if (val > AST_MAX) RSVD_OPND_FAULT; Due to S0 addresses having bit 31 set this triggers the reserved operand fault. The VMS code is clearly expecting a mask to be applied to the value. I've checked various manuals to try and find the answer but the results were not totally conclusive. EB-17835-18 - VAX-11/780 Hardware Handbook (1979) http://manx-docs.org/details.php/1,8111 Page 71 - Bits <31:3> ignored, returns 0 EK-VAXV2-HB-002 - VAX Maintenance Handbook (VAX-11/780) (Mar 1983) http://manx-docs.org/details.php/1,2826 http://www.bitsavers.org/pdf/dec/vax/780/EK-VAXV2-HB-002_vaxMaintHbk_Mar83.pdf Page 119 - Reserved operand fault if not valid i.e. MBZ /= 0 EP-ES0AA-DL-124 - VAX-11/780 Microcode (Jan 1982) http://www.bitsavers.org/pdf/dec/vax/780/fiche/EP-ES0AA-DL-124_4of6_780uCode_Jan82.pdf Page 678 - A mask of 0x7 is applied at line 25908 I've also looked at the VAX-11/750 and came up with similar results: EK-VAXV3-HB-001 - VAX Maintenance Handbook (VAX-11/750) (Mar 1983) http://manx-docs.org/details.php/1,2827 Page 20 - Reserved operand fault if not valid i.e. MBZ /= 0 CMT098.MCX - VAX-11/750 Microcode (Nov 1983) http://www.bitsavers.org/pdf/dec/pdp11/xxdp/fiche_200dpi/0187_CMT098.MCX_750uCod.pdf Page 855 - A mask of 0x7 is applied at line 35030 I guess the microcode listings are the ones to trust and the two VAX Maintenance Handbooks are probably incorrect. I've prepared a fix to add a machine specific test for the AST level IPR but I just wanted to open this up for comments before sending a pull request in case I might have overlooked something. Matt _______________________________________________ Simh mailing list Simh@trailing-edge.com http://mailman.trailing-edge.com/mailman/listinfo/simh