> On Oct 26, 2017, at 1:55 PM, Seth Morabito <[email protected]> wrote:
> 
> Hello all, and especially those who have written or are writing
> simulators,
> 
> I'm battling system timing in the 3B2/400 emulator I'm working on. As
> with any system, particular activities such as disk seeks, reads, and
> writes must be completed within certain margins -- if they happen too
> early or too late, an interrupt will be missed. But the "fudge factor",
> so to speak, seems pretty tight on the 3B2, possibly because it runs at
> a system clock frequency of 10MHz.

In most systems, odd things can happen if interrupts happen too soon.  If an 
I/O completes essentially instantaneously, then software that relies on being 
able to start I/O, then do some more stuff, and count on that completing before 
the interrupt -- even though interrupts are enabled -- will break.

The correct description for such software is "defective" though there certainly 
is quite a lot of it in the wild.

For this reason, simulators need to delay interrupts by some number of 
instruction times, and SIMH makes that easy.  But it doesn't normally matter 
that the timing is not exact, all that's needed in most cases that the 
interrupt is held off long enough to work around the sort of poorly written 
code I mentioned.  So if you base your delays on average instruction times and 
average I/O latency, you'll normally be fine.  In the 3B2 case, with 10 MHz 
clock and an average of 8 cycles per instruction, that's 1.25 MIPS.  A disk I/O 
might take 20 ms (1/2 rotation at 3600 RPM), so that would be 25,000 
instruction times.  Quite likely you could crank that number way down and have 
the code still run.

If you want to have realistic timing, that's a different matter.  You'd find 
yourself tracking the cylinder position and charging for seek timing.  The 
DECtape emulation does that, and it matters because some operating systems 
(TOPS-10, VMS) do tape position prediction based on elapsed time.  But that's 
an unusual case.

        paul


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