Looking at the DEC ChipKit documentation, it seems fairly clear that a
device implemented with the DC003/5/6/10/21 series of chips never drives
BBS7. BBS7 is an input to the address matching logic implemented in the
DC005, but that's it.
On the other hand, the DEC Standard for the LSI11 bus says that devices
are allowed to do DMA to the IO page, and that testing with the
mandatory 'missing words' (the first 8 words are reserved) is a standard
diagnostic technique for testing the NXM logic on a DMA device.
On the other, other hand, Qbus configuration standards also say that the
last 8KB of physical address space must not be implemented as memory. So
if the IO page doesn't respond to DMA requests, then the device will
<still> get an NXM, because there's no memory.
I've looked through the available Qbus DMA device schematics (there
aren't many), and I see no evidence of devices doing the 9b AND to
detect IO space and assert BBS7. However, many devices use complex gate
arrays, and who knows what's going on inside them?
So my tentative conclusion stands: the LSI11 bus did not do DMA to IO
space, even if it was theoretically possible.
Next, chips. I reread the J11 specification. As I thought, there's no
way to access any of the registers implemented inside the chipset itself
from outside. The J11 has no "snoop" function.
On the other hand, there is a small space of "system" registers which
are expected to be implemented, if at all, in the surrounding CPU logic,
which was always a gate array. I suspect, but can't prove, that the gate
arrays didn't respond to DMA requests on these registers either, only on
DMA requests to real memory. That was certainly true of the first J11
module, the KDJ11A.
Now, as to bus maps. The 11/70 bus map has a jumper-adjustable upper
limit for what parts of Unibus address space go through the map, and
what parts are resolved on the Unibus itself. The maximum value is
760000; that is, the IO page can never be mapped to memory. The 11/44
bus map has a jumper adjustable upper and lower limit of unmapped Unibus
space in addition to the IO page, which is always off limits. The 11/84
bus map is similar, but the jumpers have been replaced by configuration
registers.
So my conclusion is that IO mapped PDP11s (which are, of course, always
Unibus) do support DMA to IO space, so you could put a GT40 (in theory)
on a Unibus J11, and it would work.
Okay, here's the bottom line, then.
1. There's no need to support DMA to IO space on Qbus systems. It wasn't
done.
2. Therefore, the ba limit test can be for the 18b Unibus limit on
Unibus systems, that is,
if (UNIBUS && (ba >= unibus_io_base_page)) {then read/write IO space}
3. It's still necessary to keep DMA access away from the CPU and system
registers, with all the hair that implies.
Personally, I like Tim's solution of a private interface between
consenting devices. That would certainly work for the GT40 and its ROM too.
/Bob
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