> On Sep 18, 2018, at 10:35 AM, Ludwig TAUER <[email protected]> wrote:
>
> Hi folks!
>
> Seems I have found a bug in the PDP-11 emulating the
> MUL instruction.
>
> The current code takes the specified register as source
> instead of the register pair R and R+1 if the register is even.
The current code is correct: mul takes 16 bit inputs, and delivers a 32 bit
result if the register is even, the low 16 bits if it is odd.
> The DIV instruction is also invalid, but the other way around:
> if R is odd, R is duplicated into the high half of the 32 bit int.
Odd R for div is a strange thing to do. I'm not sure what it is supposed to
do, the manuals are not at all clear. What do you believe is correct, and what
document says so?
paul
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