> On Jul 1, 2019, at 5:09 PM, Seth J. Morabito <[email protected]> wrote:
>
>
> Lars Brinkhoff writes:
>
>> Bob Supnik wrote:
>>> The J-11 based simulators (11/73 and up) are the only ones that were
>>> verified against actual machine microcode.
>>
>> Speaking of which. Someone claimed SIMH wouldn't be well suited for a
>> microcode level simulation. Is there any truth to this? If so why?
>
> An interesting question! It's true that none of the simulators currently
> do microcode simulation, but I don't see why they couldn't. Certain
> assumptions about clock calibration may be in question, but I'm not
> sure. Even if they were, I think it's a surmountable problem and not
> fundamentally impossible given SIMH's architecture.
I can see no theoretical issues, but a number of practical ones.
("In theory, there is no difference between theory and practice. But, in
practice, there is." -- Jan L.A. van de Snepscheut)
The programmer ISA is usually well documented, minimally in programmer's
manuals and sometimes in formal standards. The micro-architecture is
documented in internal design specs that often have not survived and may not
have been updated to reflect the actual design as shipped.
Schematics and ROM contents, if accurate, may help but are not sufficient if
parts of the micro-architecture are buried inside chips whose internals are not
exposed in those documents.
Micro-architectures typically are done separately for each product, so a given
family (like PDP-11 or VAX) might have a dozen vastly different ones.
Micro-programs are often very wide and directly manipulate many low level
controls. So a micro-architecture simulator would be a whole lot more
complicated than the ISA simulator (and as a consequence much slower).
If the micro-architecture simulation is accurate, it would give an accurate ISA
simulation. But then again, if it's possible to build an accurate simulation
one might as well put the effort into making the ISA simulation accurate.
---
An analogous case comes to mind. It's possible (and has been done) to build a
VHDL model of a PDP-11. That's a separate design, just as SIMH is, and both
may have discrepancies from the original hardware. If you have enough detail
you could build a VHDL model of the original design, which might be interesting
-- for example, it would allow you to explore undocumented aspects of the
machine operation.
I've actually done this (in part, the work is not nearly complete) for the CDC
6600. For that machine, full transistor-level schematics exist, so a gate
level accurate VHDL model would seem to be possible. It's actually
surprisingly hard mostly because in that machine timing is on the hairy edge of
not working -- you must simulate the gate delays to come even close, and some
of the wire delays. If you do so then easy parts like the peripheral
processors work, but harder parts like the instruction scheduling machinery are
so "on the edge" that they stubbornly refuse to work.
I suppose translating, say, PDP-11/20 or EL-X8 schematics to gate level VHDL
models would be possible. Whether anyone would find it worth the trouble is
another question.
paul
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