URL:
<http://savannah.nongnu.org/bugs/?35195>
Summary: ICALL simulation: wrong cycles
Project: Simulavr: an AVR simulator
Submitted by: None
Submitted on: Fr 30 Dez 2011 09:12:24 UTC
Category: Simulation
Severity: 3 - Normal
Item Group: None
Status: None
Privacy: Public
Assigned to: None
Originator Email: erich.wen...@iaik.tugraz.at
Open/Closed: Open
Discussion Lock: Any
Component Version: simulavr
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Details:
Hi,
working simulavr: git clone (one month ago)
processor: atmega128
ICALL should take 3 cycles to execute, but the simulator finishes its
execution within one cycle.
(I need the cycle accuracy for a cycle accurate atmega128 written in VHDL)
./c_code/main.elf 0x02e8: test_assembler+0x108 {LDI R30, 0x00 }
./c_code/main.elf 0x02ea: test_assembler+0x109 {LDI R31, 0x01 }
./c_code/main.elf 0x02ec: test_assembler+0x10a {ICALL Z SP=0x10fa
0x77 SP=0x10f9 0x1 }
./c_code/main.elf 0x0200: test_assembler+0x94 {FMULS R18, R19
SREG=[--H---Z-] }
Best regards,
Erich
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<http://savannah.nongnu.org/bugs/?35195>
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