This sounds good. As Thomas K writes a re-integrate of Windows support is possible. I will look at your branch and probably we get a strategy how to merge everything. Honestly my attemps are currently work-in-progress and without a clear strategy. I will setup a fork repo on github so that we can see how it can be sync'd.
What version of Visual Studio do you use? I have VS2013 and VS2019 Community Edition available. This should be obscured by CMake, but I would get a good feeling if we could share easier ideas. > * the console tracer is now working. The console tracer was dropped a very long time ago and I have no idea why. I reenabled printing register content, memory content, register names, timestamp, irq vector name and a lot more. I just needed the register content during a simulation and have just added this part. Sounds like you did much more. > * open drain simulation is working again Honestly I don't know what's the topic. I have a problem on the desk: I want to simulate the UART RX ISR. I currently don't have any idea how I can prepare the UART registers and trigger an interrupt at a give CPU cylce (or cycle range). - Does your branch supports this in any way? - Did I miss this feature in the main branch? Regards, Helge Am 28.10.2020 um 13:20 schrieb Klaus Rudolph: > I am currently not able to use the master branch of simulavr nor > simulavr 1.1 because all these versions have lost too many features in > the past. I started to reintegrate a lot of the old features and also > fix a long list of bugs. There are still a long list of known bugs, e.g. > broken irq handling, spi, some unit tests and a lot of dropped features. > > So I decided to create a new branch which you can find on the repo named > "krud_private_reenable_old_features". The meaning of "private" is, that > I will not again see commits on this branch which will again remove > features :-) > > The current state of "my" branch is: > * lcd support is now back from the old simulator and works as expected. > In addition 8 bit mode interface added. > > * the console tracer is now working. The console tracer was dropped a > very long time ago and I have no idea why. I reenabled printing register > content, memory content, register names, timestamp, irq vector name and > a lot more. > > * open drain simulation is working again > > * building of libs for python and tcl is now working again > > * unit tests are reenabled, some minor bugs have fixed there > > * python is adapted to python 3 > > I did not remove any windows stuff on "my" branch, so there is a chance > that it works out of the box but I have no windows installation and > can't test it. > > Feel free to use the new branch, it has a lot of reenabled features and > a lot of bugs fixed. > > I have no idea what we will see in the future on the project. I did not > know if the master branch will take over my changes or not. But as the > master removes so many features, I was simply not able to compile nor to > use it anymore. The cmake stuff on master did not work on my fedora > installation so I wrote my own Makefile for the master branch, but still > it has dropped so many features that it is useless for me. Especially > that the console tracer is only tracing the instructions and nothing > more is useless for me. > > I have planned, but without any timeline, also to fix irq handling ( > using simply the old working code before it was "simplified" to get > correct irq handler selection and timing. > > Also planned to monitor and analyze nested irqs in the irq statistic. > That has started but is not finished. > > Also using the verilog interface for tracing registers, irq level and > memory content will be prepared ( after irq level info is available ). > > Again: Feel free to use it, maybe some of the changes may help you, > maybe the non removed windows support is a startpoint. > > Regards > Klaus