It would be a much easier project to implement a soft core CPU in the fpga then do the sip stack in software.
On 10/21/07, [EMAIL PROTECTED] <[EMAIL PROTECTED]> wrote: > > It is amazing and confusing that the VHDL is used to implement the SIP > Protocol, which is application layer protocol. > I only heard that the HLDC can be implemented via VHDL, but for the SIP > protocol, have you considered to use the C++ language in the Xilinx EDA > enviorment? > > > Thanks, > Alex > 6-554-8782 > > -----Original Message----- > From: [EMAIL PROTECTED] > [mailto:[EMAIL PROTECTED] On Behalf Of > [EMAIL PROTECTED] > Sent: Saturday, October 20, 2007 2:43 AM > To: [email protected] > Subject: Re: [Sip-implementors] SIP in a FPGA with VHDL > > > From: =?ISO-8859-1?Q?Luis_Alberto_Cacho_Garc=EDa?= > <[EMAIL PROTECTED]> > > Hi, i'm newbie in this topic (SIP), and I tried to implement over > FPGA > specify in a Xilinx Spartan 3E, but the fact is that i don't know > the > architecture of SIP, I study the RFC3261 but I don't understand > very > well. I request your help to understand the protocol and implement > in a > FPGA with VHDL. > > I have no idea how one would implement SIP using VHDL. SIP is a very > complicated protocol. > > Do you know how you would implement a simpler protocol, such as TCP, > using VHDL? > > Dale > _______________________________________________ > Sip-implementors mailing list > [email protected] > https://lists.cs.columbia.edu/cucslists/listinfo/sip-implementors > > _______________________________________________ > Sip-implementors mailing list > [email protected] > https://lists.cs.columbia.edu/cucslists/listinfo/sip-implementors > -- Ryan Mitchell <[EMAIL PROTECTED]> Telecom Logic, LLC http://www.tcl.net _______________________________________________ Sip-implementors mailing list [email protected] https://lists.cs.columbia.edu/cucslists/listinfo/sip-implementors
