Robert Collins wrote:
On Sun, 2005-12-25 at 09:34 +1100, O Plameras wrote:
James Gregory wrote:
That's exactly right. And if you compile without CONFIG_SMP, that's what
gets built into your kernel. You can get away with it because of the
clever way in which a CPU does one thing at a time; there is no "true"
parallelism.
By the way, is it not true that 'pipelining' that's a feature of x86
CPU's starting
with i586 which I have pointed out in one of my previous post is
(another name)
implementation of 'parallel' processing ? This means that more than one
instructions may be
executed in one clock cycle. This is implemented by using a bus
interface unit
(BIU) and an execution unit. Experts on Intel Arch may confirm the
truthfullness or
falsehood of this assertion. (I'm not an expert, I just know by
researching).
With pipelining, the CPU overlaps instruction fetching and decoding with
instruction execution, i.e., while one instruction is executing BIU is
fetching
and decoding the next instruction. So, assuming you're willing to add
hardware
you can execute more and more operations in parallel.
So, in this way there is true parallelism in x86 arch.
Just a clarification.
Holy shit! You are soooo off base here its not funny. 'More than one
thing per clock cycle' -> What do clock cycles have to do with
parallelism? Nothing. Concurrency means 'concurrent'. If two operations
complete in one clock cycle *in series*, then its not parallel. Its
fast, but not parallel.
Have a look at the intel documentation on Intel IA-32 Architecture -
Series x86. You
will be pleasantly surprise.
If you want an cpu architecture that performs *concurrent operations* in
one cpu, look into EPIC or IA-64.
Just a un-clarification.
Rob
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