Hi Oliver, On 05/17/2010 01:06 PM, Oliver Hartkopp wrote: > The SJA1000 command register is concurrently written in the rx-path to free > the receive buffer _and_ in the tx-path to start the transmission. > On SMP systems this leads to a write stall in the tx-path, which can be > solved by adding some locking for the command register in the SMP case.
We should explain why a write stall can happen. Here is the relavant part from the SJA1000 data sheet, 6.4.4 COMMAND REGISTER (CMR): "Between two commands at least one internal clock cycle is needed in order to proceed. The internal clock is half of the external oscillator frequency." Wolfgang. _______________________________________________ Socketcan-core mailing list [email protected] https://lists.berlios.de/mailman/listinfo/socketcan-core
