Hi Wolfgang, > -----Original Message----- > From: Wolfgang Grandegger [mailto:[email protected]] > Sent: Friday, September 03, 2010 12:21 PM > To: Bhupesh SHARMA > Cc: Marc Kleine-Budde; [email protected] > Subject: Re: [RFC PATCH 1/4] SPEAr320 CCAN driver > > On 09/03/2010 06:06 AM, Bhupesh SHARMA wrote: > > Hi Wolfgang and Mark, > > > >> -----Original Message----- > >> From: Wolfgang Grandegger [mailto:[email protected]] > >> Sent: Wednesday, September 01, 2010 6:01 PM > >> To: Marc Kleine-Budde > >> Cc: Bhupesh SHARMA; [email protected] > >> Subject: Re: [RFC PATCH 1/4] SPEAr320 CCAN driver > >> > >> On 09/01/2010 02:10 PM, Marc Kleine-Budde wrote: > >>> Wolfgang Grandegger wrote: > >>>>> static u16 spear1310_can_read_reg(const struct bosch_ccan_priv > >> *priv, > >>>>> enum ccan_regs reg) > >>>>> { > >>>>> u16 val; > >>>>> > >>>>> /* 16 bit registers are aligned at 16-bit boundary */ > >>>>> val = readw(priv->reg_base + reg); > >>>>> return val; > >>>>> } > >>>>> > >>>>> static void spear1310_can_write_reg(const struct bosch_ccan_priv > >> *priv, > >>>>> enum ccan_regs reg, u16 val) > >>>>> { > >>>>> /* 16 bit registers are aligned at 16-bit boundary */ > >>>>> writew(val, priv->reg_base + reg); > >>>>> } > >>>>> > >>>>> The one for SPEAr320 will look like: > >>>>> static u16 spear320_can_read_reg(const struct bosch_ccan_priv > >> *priv, > >>>>> enum ccan_regs reg) > >>>>> { > >>>>> u16 val; > >>>>> > >>>>> /* shifting 1 place because 16 bit registers are word > aligned */ > >>>>> val = readw(priv->reg_base + (reg << 1)); > >>>>> return val; > >>>>> } > >>>>> > >>>>> static void spear320_can_write_reg(const struct bosch_ccan_priv > >> *priv, > >>>>> enum ccan_regs reg, u16 val) > >>>>> { > >>>>> /* shifting 1 place because 16 bit registers are word > aligned */ > >>>>> writew(val, priv->reg_base + (reg << 1)); > >>>>> } > >>>> > >>>> These functions are still pretty generic and could be handled by a > >>>> generic platform C_CAN driver via platform data field "reg_shift". > >>> > >>> the sja1000 uses IORESOURCE_MEM_xxBIT for this. See [1]. > >>> > >>> cheers, Marc > >>> > >>> [1] > >>> > >> > http://lxr.linux.no/linux+v2.6.35/drivers/net/can/sja1000/sja1000_platf > >> orm.c#L119 > >> > >> Well, yes and no. I think for the SPEAr *word* accesses are required > on > >> a 2 and 4 byte boundary? Bhupesh? We could use IORESOURCE_MEM_16BIT > and > >> IORESOURCE_MEM_32BIT for these access types. But that might need to > be > >> extended. In the C_CAN manual there is written: > >> > >> "Up to now the C_CAN module is delivered with three different > >> interfaces. An 8-bit interface for the Motorola HC08 controller > and > >> two 16-bit interfaces to the AMBA APB bus from ARM. They can > easily > >> be replaced by a user-defined module interface." > >> > > > > Ok, so are we aligned on generating a V2 that has CCAN as a platform > driver > > on the lines of sja1000_platform with > "include/linux/can/platform/c_can.h" > > providing the platform details and register offsets (as may vary with > different > > SoCs). > > Yes. > > > And yes you are right. In SPEAr *word* accesses are required on a 2 > and 4 byte > > boundary. > > Would byte access work as well? >
No. I don't remember SPEAr supporting 8-bit access. Regards, Bhupesh _______________________________________________ Socketcan-core mailing list [email protected] https://lists.berlios.de/mailman/listinfo/socketcan-core
