Hi Attila, Sometimes you postings are well thought out, like the one at 12:03 today, but then you do postings like this where it sounds like you have no idea what you're doing....
Attila Kinali wrote: .. > > Attached is a picture of an DDR SRAM chip mounted at the bottom of > the net5501. For your convenience, i marked the power supply pins red > (for VDD and VDDQ) and the ground pins blue (for the VSS and VSSQ). I > used this, because it's one of the best examples for what i want to > show and it has very little circuitry around that would distract or > make my point less clear. > > The first thing that strikes the eye is, that there are only 4 > capacitors around the chip while it has 8 power supply pins. And even > worse, those 4 capacitors are shared with the two adjacent SRAM > chips. (effectively halfing the number of capacitors "seen" by a > chip) > > The next thing you should notice is, that there isnt a via visible > for each power or ground pin. This suggests that only one via > (underneath the chip) has been used to connect the pin to it's > power/ground plane. You can also spot places where the same via is > used for two pins. .. > That's the theory. > > Now to the practical stuff: > > Because of the "spiky" current consumption of digital logic it has > become custom in the field of electronics to attach an 100nF > capacitor to each power supply pin, to ensure the power supply has a > low inductance and low resistance "power source" for the switching > time. This has been done since at least the 1970s, when the first > 74xx logic family appeared. You can see this still in DIL sockets > sold with integrated 100nF capacitors. The capacitor is connected > directly between a power and a ground pin if possible, to ensure > minimal resistance between the capacitor and the chip. You cannot > group those capacitors together at one pin and just connect the other > pins to the power supply and ground, because the wires and vias will > have a resistance an (more importantly) an inductance that can not be > neglected. For fast digital chips, which have very high frequency > components on the power supply pins, it became custom to connect a > 10nF capacitor directly at the pin and a 100nF adjacent to it. This > is because even those tiny capacitors have an inductance. And due the > internal structure this inductance becomes dominating above the so > called self resonance frequency. This self resonance frequency is > higher for smaller value capacitors, making them better suited for > high frequency applications. The larger capacitor is then used to > provide the energy, while the smaller "eats" the spikes. > > Also, for high current chips like SRAM chips, you generally use a > higher capacitor (somewhere in the range of 1-10uF) adjacent to the > chip, to catch the lower frequency components, or the bumbs so to > speak of, that the 100nF capacitors couldnt catch. The placement of > this capacitor is not so critical as it is "only" for the "low" > frequency components. But it should be still as near to the chip as > possible, and one capacitor per chip. > > Additionally, each power supply and ground pin is connected to their > planes in the middle of the board by two vias. This is done to reduce > the inductance that a via has. Using two vias in parallel halfes the > inductance. > > Ignoring this common engineering practices is generally a bad idea. > It will lead to so called ground bounces, where the local power > supply voltage at the chip decreases, due to inductance and > resistance in the wires/vias to the chip. And even worse: because the > inductance/resistance at the power supply and ground pins is not the > same, the chips voltage level will bounce around wildly depending on > how much current is flowing where. These ground bounces lead at best > to a decreased signal to noise ratio (higher bit error rate) and > intermediatly to bit errors. But in the worst case, it will lead to > the chip entering a improper operating state, where it because > dysfunctional (either not doing anything anymore or doing wild things > it shouldnt do, potentially leading to the destruction of itself or > other chips). > > You also do not share power supply and ground pins of chips, of which > you cannot ensure that they are switching at different times. In this > case, the SRAM chips will switch exactly at the same time, making the > ground bounce problem even worse. Sorry Attila, but you can't really apply design techniques from the TTL era to modern high speed designs with power planes, nowadays it's all a question about two things: 1) Inductance from planes to the chip die itself. 2) The planes's impedance from low to very high frequencies. It doesn't really matter how many capacitors there are close to the chip if the pins are connected to low impedance planes. And you can safely share vias if needed, the reason a DDR DRAM chip have many power pins is to reduce the inductance from plane to chip, on a tsop package the inductance due to the long distance from die to pin is much higher than the short distance from pin to via/plane. The net5501 have a seperate memory 2.5V power plane feed from a low impedance high speed linear regulator, with a total of 31 ceramic capacitors, incl. two 22uF ones. If the memory decoupling was the source of the crashes, how come your net5501 works just fine without the wlan card who have nothing to do with the memory ? Not even connected to the same power rail.... > There is a way to mitigate this problem a little bit, at least the > part of the problem that is caused by the output pin wire > capacitance. If you put a resistor (usually 10-30 Ohm) into the wire, > you "insulate" the capacitance at the down stream part from the > output pin, forming an R-C circuit. The R limits the amount of > current flowing into the capacitance downstream of the resistor. The > main disadvantage of this is that the switching time is increased by > the R-C time constant. A second disadvantage is, that you add two > additional pin capacitances (the one of the resistor) to the system. > Over all, this technique helps only if the capacitance of the wire or > of the "recipient" chips pin is significantly higher than the > "sender" chips pin and the part of the wire between the "sender" chip > and the resistor. You can see those resistors on the net5501 as small > resistor networks between the SRAM and the Geode chips. Please note > that: the resistors are on a short wire, hence the capacitance of the > wire is most likely below 10pF, probably in the range of 2-5pF. Also > note that the Geode chip has probably similar pin capacitance > characteristics as the SRAM chips. What is really interesting here > though, is that the top side and bottom side SRAM chips have > resistors of different values. The top side is 33 Ohm while the > bottom side is 22 Ohm. This is very unusual, as normally you'd chose > the same for all resistors, because the wires are usually routed to > have the same properties (same length, same capacitance, same > inductance). I can only guess that Soekris might have had problems > with the SRAM ground bounce and thus increased the resistor size on > the top to mitigate this. Sorry Attila, again you're completely off.... On modern high speed designs all signals are to be considered transmission lines.... So the 20x4 33R resistors on the top side are series termination resistors for the 64 data lines and associated 16 DM/DQS lines. And the 22R resistors on the bottom side are series termination resistors on the address and control lines, those have different characteristics. You really need to get your facts right before speculating.... > You can see this two problems of not heaving enough capcacitors and > the sharing of power supply pins between chips troughout the board. > Actually, i found it everywhere i cared to check. .. > > As you can tell, i'm quite pissed at all this, because Soren > personally made it a few times clear that he thinks that his design > is flawless, calling the power supply "rock solid". And in sometimes > roundabout ways, sometimes quite direct telling me that i'm an idiot > looking for hardware problems. What I'm trying to say is to start with most likely source of the problem, if you check a recent serial number you will notice that we now over about 11 years have manufactured and sold about 250.000 boards. So I have some experience and a have learned that the most common problem is less than perfect drivers, so that's where I start from when meeting problems with crashes. And it is a fact that the Linux VT6105M driver had bugs, reported to be fixed in Linux 3.3. And that the atheros and/or wlan drivers had/have bugs, don't know if fixed. Opgrade to Linux >= 3.3 and we can continue talking. > And consider that the net5501 is a very expensive board, it costs > 220USD, which is twice what PC-Engines wants for their Alix boards > (and you cannot tell me that a Swiss company has lower labor costs > than an US company or that it has lower quality. If anything, the > labor and production costs in Switzerland are higher). I would have > thought, that at these prices, one could expect a proper design, with > all due diligence. Again, check the facts: PC Engines boards are manufactured in Taiwan or China. Soekris boards are manufactured in Silicon Valley, USA. The cost of assembly alone is 5-10 times higher in USA than in the Far East, but we believe that the better quality is worth it. And yes, there is better quality, partly because we have full control on what parts goes into our boards, no random "just as good" chinese parts.... Best Regards, Soren Kristensen CEO & Chief Engineer Soekris Engineering, Inc. _______________________________________________ Soekris-tech mailing list [email protected] http://lists.soekris.com/mailman/listinfo/soekris-tech
