Module Name: src
Committed By: mrg
Date: Tue Feb 23 05:24:50 UTC 2010
Modified Files:
src/sys/arch/sparc64/include: ctlreg.h
Log Message:
add some bits to set to access all the cheetah dtlb/itlb's.
To generate a diff of this commit:
cvs rdiff -u -r1.51 -r1.52 src/sys/arch/sparc64/include/ctlreg.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/sparc64/include/ctlreg.h
diff -u src/sys/arch/sparc64/include/ctlreg.h:1.51 src/sys/arch/sparc64/include/ctlreg.h:1.52
--- src/sys/arch/sparc64/include/ctlreg.h:1.51 Sun Feb 21 00:57:44 2010
+++ src/sys/arch/sparc64/include/ctlreg.h Tue Feb 23 05:24:50 2010
@@ -1,4 +1,4 @@
-/* $NetBSD: ctlreg.h,v 1.51 2010/02/21 00:57:44 mrg Exp $ */
+/* $NetBSD: ctlreg.h,v 1.52 2010/02/23 05:24:50 mrg Exp $ */
/*
* Copyright (c) 1996-2002 Eduardo Horvath
@@ -374,6 +374,11 @@
#define TLB_SIZE_CHEETAH_D16 16
#define TLB_SIZE_CHEETAH_D512_0 512
#define TLB_SIZE_CHEETAH_D512_1 512
+#define TLB_CHEETAH_I16 (0 << 16)
+#define TLB_CHEETAH_I128 (2 << 16)
+#define TLB_CHEETAH_D16 (0 << 16)
+#define TLB_CHEETAH_D512_0 (2 << 16)
+#define TLB_CHEETAH_D512_1 (3 << 16)
/*
* Interrupt registers. This really gets hairy.
