Module Name: src
Committed By: msaitoh
Date: Thu Jun 27 05:55:40 UTC 2019
Modified Files:
src/sys/dev/pci/ixgbe: if_sriov.c ix_txrx.c ixgbe.c ixgbe.h ixgbe_api.c
ixgbe_api.h ixgbe_common.c ixgbe_common.h ixgbe_mbx.c ixgbe_mbx.h
ixgbe_netmap.c ixgbe_type.h
Log Message:
Sync with FreeBSD ix-3.3.8 part 1. No functional change in this part:
- Move ixgbe_toggle_txdctl() to ixgbe_common.c and modify a bit.
No functional change because this function is currently used for SR-IOV
and it's not used in NetBSD.
- Some modification to match the latest netmap API.
- Modify ixgbe_hic_unlocked(). No functional change because neither
IXGBE_HOST_INTERFACE_APPLY_UPDATE_CMD(0x38) nor
IXGBE_HOST_INTERFACE_SHADOW_RAM_READ_CMD(0x31) are used.
- Add ixgbe_clear_mbx(). No functional change because this function is not
used yet.
- Add some not-yet-used register definitions.
- Whitespace fixes.
To generate a diff of this commit:
cvs rdiff -u -r1.5 -r1.6 src/sys/dev/pci/ixgbe/if_sriov.c
cvs rdiff -u -r1.52 -r1.53 src/sys/dev/pci/ixgbe/ix_txrx.c
cvs rdiff -u -r1.188 -r1.189 src/sys/dev/pci/ixgbe/ixgbe.c
cvs rdiff -u -r1.54 -r1.55 src/sys/dev/pci/ixgbe/ixgbe.h
cvs rdiff -u -r1.22 -r1.23 src/sys/dev/pci/ixgbe/ixgbe_api.c \
src/sys/dev/pci/ixgbe/ixgbe_common.c
cvs rdiff -u -r1.14 -r1.15 src/sys/dev/pci/ixgbe/ixgbe_api.h
cvs rdiff -u -r1.13 -r1.14 src/sys/dev/pci/ixgbe/ixgbe_common.h \
src/sys/dev/pci/ixgbe/ixgbe_mbx.h
cvs rdiff -u -r1.10 -r1.11 src/sys/dev/pci/ixgbe/ixgbe_mbx.c
cvs rdiff -u -r1.1 -r1.2 src/sys/dev/pci/ixgbe/ixgbe_netmap.c
cvs rdiff -u -r1.38 -r1.39 src/sys/dev/pci/ixgbe/ixgbe_type.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/dev/pci/ixgbe/if_sriov.c
diff -u src/sys/dev/pci/ixgbe/if_sriov.c:1.5 src/sys/dev/pci/ixgbe/if_sriov.c:1.6
--- src/sys/dev/pci/ixgbe/if_sriov.c:1.5 Thu Dec 6 13:25:02 2018
+++ src/sys/dev/pci/ixgbe/if_sriov.c Thu Jun 27 05:55:40 2019
@@ -264,50 +264,6 @@ ixgbe_clear_vfmbmem(struct ixgbe_hw *hw,
} /* ixgbe_clear_vfmbmem */
-static void
-ixgbe_toggle_txdctl(struct ixgbe_hw *hw, struct ixgbe_vf *vf)
-{
- uint32_t vf_index, offset, reg;
- uint8_t queue_count, i;
-
- IXGBE_CORE_LOCK_ASSERT(adapter);
-
- vf_index = IXGBE_VF_INDEX(vf->pool);
-
- /* Determine number of queues by checking
- * number of virtual functions */
- reg = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
- switch (reg & IXGBE_GCR_EXT_VT_MODE_MASK) {
- case IXGBE_GCR_EXT_VT_MODE_64:
- queue_count = 2;
- break;
- case IXGBE_GCR_EXT_VT_MODE_32:
- queue_count = 4;
- break;
- default:
- return;
- }
-
- /* Toggle queues */
- for (i = 0; i < queue_count; ++i) {
- /* Calculate offset of current queue */
- offset = queue_count * vf_index + i;
-
- /* Enable queue */
- reg = IXGBE_READ_REG(hw, IXGBE_PVFTXDCTL(offset));
- reg |= IXGBE_TXDCTL_ENABLE;
- IXGBE_WRITE_REG(hw, IXGBE_PVFTXDCTL(offset), reg);
- IXGBE_WRITE_FLUSH(hw);
-
- /* Disable queue */
- reg = IXGBE_READ_REG(hw, IXGBE_PVFTXDCTL(offset));
- reg &= ~IXGBE_TXDCTL_ENABLE;
- IXGBE_WRITE_REG(hw, IXGBE_PVFTXDCTL(offset), reg);
- IXGBE_WRITE_FLUSH(hw);
- }
-} /* ixgbe_toggle_txdctl */
-
-
static boolean_t
ixgbe_vf_frame_size_compatible(struct adapter *adapter, struct ixgbe_vf *vf)
{
@@ -364,7 +320,7 @@ ixgbe_process_vf_reset(struct adapter *a
ixgbe_clear_rar(&adapter->hw, vf->rar_index);
ixgbe_clear_vfmbmem(&adapter->hw, vf);
- ixgbe_toggle_txdctl(&adapter->hw, vf);
+ ixgbe_toggle_txdctl(&adapter->hw, IXGBE_VF_INDEX(vf->pool));
vf->api_ver = IXGBE_API_VER_UNKNOWN;
} /* ixgbe_process_vf_reset */
Index: src/sys/dev/pci/ixgbe/ix_txrx.c
diff -u src/sys/dev/pci/ixgbe/ix_txrx.c:1.52 src/sys/dev/pci/ixgbe/ix_txrx.c:1.53
--- src/sys/dev/pci/ixgbe/ix_txrx.c:1.52 Fri Feb 22 06:49:15 2019
+++ src/sys/dev/pci/ixgbe/ix_txrx.c Thu Jun 27 05:55:40 2019
@@ -1,4 +1,4 @@
-/* $NetBSD: ix_txrx.c,v 1.52 2019/02/22 06:49:15 msaitoh Exp $ */
+/* $NetBSD: ix_txrx.c,v 1.53 2019/06/27 05:55:40 msaitoh Exp $ */
/******************************************************************************
@@ -694,7 +694,7 @@ ixgbe_setup_transmit_ring(struct tx_ring
* netmap_idx_n2k() handles wraparounds properly.
*/
if ((adapter->feat_en & IXGBE_FEATURE_NETMAP) && slot) {
- int si = netmap_idx_n2k(&na->tx_rings[txr->me], i);
+ int si = netmap_idx_n2k(na->tx_rings[txr->me], i);
netmap_load_map(na, txr->txtag,
txbuf->map, NMB(na, slot + si));
}
@@ -1105,7 +1105,7 @@ ixgbe_txeof(struct tx_ring *txr)
if ((adapter->feat_en & IXGBE_FEATURE_NETMAP) &&
(adapter->ifp->if_capenable & IFCAP_NETMAP)) {
struct netmap_adapter *na = NA(adapter->ifp);
- struct netmap_kring *kring = &na->tx_rings[txr->me];
+ struct netmap_kring *kring = na->tx_rings[txr->me];
txd = txr->tx_base;
bus_dmamap_sync(txr->txdma.dma_tag, txr->txdma.dma_map,
BUS_DMASYNC_POSTREAD);
@@ -1123,9 +1123,8 @@ ixgbe_txeof(struct tx_ring *txr)
* - the driver ignores tx interrupts unless netmap_mitigate=0
* or the slot has the DD bit set.
*/
- if (!netmap_mitigate ||
- (kring->nr_kflags < kring->nkr_num_slots &&
- txd[kring->nr_kflags].wb.status & IXGBE_TXD_STAT_DD)) {
+ if (kring->nr_kflags < kring->nkr_num_slots &&
+ txd[kring->nr_kflags].wb.status & IXGBE_TXD_STAT_DD) {
netmap_tx_irq(ifp, txr->me);
}
return false;
@@ -1405,7 +1404,7 @@ update:
static int
ixgbe_allocate_receive_buffers(struct rx_ring *rxr)
{
- struct adapter *adapter = rxr->adapter;
+ struct adapter *adapter = rxr->adapter;
device_t dev = adapter->dev;
struct ixgbe_rx_buf *rxbuf;
int bsize, error;
@@ -1530,7 +1529,7 @@ ixgbe_setup_receive_ring(struct rx_ring
* an mbuf, so end the block with a continue;
*/
if ((adapter->feat_en & IXGBE_FEATURE_NETMAP) && slot) {
- int sj = netmap_idx_n2k(&na->rx_rings[rxr->me], j);
+ int sj = netmap_idx_n2k(na->rx_rings[rxr->me], j);
uint64_t paddr;
void *addr;
@@ -1827,7 +1826,7 @@ ixgbe_rxeof(struct ix_queue *que)
u16 len;
u16 vtag = 0;
bool eop;
-
+
/* Sync the ring. */
ixgbe_dmamap_sync(rxr->rxdma.dma_tag, rxr->rxdma.dma_map,
BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
@@ -2307,7 +2306,7 @@ ixgbe_allocate_queues(struct adapter *ad
/*
* Next the RX queues...
- */
+ */
rsize = roundup2(adapter->num_rx_desc * sizeof(union ixgbe_adv_rx_desc),
DBA_ALIGN);
for (int i = 0; i < adapter->num_queues; i++, rxconf++) {
Index: src/sys/dev/pci/ixgbe/ixgbe.c
diff -u src/sys/dev/pci/ixgbe/ixgbe.c:1.188 src/sys/dev/pci/ixgbe/ixgbe.c:1.189
--- src/sys/dev/pci/ixgbe/ixgbe.c:1.188 Tue Jun 4 09:43:15 2019
+++ src/sys/dev/pci/ixgbe/ixgbe.c Thu Jun 27 05:55:40 2019
@@ -1,4 +1,4 @@
-/* $NetBSD: ixgbe.c,v 1.188 2019/06/04 09:43:15 msaitoh Exp $ */
+/* $NetBSD: ixgbe.c,v 1.189 2019/06/27 05:55:40 msaitoh Exp $ */
/******************************************************************************
@@ -81,7 +81,7 @@
* Driver version
************************************************************************/
static const char ixgbe_driver_version[] = "4.0.1-k";
-/* XXX NetBSD: + 3.3.6 */
+/* XXX NetBSD: + 3.3.8 */
/************************************************************************
* PCI Device ID Table
@@ -4019,7 +4019,7 @@ ixgbe_init_locked(struct adapter *adapte
if ((adapter->feat_en & IXGBE_FEATURE_NETMAP) &&
(ifp->if_capenable & IFCAP_NETMAP)) {
struct netmap_adapter *na = NA(adapter->ifp);
- struct netmap_kring *kring = &na->rx_rings[i];
+ struct netmap_kring *kring = na->rx_rings[i];
int t = na->num_rx_desc - 1 - nm_kr_rxspace(kring);
IXGBE_WRITE_REG(hw, IXGBE_RDT(rxr->me), t);
Index: src/sys/dev/pci/ixgbe/ixgbe.h
diff -u src/sys/dev/pci/ixgbe/ixgbe.h:1.54 src/sys/dev/pci/ixgbe/ixgbe.h:1.55
--- src/sys/dev/pci/ixgbe/ixgbe.h:1.54 Fri Feb 22 06:49:15 2019
+++ src/sys/dev/pci/ixgbe/ixgbe.h Thu Jun 27 05:55:40 2019
@@ -1,4 +1,4 @@
-/* $NetBSD: ixgbe.h,v 1.54 2019/02/22 06:49:15 msaitoh Exp $ */
+/* $NetBSD: ixgbe.h,v 1.55 2019/06/27 05:55:40 msaitoh Exp $ */
/******************************************************************************
SPDX-License-Identifier: BSD-3-Clause
@@ -240,7 +240,7 @@
#endif
/*
- * Interrupt Moderation parameters
+ * Interrupt Moderation parameters
*/
#define IXGBE_LOW_LATENCY 128
#define IXGBE_AVE_LATENCY 400
@@ -348,7 +348,7 @@ struct ix_queue {
* The transmit ring, one per queue
*/
struct tx_ring {
- struct adapter *adapter;
+ struct adapter *adapter;
kmutex_t tx_mtx;
u32 me;
u32 tail;
@@ -396,7 +396,7 @@ struct tx_ring {
* The Receive ring, one per rx queue
*/
struct rx_ring {
- struct adapter *adapter;
+ struct adapter *adapter;
kmutex_t rx_mtx;
u32 me;
u32 tail;
@@ -408,8 +408,8 @@ struct rx_ring {
bool lro_enabled;
bool hw_rsc;
bool vtag_strip;
- u16 next_to_refresh;
- u16 next_to_check;
+ u16 next_to_refresh;
+ u16 next_to_check;
u16 num_desc;
u16 mbuf_sz;
#if 0
@@ -678,11 +678,11 @@ struct adapter {
"\nControl advertised link speed using these flags:\n" \
"\t0x01 - advertise 100M\n" \
"\t0x02 - advertise 1G\n" \
- "\t0x04 - advertise 10G\n" \
- "\t0x08 - advertise 10M\n" \
- "\t0x10 - advertise 2.5G\n" \
- "\t0x20 - advertise 5G\n\n" \
- "\t5G, 2.5G, 100M and 10M are only supported on certain adapters."
+ "\t0x04 - advertise 10G\n" \
+ "\t0x08 - advertise 10M\n" \
+ "\t0x10 - advertise 2.5G\n" \
+ "\t0x20 - advertise 5G\n\n" \
+ "\t5G, 2.5G, 100M and 10M are only supported on certain adapters."
#define IXGBE_SYSCTL_DESC_SET_FC \
"\nSet flow control mode using these values:\n" \
Index: src/sys/dev/pci/ixgbe/ixgbe_api.c
diff -u src/sys/dev/pci/ixgbe/ixgbe_api.c:1.22 src/sys/dev/pci/ixgbe/ixgbe_api.c:1.23
--- src/sys/dev/pci/ixgbe/ixgbe_api.c:1.22 Thu Dec 6 13:25:02 2018
+++ src/sys/dev/pci/ixgbe/ixgbe_api.c Thu Jun 27 05:55:40 2019
@@ -1,4 +1,4 @@
-/* $NetBSD: ixgbe_api.c,v 1.22 2018/12/06 13:25:02 msaitoh Exp $ */
+/* $NetBSD: ixgbe_api.c,v 1.23 2019/06/27 05:55:40 msaitoh Exp $ */
/******************************************************************************
SPDX-License-Identifier: BSD-3-Clause
@@ -1106,6 +1106,19 @@ s32 ixgbe_set_vlvf(struct ixgbe_hw *hw,
}
/**
+ * ixgbe_toggle_txdctl - Toggle VF's queues
+ * @hw: pointer to hardware structure
+ * @vind: VMDq pool index
+ *
+ * Enable and disable each queue in VF.
+ */
+s32 ixgbe_toggle_txdctl(struct ixgbe_hw *hw, u32 vind)
+{
+ return ixgbe_call_func(hw, hw->mac.ops.toggle_txdctl, (hw,
+ vind), IXGBE_NOT_IMPLEMENTED);
+}
+
+/**
* ixgbe_fc_enable - Enable flow control
* @hw: pointer to hardware structure
*
Index: src/sys/dev/pci/ixgbe/ixgbe_common.c
diff -u src/sys/dev/pci/ixgbe/ixgbe_common.c:1.22 src/sys/dev/pci/ixgbe/ixgbe_common.c:1.23
--- src/sys/dev/pci/ixgbe/ixgbe_common.c:1.22 Wed Apr 4 08:59:22 2018
+++ src/sys/dev/pci/ixgbe/ixgbe_common.c Thu Jun 27 05:55:40 2019
@@ -1,4 +1,4 @@
-/* $NetBSD: ixgbe_common.c,v 1.22 2018/04/04 08:59:22 msaitoh Exp $ */
+/* $NetBSD: ixgbe_common.c,v 1.23 2019/06/27 05:55:40 msaitoh Exp $ */
/******************************************************************************
SPDX-License-Identifier: BSD-3-Clause
@@ -136,6 +136,7 @@ s32 ixgbe_init_ops_generic(struct ixgbe_
mac->ops.init_uta_tables = NULL;
mac->ops.enable_rx = ixgbe_enable_rx_generic;
mac->ops.disable_rx = ixgbe_disable_rx_generic;
+ mac->ops.toggle_txdctl = ixgbe_toggle_txdctl_generic;
/* Flow Control */
mac->ops.fc_enable = ixgbe_fc_enable_generic;
@@ -4163,6 +4164,61 @@ s32 ixgbe_clear_vfta_generic(struct ixgb
}
/**
+ * ixgbe_toggle_txdctl_generic - Toggle VF's queues
+ * @hw: pointer to hardware structure
+ * @vf_number: VF index
+ *
+ * Enable and disable each queue in VF.
+ */
+s32 ixgbe_toggle_txdctl_generic(struct ixgbe_hw *hw, u32 vf_number)
+{
+ u8 queue_count, i;
+ u32 offset, reg;
+
+ if (vf_number > 63)
+ return IXGBE_ERR_PARAM;
+
+ /*
+ * Determine number of queues by checking
+ * number of virtual functions
+ */
+ reg = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
+ switch (reg & IXGBE_GCR_EXT_VT_MODE_MASK) {
+ case IXGBE_GCR_EXT_VT_MODE_64:
+ queue_count = 2;
+ break;
+ case IXGBE_GCR_EXT_VT_MODE_32:
+ queue_count = 4;
+ break;
+ case IXGBE_GCR_EXT_VT_MODE_16:
+ queue_count = 8;
+ break;
+ default:
+ return IXGBE_ERR_CONFIG;
+ }
+
+ /* Toggle queues */
+ for (i = 0; i < queue_count; ++i) {
+ /* Calculate offset of current queue */
+ offset = queue_count * vf_number + i;
+
+ /* Enable queue */
+ reg = IXGBE_READ_REG(hw, IXGBE_PVFTXDCTL(offset));
+ reg |= IXGBE_TXDCTL_ENABLE;
+ IXGBE_WRITE_REG(hw, IXGBE_PVFTXDCTL(offset), reg);
+ IXGBE_WRITE_FLUSH(hw);
+
+ /* Disable queue */
+ reg = IXGBE_READ_REG(hw, IXGBE_PVFTXDCTL(offset));
+ reg &= ~IXGBE_TXDCTL_ENABLE;
+ IXGBE_WRITE_REG(hw, IXGBE_PVFTXDCTL(offset), reg);
+ IXGBE_WRITE_FLUSH(hw);
+ }
+
+ return IXGBE_SUCCESS;
+}
+
+/**
* ixgbe_need_crosstalk_fix - Determine if we need to do cross talk fix
* @hw: pointer to hardware structure
*
@@ -4579,11 +4635,18 @@ s32 ixgbe_hic_unlocked(struct ixgbe_hw *
msec_delay(1);
}
+ /* For each command except "Apply Update" perform
+ * status checks in the HICR registry.
+ */
+ if ((buffer[0] & IXGBE_HOST_INTERFACE_MASK_CMD) ==
+ IXGBE_HOST_INTERFACE_APPLY_UPDATE_CMD)
+ return IXGBE_SUCCESS;
+
/* Check command completion */
if ((timeout && i == timeout) ||
!(IXGBE_READ_REG(hw, IXGBE_HICR) & IXGBE_HICR_SV)) {
ERROR_REPORT1(IXGBE_ERROR_CAUTION,
- "Command has failed with no status valid.\n");
+ "Command has failed with no status valid.\n");
return IXGBE_ERR_HOST_INTERFACE_COMMAND;
}
@@ -4651,7 +4714,7 @@ s32 ixgbe_host_interface_command(struct
* Read Flash command requires reading buffer length from
* two byes instead of one byte
*/
- if (resp->cmd == 0x30) {
+ if (resp->cmd == 0x30 || resp->cmd == 0x31) {
for (; bi < dword_len + 2; bi++) {
buffer[bi] = IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG,
bi);
Index: src/sys/dev/pci/ixgbe/ixgbe_api.h
diff -u src/sys/dev/pci/ixgbe/ixgbe_api.h:1.14 src/sys/dev/pci/ixgbe/ixgbe_api.h:1.15
--- src/sys/dev/pci/ixgbe/ixgbe_api.h:1.14 Thu Dec 6 13:25:02 2018
+++ src/sys/dev/pci/ixgbe/ixgbe_api.h Thu Jun 27 05:55:40 2019
@@ -1,4 +1,4 @@
-/* $NetBSD: ixgbe_api.h,v 1.14 2018/12/06 13:25:02 msaitoh Exp $ */
+/* $NetBSD: ixgbe_api.h,v 1.15 2019/06/27 05:55:40 msaitoh Exp $ */
/******************************************************************************
SPDX-License-Identifier: BSD-3-Clause
@@ -133,6 +133,7 @@ s32 ixgbe_set_vfta(struct ixgbe_hw *hw,
s32 ixgbe_set_vlvf(struct ixgbe_hw *hw, u32 vlan, u32 vind,
bool vlan_on, u32 *vfta_delta, u32 vfta,
bool vlvf_bypass);
+s32 ixgbe_toggle_txdctl(struct ixgbe_hw *hw, u32 vind);
s32 ixgbe_fc_enable(struct ixgbe_hw *hw);
s32 ixgbe_setup_fc(struct ixgbe_hw *hw);
s32 ixgbe_set_fw_drv_ver(struct ixgbe_hw *hw, u8 maj, u8 min, u8 build,
Index: src/sys/dev/pci/ixgbe/ixgbe_common.h
diff -u src/sys/dev/pci/ixgbe/ixgbe_common.h:1.13 src/sys/dev/pci/ixgbe/ixgbe_common.h:1.14
--- src/sys/dev/pci/ixgbe/ixgbe_common.h:1.13 Wed Apr 4 08:59:22 2018
+++ src/sys/dev/pci/ixgbe/ixgbe_common.h Thu Jun 27 05:55:40 2019
@@ -1,4 +1,4 @@
-/* $NetBSD: ixgbe_common.h,v 1.13 2018/04/04 08:59:22 msaitoh Exp $ */
+/* $NetBSD: ixgbe_common.h,v 1.14 2019/06/27 05:55:40 msaitoh Exp $ */
/******************************************************************************
SPDX-License-Identifier: BSD-3-Clause
@@ -146,6 +146,7 @@ s32 ixgbe_set_vlvf_generic(struct ixgbe_
bool vlvf_bypass);
s32 ixgbe_clear_vfta_generic(struct ixgbe_hw *hw);
s32 ixgbe_find_vlvf_slot(struct ixgbe_hw *hw, u32 vlan, bool vlvf_bypass);
+s32 ixgbe_toggle_txdctl_generic(struct ixgbe_hw *hw, u32 vind);
s32 ixgbe_check_mac_link_generic(struct ixgbe_hw *hw,
ixgbe_link_speed *speed,
Index: src/sys/dev/pci/ixgbe/ixgbe_mbx.h
diff -u src/sys/dev/pci/ixgbe/ixgbe_mbx.h:1.13 src/sys/dev/pci/ixgbe/ixgbe_mbx.h:1.14
--- src/sys/dev/pci/ixgbe/ixgbe_mbx.h:1.13 Wed Apr 4 08:13:07 2018
+++ src/sys/dev/pci/ixgbe/ixgbe_mbx.h Thu Jun 27 05:55:40 2019
@@ -1,4 +1,4 @@
-/* $NetBSD: ixgbe_mbx.h,v 1.13 2018/04/04 08:13:07 msaitoh Exp $ */
+/* $NetBSD: ixgbe_mbx.h,v 1.14 2019/06/27 05:55:40 msaitoh Exp $ */
/******************************************************************************
SPDX-License-Identifier: BSD-3-Clause
@@ -155,6 +155,7 @@ enum ixgbevf_xcast_modes {
#define IXGBE_VF_MBX_INIT_TIMEOUT 2000 /* number of retries on mailbox */
#define IXGBE_VF_MBX_INIT_DELAY 500 /* microseconds between retries */
+s32 ixgbe_clear_mbx(struct ixgbe_hw *hw, u16 vf_number);
void ixgbe_init_mbx_ops_generic(struct ixgbe_hw *hw);
void ixgbe_init_mbx_params_vf(struct ixgbe_hw *);
void ixgbe_init_mbx_params_pf(struct ixgbe_hw *);
Index: src/sys/dev/pci/ixgbe/ixgbe_mbx.c
diff -u src/sys/dev/pci/ixgbe/ixgbe_mbx.c:1.10 src/sys/dev/pci/ixgbe/ixgbe_mbx.c:1.11
--- src/sys/dev/pci/ixgbe/ixgbe_mbx.c:1.10 Wed Apr 4 08:13:07 2018
+++ src/sys/dev/pci/ixgbe/ixgbe_mbx.c Thu Jun 27 05:55:40 2019
@@ -1,4 +1,4 @@
-/* $NetBSD: ixgbe_mbx.c,v 1.10 2018/04/04 08:13:07 msaitoh Exp $ */
+/* $NetBSD: ixgbe_mbx.c,v 1.11 2019/06/27 05:55:40 msaitoh Exp $ */
/******************************************************************************
SPDX-License-Identifier: BSD-3-Clause
@@ -39,6 +39,26 @@
#include "ixgbe_mbx.h"
/**
+ * ixgbe_clear_mbx - Clear Mailbox Memory
+ * @hw: pointer to the HW structure
+ * @vf_number: id of mailbox to write
+ *
+ * Set VFMBMEM of given VF to 0x0.
+ **/
+s32 ixgbe_clear_mbx(struct ixgbe_hw *hw, u16 vf_number)
+{
+ struct ixgbe_mbx_info *mbx = &hw->mbx;
+ s32 ret_val = IXGBE_SUCCESS;
+
+ DEBUGFUNC("ixgbe_clear_mbx");
+
+ if (mbx->ops.clear)
+ ret_val = mbx->ops.clear(hw, vf_number);
+
+ return ret_val;
+}
+
+/**
* ixgbe_poll_for_msg - Wait for message notification
* @hw: pointer to the HW structure
* @mbx_id: id of mailbox to write
@@ -408,6 +428,7 @@ void ixgbe_init_mbx_params_vf(struct ixg
mbx->ops.check_for_msg = ixgbe_check_for_msg_vf;
mbx->ops.check_for_ack = ixgbe_check_for_ack_vf;
mbx->ops.check_for_rst = ixgbe_check_for_rst_vf;
+ mbx->ops.clear = NULL;
mbx->stats.msgs_tx.ev_count = 0;
mbx->stats.msgs_rx.ev_count = 0;
@@ -625,6 +646,27 @@ out_no_read:
}
/**
+ * ixgbe_clear_mbx_pf - Clear Mailbox Memory
+ * @hw: pointer to the HW structure
+ * @vf_number: the VF index
+ *
+ * Set VFMBMEM of given VF to 0x0.
+ **/
+static s32 ixgbe_clear_mbx_pf(struct ixgbe_hw *hw, u16 vf_number)
+{
+ u16 mbx_size = hw->mbx.size;
+ u16 i;
+
+ if (vf_number > 63)
+ return IXGBE_ERR_PARAM;
+
+ for (i = 0; i < mbx_size; ++i)
+ IXGBE_WRITE_REG_ARRAY(hw, IXGBE_PFMBMEM(vf_number), i, 0x0);
+
+ return IXGBE_SUCCESS;
+}
+
+/**
* ixgbe_init_mbx_params_pf - set initial values for pf mailbox
* @hw: pointer to the HW structure
*
@@ -653,6 +695,7 @@ void ixgbe_init_mbx_params_pf(struct ixg
mbx->ops.check_for_msg = ixgbe_check_for_msg_pf;
mbx->ops.check_for_ack = ixgbe_check_for_ack_pf;
mbx->ops.check_for_rst = ixgbe_check_for_rst_pf;
+ mbx->ops.clear = ixgbe_clear_mbx_pf;
mbx->stats.msgs_tx.ev_count = 0;
mbx->stats.msgs_rx.ev_count = 0;
Index: src/sys/dev/pci/ixgbe/ixgbe_netmap.c
diff -u src/sys/dev/pci/ixgbe/ixgbe_netmap.c:1.1 src/sys/dev/pci/ixgbe/ixgbe_netmap.c:1.2
--- src/sys/dev/pci/ixgbe/ixgbe_netmap.c:1.1 Wed Aug 30 08:49:18 2017
+++ src/sys/dev/pci/ixgbe/ixgbe_netmap.c Thu Jun 27 05:55:40 2019
@@ -408,7 +408,6 @@ ixgbe_netmap_rxsync(struct netmap_kring
*/
if (netmap_no_pendintr || force_update) {
int crclen = (ix_crcstrip) ? 0 : 4;
- uint16_t slot_flags = kring->nkr_slot_flags;
nic_i = rxr->next_to_check; // or also k2n(kring->nr_hwtail)
nm_i = netmap_idx_n2k(kring, nic_i);
@@ -420,7 +419,7 @@ ixgbe_netmap_rxsync(struct netmap_kring
if ((staterr & IXGBE_RXD_STAT_DD) == 0)
break;
ring->slot[nm_i].len = le16toh(curr->wb.upper.length) - crclen;
- ring->slot[nm_i].flags = slot_flags;
+ ring->slot[nm_i].flags = 0;
bus_dmamap_sync(rxr->ptag,
rxr->rx_buffers[nic_i].pmap, BUS_DMASYNC_POSTREAD);
nm_i = nm_next(nm_i, lim);
Index: src/sys/dev/pci/ixgbe/ixgbe_type.h
diff -u src/sys/dev/pci/ixgbe/ixgbe_type.h:1.38 src/sys/dev/pci/ixgbe/ixgbe_type.h:1.39
--- src/sys/dev/pci/ixgbe/ixgbe_type.h:1.38 Tue Mar 5 09:42:36 2019
+++ src/sys/dev/pci/ixgbe/ixgbe_type.h Thu Jun 27 05:55:40 2019
@@ -1,4 +1,4 @@
-/* $NetBSD: ixgbe_type.h,v 1.38 2019/03/05 09:42:36 msaitoh Exp $ */
+/* $NetBSD: ixgbe_type.h,v 1.39 2019/06/27 05:55:40 msaitoh Exp $ */
/******************************************************************************
SPDX-License-Identifier: BSD-3-Clause
@@ -877,6 +877,10 @@ struct ixgbe_dmac_config {
#define IXGBE_RTTDQSEL 0x04904
#define IXGBE_RTTDT1C 0x04908
#define IXGBE_RTTDT1S 0x0490C
+#define IXGBE_RTTQCNCR 0x08B00
+#define IXGBE_RTTQCNTG 0x04A90
+#define IXGBE_RTTBCNRD 0x0498C
+#define IXGBE_RTTQCNRR 0x0498C
#define IXGBE_RTTDTECC 0x04990
#define IXGBE_RTTDTECC_NO_BCN 0x00000100
@@ -887,6 +891,7 @@ struct ixgbe_dmac_config {
#define IXGBE_RTTBCNRC_RF_INT_MASK \
(IXGBE_RTTBCNRC_RF_DEC_MASK << IXGBE_RTTBCNRC_RF_INT_SHIFT)
#define IXGBE_RTTBCNRM 0x04980
+#define IXGBE_RTTQCNRM 0x04980
/* BCN (for DCB) Registers */
#define IXGBE_RTTBCNRS 0x04988
@@ -4050,6 +4055,7 @@ struct ixgbe_mac_operations {
s32 (*init_uta_tables)(struct ixgbe_hw *);
void (*set_mac_anti_spoofing)(struct ixgbe_hw *, bool, int);
void (*set_vlan_anti_spoofing)(struct ixgbe_hw *, bool, int);
+ s32 (*toggle_txdctl)(struct ixgbe_hw *hw, u32 vf_index);
/* Flow Control */
s32 (*fc_enable)(struct ixgbe_hw *);
@@ -4209,6 +4215,7 @@ struct ixgbe_mbx_operations {
s32 (*check_for_msg)(struct ixgbe_hw *, u16);
s32 (*check_for_ack)(struct ixgbe_hw *, u16);
s32 (*check_for_rst)(struct ixgbe_hw *, u16);
+ s32 (*clear)(struct ixgbe_hw *hw, u16 vf_number);
};
struct ixgbe_mbx_stats {
@@ -4509,4 +4516,16 @@ struct ixgbe_bypass_eeprom {
#define IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD \
(0x1F << IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD_SHIFT)
+/* Code Command (Flash I/F Interface) */
+#define IXGBE_HOST_INTERFACE_FLASH_READ_CMD 0x30
+#define IXGBE_HOST_INTERFACE_SHADOW_RAM_READ_CMD 0x31
+#define IXGBE_HOST_INTERFACE_FLASH_WRITE_CMD 0x32
+#define IXGBE_HOST_INTERFACE_SHADOW_RAM_WRITE_CMD 0x33
+#define IXGBE_HOST_INTERFACE_FLASH_MODULE_UPDATE_CMD 0x34
+#define IXGBE_HOST_INTERFACE_FLASH_BLOCK_EREASE_CMD 0x35
+#define IXGBE_HOST_INTERFACE_SHADOW_RAM_DUMP_CMD 0x36
+#define IXGBE_HOST_INTERFACE_FLASH_INFO_CMD 0x37
+#define IXGBE_HOST_INTERFACE_APPLY_UPDATE_CMD 0x38
+#define IXGBE_HOST_INTERFACE_MASK_CMD 0x000000FF
+
#endif /* _IXGBE_TYPE_H_ */
