Module Name: src
Committed By: hkenken
Date: Mon Jul 22 11:44:01 UTC 2019
Modified Files:
src/sys/arch/arm/imx: imx6_ahcisata.c imx6_iomuxreg.h
Log Message:
Change register assignments.
To generate a diff of this commit:
cvs rdiff -u -r1.9 -r1.10 src/sys/arch/arm/imx/imx6_ahcisata.c
cvs rdiff -u -r1.4 -r1.5 src/sys/arch/arm/imx/imx6_iomuxreg.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/imx/imx6_ahcisata.c
diff -u src/sys/arch/arm/imx/imx6_ahcisata.c:1.9 src/sys/arch/arm/imx/imx6_ahcisata.c:1.10
--- src/sys/arch/arm/imx/imx6_ahcisata.c:1.9 Thu Jun 20 08:16:19 2019
+++ src/sys/arch/arm/imx/imx6_ahcisata.c Mon Jul 22 11:44:01 2019
@@ -1,4 +1,4 @@
-/* $NetBSD: imx6_ahcisata.c,v 1.9 2019/06/20 08:16:19 hkenken Exp $ */
+/* $NetBSD: imx6_ahcisata.c,v 1.10 2019/07/22 11:44:01 hkenken Exp $ */
/*
* Copyright (c) 2014 Ryo Shimizu <r...@nerv.org>
@@ -27,7 +27,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: imx6_ahcisata.c,v 1.9 2019/06/20 08:16:19 hkenken Exp $");
+__KERNEL_RCSID(0, "$NetBSD: imx6_ahcisata.c,v 1.10 2019/07/22 11:44:01 hkenken Exp $");
#include "locators.h"
#include "opt_imx.h"
@@ -289,26 +289,26 @@ imx6_ahcisata_init(struct imx_ahci_softc
v = iomux_read(IOMUX_GPR13);
/* clear */
- v &= ~(IOMUX_GPR13_SATA_PHY_8(7) |
- IOMUX_GPR13_SATA_PHY_7(0x1f) |
- IOMUX_GPR13_SATA_PHY_6(7) |
- IOMUX_GPR13_SATA_SPEED(1) |
- IOMUX_GPR13_SATA_PHY_5(1) |
- IOMUX_GPR13_SATA_PHY_4(7) |
- IOMUX_GPR13_SATA_PHY_3(0xf) |
- IOMUX_GPR13_SATA_PHY_2(0x1f) |
- IOMUX_GPR13_SATA_PHY_1(1) |
- IOMUX_GPR13_SATA_PHY_0(1));
+ v &= ~(IOMUX_GPR13_SATA_PHY_8 |
+ IOMUX_GPR13_SATA_PHY_7 |
+ IOMUX_GPR13_SATA_PHY_6 |
+ IOMUX_GPR13_SATA_SPEED |
+ IOMUX_GPR13_SATA_PHY_5 |
+ IOMUX_GPR13_SATA_PHY_4 |
+ IOMUX_GPR13_SATA_PHY_3 |
+ IOMUX_GPR13_SATA_PHY_2 |
+ IOMUX_GPR13_SATA_PHY_1 |
+ IOMUX_GPR13_SATA_PHY_0);
/* setting */
- v |= IOMUX_GPR13_SATA_PHY_8(5) | /* Rx 3.0db */
- IOMUX_GPR13_SATA_PHY_7(0x12) | /* Rx SATA2m */
- IOMUX_GPR13_SATA_PHY_6(3) | /* Rx DPLL mode */
- IOMUX_GPR13_SATA_SPEED(1) | /* 3.0GHz */
- IOMUX_GPR13_SATA_PHY_5(0) | /* SpreadSpectram */
- IOMUX_GPR13_SATA_PHY_4(4) | /* Tx Attenuation 9/16 */
- IOMUX_GPR13_SATA_PHY_3(0) | /* Tx Boost 0db */
- IOMUX_GPR13_SATA_PHY_2(0x11) | /* Tx Level 1.104V */
- IOMUX_GPR13_SATA_PHY_1(1); /* PLL clock enable */
+ v |= __SHIFTIN(5, IOMUX_GPR13_SATA_PHY_8); /* Rx 3.0db */
+ v |= __SHIFTIN(0x12, IOMUX_GPR13_SATA_PHY_7); /* Rx SATA2m */
+ v |= __SHIFTIN(3, IOMUX_GPR13_SATA_PHY_6); /* Rx DPLL mode */
+ v |= __SHIFTIN(1, IOMUX_GPR13_SATA_SPEED); /* 3.0GHz */
+ v |= __SHIFTIN(0, IOMUX_GPR13_SATA_PHY_5); /* SpreadSpectram */
+ v |= __SHIFTIN(4, IOMUX_GPR13_SATA_PHY_4); /* Tx Attenuation 9/16 */
+ v |= __SHIFTIN(0, IOMUX_GPR13_SATA_PHY_3); /* Tx Boost 0db */
+ v |= __SHIFTIN(0x11, IOMUX_GPR13_SATA_PHY_2); /* Tx Level 1.104V */
+ v |= __SHIFTIN(1, IOMUX_GPR13_SATA_PHY_1); /* PLL clock enable */
iomux_write(IOMUX_GPR13, v);
/* phy reset */
Index: src/sys/arch/arm/imx/imx6_iomuxreg.h
diff -u src/sys/arch/arm/imx/imx6_iomuxreg.h:1.4 src/sys/arch/arm/imx/imx6_iomuxreg.h:1.5
--- src/sys/arch/arm/imx/imx6_iomuxreg.h:1.4 Fri Jun 9 18:14:59 2017
+++ src/sys/arch/arm/imx/imx6_iomuxreg.h Mon Jul 22 11:44:01 2019
@@ -1,4 +1,4 @@
-/* $NetBSD: imx6_iomuxreg.h,v 1.4 2017/06/09 18:14:59 ryo Exp $ */
+/* $NetBSD: imx6_iomuxreg.h,v 1.5 2019/07/22 11:44:01 hkenken Exp $ */
/*
* Copyright (c) 2014 Ryo Shimizu <r...@nerv.org>
@@ -93,16 +93,16 @@
#define IOMUX_GPR13_CAN2_STOP_REQ __BIT(29)
#define IOMUX_GPR13_CAN1_STOP_REQ __BIT(28)
#define IOMUX_GPR13_ENET_STOP_REQ __BIT(27)
-#define IOMUX_GPR13_SATA_PHY_8(n) __SHIFTIN(n, __BITS(26, 24))
-#define IOMUX_GPR13_SATA_PHY_7(n) __SHIFTIN(n, __BITS(23, 19))
-#define IOMUX_GPR13_SATA_PHY_6(n) __SHIFTIN(n, __BITS(18, 16))
-#define IOMUX_GPR13_SATA_SPEED(n) __SHIFTIN(n, __BIT(15))
-#define IOMUX_GPR13_SATA_PHY_5(n) __SHIFTIN(n, __BIT(14))
-#define IOMUX_GPR13_SATA_PHY_4(n) __SHIFTIN(n, __BITS(13, 11))
-#define IOMUX_GPR13_SATA_PHY_3(n) __SHIFTIN(n, __BITS(10, 7))
-#define IOMUX_GPR13_SATA_PHY_2(n) __SHIFTIN(n, __BITS(6, 2))
-#define IOMUX_GPR13_SATA_PHY_1(n) __SHIFTIN(n, __BIT(1))
-#define IOMUX_GPR13_SATA_PHY_0(n) __SHIFTIN(n, __BIT(0))
+#define IOMUX_GPR13_SATA_PHY_8 __BITS(26, 24)
+#define IOMUX_GPR13_SATA_PHY_7 __BITS(23, 19)
+#define IOMUX_GPR13_SATA_PHY_6 __BITS(18, 16)
+#define IOMUX_GPR13_SATA_SPEED __BIT(15)
+#define IOMUX_GPR13_SATA_PHY_5 __BIT(14)
+#define IOMUX_GPR13_SATA_PHY_4 __BITS(13, 11)
+#define IOMUX_GPR13_SATA_PHY_3 __BITS(10, 7)
+#define IOMUX_GPR13_SATA_PHY_2 __BITS(6, 2)
+#define IOMUX_GPR13_SATA_PHY_1 __BIT(1)
+#define IOMUX_GPR13_SATA_PHY_0 __BIT(0)
/* for iMX6Dual/Quad */
#define IMX6DQ_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA1 0x0000004c
