Module Name: src
Committed By: msaitoh
Date: Wed Jul 24 10:45:47 UTC 2019
Modified Files:
src/sys/arch/x86/include: cacheinfo.h
Log Message:
It seems that AMD zen2's CPUID 0x80000006 leaf's spec has changed.
The EDX register's acsociativity field has 9. In the latest available document,
it's a reserved value. I have no access to zen2's document, but many websites
say that the acsociativity is 16. Add it.
To generate a diff of this commit:
cvs rdiff -u -r1.26 -r1.27 src/sys/arch/x86/include/cacheinfo.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/x86/include/cacheinfo.h
diff -u src/sys/arch/x86/include/cacheinfo.h:1.26 src/sys/arch/x86/include/cacheinfo.h:1.27
--- src/sys/arch/x86/include/cacheinfo.h:1.26 Mon Mar 12 07:35:45 2018
+++ src/sys/arch/x86/include/cacheinfo.h Wed Jul 24 10:45:47 2019
@@ -1,4 +1,4 @@
-/* $NetBSD: cacheinfo.h,v 1.26 2018/03/12 07:35:45 msaitoh Exp $ */
+/* $NetBSD: cacheinfo.h,v 1.27 2019/07/24 10:45:47 msaitoh Exp $ */
#ifndef _X86_CACHEINFO_H_
#define _X86_CACHEINFO_H_
@@ -362,6 +362,7 @@ __CI_TBL(0, 0x02, 2, 0, 0, NULL), \
__CI_TBL(0, 0x04, 4, 0, 0, NULL), \
__CI_TBL(0, 0x06, 8, 0, 0, NULL), \
__CI_TBL(0, 0x08, 16, 0, 0, NULL), \
+__CI_TBL(0, 0x09, 16, 0, 0, NULL), \
__CI_TBL(0, 0x0a, 32, 0, 0, NULL), \
__CI_TBL(0, 0x0b, 48, 0, 0, NULL), \
__CI_TBL(0, 0x0c, 64, 0, 0, NULL), \
