Module Name: src
Committed By: msaitoh
Date: Fri Aug 9 06:27:21 UTC 2019
Modified Files:
src/sys/external/bsd/drm2/dist/drm/radeon: cikd.h evergreend.h nid.h
radeon_mode.h radeon_reg.h radeon_si_smc.c radeon_uvd_v1_0.c
radeon_uvd_v2_2.c radeon_uvd_v4_2.c sid.h
Log Message:
Use unsigned to avoid undefined behavior. Found by kUBSan.
To generate a diff of this commit:
cvs rdiff -u -r1.2 -r1.3 src/sys/external/bsd/drm2/dist/drm/radeon/cikd.h \
src/sys/external/bsd/drm2/dist/drm/radeon/evergreend.h \
src/sys/external/bsd/drm2/dist/drm/radeon/nid.h \
src/sys/external/bsd/drm2/dist/drm/radeon/radeon_reg.h \
src/sys/external/bsd/drm2/dist/drm/radeon/sid.h
cvs rdiff -u -r1.4 -r1.5 \
src/sys/external/bsd/drm2/dist/drm/radeon/radeon_mode.h
cvs rdiff -u -r1.1 -r1.2 \
src/sys/external/bsd/drm2/dist/drm/radeon/radeon_si_smc.c \
src/sys/external/bsd/drm2/dist/drm/radeon/radeon_uvd_v1_0.c \
src/sys/external/bsd/drm2/dist/drm/radeon/radeon_uvd_v2_2.c \
src/sys/external/bsd/drm2/dist/drm/radeon/radeon_uvd_v4_2.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/external/bsd/drm2/dist/drm/radeon/cikd.h
diff -u src/sys/external/bsd/drm2/dist/drm/radeon/cikd.h:1.2 src/sys/external/bsd/drm2/dist/drm/radeon/cikd.h:1.3
--- src/sys/external/bsd/drm2/dist/drm/radeon/cikd.h:1.2 Mon Aug 27 04:58:35 2018
+++ src/sys/external/bsd/drm2/dist/drm/radeon/cikd.h Fri Aug 9 06:27:21 2019
@@ -1,4 +1,4 @@
-/* $NetBSD: cikd.h,v 1.2 2018/08/27 04:58:35 riastradh Exp $ */
+/* $NetBSD: cikd.h,v 1.3 2019/08/09 06:27:21 msaitoh Exp $ */
/*
* Copyright 2012 Advanced Micro Devices, Inc.
@@ -809,7 +809,7 @@
# define IH_WPTR_WRITEBACK_ENABLE (1 << 8)
# define IH_WPTR_WRITEBACK_TIMER(x) ((x) << 9) /* log2 */
# define IH_WPTR_OVERFLOW_ENABLE (1 << 16)
-# define IH_WPTR_OVERFLOW_CLEAR (1 << 31)
+# define IH_WPTR_OVERFLOW_CLEAR (1U << 31)
#define IH_RB_BASE 0x3e04
#define IH_RB_RPTR 0x3e08
#define IH_RB_WPTR 0x3e0c
@@ -1308,7 +1308,7 @@
#define RB_BLKSZ(x) ((x) << 8)
#define BUF_SWAP_32BIT (2 << 16)
#define RB_NO_UPDATE (1 << 27)
-#define RB_RPTR_WR_ENA (1 << 31)
+#define RB_RPTR_WR_ENA (1U << 31)
#define CP_RB0_RPTR_ADDR 0xC10C
#define RB_RPTR_SWAP_32BIT (2 << 0)
@@ -1357,7 +1357,7 @@
#define CP_CPF_DEBUG 0xC200
#define CP_PQ_WPTR_POLL_CNTL 0xC20C
-#define WPTR_POLL_EN (1 << 31)
+#define WPTR_POLL_EN (1U << 31)
#define CP_ME1_PIPE0_INT_CNTL 0xC214
#define CP_ME1_PIPE1_INT_CNTL 0xC218
@@ -1518,7 +1518,7 @@
#define DOORBELL_SOURCE (1 << 28)
#define DOORBELL_SCHD_HIT (1 << 29)
#define DOORBELL_EN (1 << 30)
-#define DOORBELL_HIT (1 << 31)
+#define DOORBELL_HIT (1U << 31)
#define CP_HQD_PQ_WPTR 0xC954
#define CP_HQD_PQ_CONTROL 0xC958
#define QUEUE_SIZE(x) ((x) << 0)
@@ -1530,7 +1530,7 @@
#define UNORD_DISPATCH (1 << 28)
#define ROQ_PQ_IB_FLIP (1 << 29)
#define PRIV_STATE (1 << 30)
-#define KMD_QUEUE (1 << 31)
+#define KMD_QUEUE (1U << 31)
#define CP_HQD_IB_BASE_ADDR 0xC95Cu
#define CP_HQD_IB_BASE_ADDR_HI 0xC960u
@@ -1634,7 +1634,7 @@
#define SE_INDEX(x) ((x) << 16)
#define SH_BROADCAST_WRITES (1 << 29)
#define INSTANCE_BROADCAST_WRITES (1 << 30)
-#define SE_BROADCAST_WRITES (1 << 31)
+#define SE_BROADCAST_WRITES (1U << 31)
#define VGT_ESGS_RING_SIZE 0x30900
#define VGT_GSVS_RING_SIZE 0x30904
@@ -1661,8 +1661,8 @@
#define CGTS_OVERRIDE (1 << 21)
#define CGTS_LS_OVERRIDE (1 << 22)
#define ON_MONITOR_ADD_EN (1 << 23)
-#define ON_MONITOR_ADD(x) ((x) << 24)
-#define ON_MONITOR_ADD_MASK (0xff << 24)
+#define ON_MONITOR_ADD(x) ((uint32_t)(x) << 24)
+#define ON_MONITOR_ADD_MASK (0xffU << 24)
#define CGTS_TCC_DISABLE 0x3c00c
#define CGTS_USER_TCC_DISABLE 0x3c010
@@ -1674,10 +1674,10 @@
/*
* PM4
*/
-#define PACKET_TYPE0 0
-#define PACKET_TYPE1 1
-#define PACKET_TYPE2 2
-#define PACKET_TYPE3 3
+#define PACKET_TYPE0 0U
+#define PACKET_TYPE1 1U
+#define PACKET_TYPE2 2U
+#define PACKET_TYPE3 3U
#define CP_PACKET_GET_TYPE(h) (((h) >> 30) & 3)
#define CP_PACKET_GET_COUNT(h) (((h) >> 16) & 0x3FFF)
Index: src/sys/external/bsd/drm2/dist/drm/radeon/evergreend.h
diff -u src/sys/external/bsd/drm2/dist/drm/radeon/evergreend.h:1.2 src/sys/external/bsd/drm2/dist/drm/radeon/evergreend.h:1.3
--- src/sys/external/bsd/drm2/dist/drm/radeon/evergreend.h:1.2 Mon Aug 27 04:58:36 2018
+++ src/sys/external/bsd/drm2/dist/drm/radeon/evergreend.h Fri Aug 9 06:27:21 2019
@@ -1,4 +1,4 @@
-/* $NetBSD: evergreend.h,v 1.2 2018/08/27 04:58:36 riastradh Exp $ */
+/* $NetBSD: evergreend.h,v 1.3 2019/08/09 06:27:21 msaitoh Exp $ */
/*
* Copyright 2010 Advanced Micro Devices, Inc.
@@ -1415,7 +1415,7 @@
#define CAYMAN_DMA1_CNTL 0xd82c
/* async DMA packets */
-#define DMA_PACKET(cmd, sub_cmd, n) ((((cmd) & 0xF) << 28) | \
+#define DMA_PACKET(cmd, sub_cmd, n) ((((uint32_t)(cmd) & 0xF) << 28) | \
(((sub_cmd) & 0xFF) << 20) |\
(((n) & 0xFFFFF) << 0))
#define GET_DMA_CMD(h) (((h) & 0xf0000000) >> 28)
Index: src/sys/external/bsd/drm2/dist/drm/radeon/nid.h
diff -u src/sys/external/bsd/drm2/dist/drm/radeon/nid.h:1.2 src/sys/external/bsd/drm2/dist/drm/radeon/nid.h:1.3
--- src/sys/external/bsd/drm2/dist/drm/radeon/nid.h:1.2 Mon Aug 27 04:58:36 2018
+++ src/sys/external/bsd/drm2/dist/drm/radeon/nid.h Fri Aug 9 06:27:21 2019
@@ -1,4 +1,4 @@
-/* $NetBSD: nid.h,v 1.2 2018/08/27 04:58:36 riastradh Exp $ */
+/* $NetBSD: nid.h,v 1.3 2019/08/09 06:27:21 msaitoh Exp $ */
/*
* Copyright 2010 Advanced Micro Devices, Inc.
@@ -869,7 +869,7 @@
#define AUX_SW_DATA_RW (1 << 0)
#define AUX_SW_DATA_MASK(x) (((x) & 0xff) << 8)
#define AUX_SW_DATA_INDEX(x) (((x) & 0x1f) << 16)
-#define AUX_SW_AUTOINCREMENT_DISABLE (1 << 31)
+#define AUX_SW_AUTOINCREMENT_DISABLE (1U << 31)
#define LB_SYNC_RESET_SEL 0x6b28
#define LB_SYNC_RESET_SEL_MASK (3 << 0)
@@ -1319,7 +1319,7 @@
#define DMA_IB_CNTL 0xd024
# define DMA_IB_ENABLE (1 << 0)
# define DMA_IB_SWAP_ENABLE (1 << 4)
-# define CMD_VMID_FORCE (1 << 31)
+# define CMD_VMID_FORCE (1U << 31)
#define DMA_IB_RPTR 0xd028
#define DMA_CNTL 0xd02c
# define TRAP_ENABLE (1 << 0)
@@ -1335,7 +1335,7 @@
#define DMA_TILING_CONFIG 0xd0b8
#define DMA_MODE 0xd0bc
-#define DMA_PACKET(cmd, t, s, n) ((((cmd) & 0xF) << 28) | \
+#define DMA_PACKET(cmd, t, s, n) ((((uint32_t)(cmd) & 0xF) << 28) | \
(((t) & 0x1) << 23) | \
(((s) & 0x1) << 22) | \
(((n) & 0xFFFFF) << 0))
Index: src/sys/external/bsd/drm2/dist/drm/radeon/radeon_reg.h
diff -u src/sys/external/bsd/drm2/dist/drm/radeon/radeon_reg.h:1.2 src/sys/external/bsd/drm2/dist/drm/radeon/radeon_reg.h:1.3
--- src/sys/external/bsd/drm2/dist/drm/radeon/radeon_reg.h:1.2 Mon Aug 27 04:58:36 2018
+++ src/sys/external/bsd/drm2/dist/drm/radeon/radeon_reg.h Fri Aug 9 06:27:21 2019
@@ -1,4 +1,4 @@
-/* $NetBSD: radeon_reg.h,v 1.2 2018/08/27 04:58:36 riastradh Exp $ */
+/* $NetBSD: radeon_reg.h,v 1.3 2019/08/09 06:27:21 msaitoh Exp $ */
/*
* Copyright 2000 ATI Technologies Inc., Markham, Ontario, and
@@ -3715,10 +3715,10 @@
#define RADEON_CP_PACKET3_GET_OPCODE(h) (((h) >> 8) & 0xFF)
#define R100_CP_PACKET0_GET_REG(h) (((h) & 0x1FFF) << 2)
#define R600_CP_PACKET0_GET_REG(h) (((h) & 0xFFFF) << 2)
-#define RADEON_PACKET_TYPE0 0
-#define RADEON_PACKET_TYPE1 1
-#define RADEON_PACKET_TYPE2 2
-#define RADEON_PACKET_TYPE3 3
+#define RADEON_PACKET_TYPE0 0U
+#define RADEON_PACKET_TYPE1 1U
+#define RADEON_PACKET_TYPE2 2U
+#define RADEON_PACKET_TYPE3 3U
#define RADEON_PACKET3_NOP 0x10
Index: src/sys/external/bsd/drm2/dist/drm/radeon/sid.h
diff -u src/sys/external/bsd/drm2/dist/drm/radeon/sid.h:1.2 src/sys/external/bsd/drm2/dist/drm/radeon/sid.h:1.3
--- src/sys/external/bsd/drm2/dist/drm/radeon/sid.h:1.2 Mon Aug 27 04:58:36 2018
+++ src/sys/external/bsd/drm2/dist/drm/radeon/sid.h Fri Aug 9 06:27:21 2019
@@ -1,4 +1,4 @@
-/* $NetBSD: sid.h,v 1.2 2018/08/27 04:58:36 riastradh Exp $ */
+/* $NetBSD: sid.h,v 1.3 2019/08/09 06:27:21 msaitoh Exp $ */
/*
* Copyright 2011 Advanced Micro Devices, Inc.
@@ -224,7 +224,7 @@
#define FDO_PWM_MODE_MASK (7 << 11)
#define FDO_PWM_MODE_SHIFT 11
#define TACH_PWM_RESP_RATE(x) ((x) << 25)
-#define TACH_PWM_RESP_RATE_MASK (0x7f << 25)
+#define TACH_PWM_RESP_RATE_MASK (0x7fU << 25)
#define TACH_PWM_RESP_RATE_SHIFT 25
#define CG_TACH_CTRL 0x770
@@ -530,7 +530,7 @@
#define MC_SEQ_TRAIN_WAKEUP_CNTL 0x28e8
#define TRAIN_DONE_D0 (1 << 30)
-#define TRAIN_DONE_D1 (1 << 31)
+#define TRAIN_DONE_D1 (1U << 31)
#define MC_SEQ_SUP_CNTL 0x28c8
#define RUN_MASK (1 << 0)
@@ -657,7 +657,7 @@
# define IH_WPTR_WRITEBACK_ENABLE (1 << 8)
# define IH_WPTR_WRITEBACK_TIMER(x) ((x) << 9) /* log2 */
# define IH_WPTR_OVERFLOW_ENABLE (1 << 16)
-# define IH_WPTR_OVERFLOW_CLEAR (1 << 31)
+# define IH_WPTR_OVERFLOW_CLEAR (1U << 31)
#define IH_RB_BASE 0x3e04
#define IH_RB_RPTR 0x3e08
#define IH_RB_WPTR 0x3e0c
@@ -1003,7 +1003,7 @@
#define SE_INDEX(x) ((x) << 16)
#define SH_BROADCAST_WRITES (1 << 29)
#define INSTANCE_BROADCAST_WRITES (1 << 30)
-#define SE_BROADCAST_WRITES (1 << 31)
+#define SE_BROADCAST_WRITES (1U << 31)
#define GRBM_INT_CNTL 0x8060
# define RDERR_INT_ENABLE (1 << 0)
@@ -1249,7 +1249,7 @@
#define RB_BLKSZ(x) ((x) << 8)
#define BUF_SWAP_32BIT (2 << 16)
#define RB_NO_UPDATE (1 << 27)
-#define RB_RPTR_WR_ENA (1 << 31)
+#define RB_RPTR_WR_ENA (1U << 31)
#define CP_RB0_RPTR_ADDR 0xC10C
#define CP_RB0_RPTR_ADDR_HI 0xC110
@@ -1523,7 +1523,7 @@
# define LC_XMIT_N_FTS_MASK (0xff << 0)
# define LC_XMIT_N_FTS_SHIFT 0
# define LC_XMIT_N_FTS_OVERRIDE_EN (1 << 8)
-# define LC_N_FTS_MASK (0xff << 24)
+# define LC_N_FTS_MASK (0xffU << 24)
#define PCIE_LC_SPEED_CNTL 0xa4 /* PCIE_P */
# define LC_GEN2_EN_STRAP (1 << 0)
# define LC_GEN3_EN_STRAP (1 << 1)
@@ -1850,7 +1850,7 @@
#define DMA_PGFSM_CONFIG 0xd0d8
#define DMA_PGFSM_WRITE 0xd0dc
-#define DMA_PACKET(cmd, b, t, s, n) ((((cmd) & 0xF) << 28) | \
+#define DMA_PACKET(cmd, b, t, s, n) ((((uint32_t)(cmd) & 0xF) << 28) | \
(((b) & 0x1) << 26) | \
(((t) & 0x1) << 23) | \
(((s) & 0x1) << 22) | \
Index: src/sys/external/bsd/drm2/dist/drm/radeon/radeon_mode.h
diff -u src/sys/external/bsd/drm2/dist/drm/radeon/radeon_mode.h:1.4 src/sys/external/bsd/drm2/dist/drm/radeon/radeon_mode.h:1.5
--- src/sys/external/bsd/drm2/dist/drm/radeon/radeon_mode.h:1.4 Mon Aug 27 15:13:05 2018
+++ src/sys/external/bsd/drm2/dist/drm/radeon/radeon_mode.h Fri Aug 9 06:27:21 2019
@@ -1,4 +1,4 @@
-/* $NetBSD: radeon_mode.h,v 1.4 2018/08/27 15:13:05 riastradh Exp $ */
+/* $NetBSD: radeon_mode.h,v 1.5 2019/08/09 06:27:21 msaitoh Exp $ */
/*
* Copyright 2000 ATI Technologies Inc., Markham, Ontario, and
@@ -693,7 +693,7 @@ struct atom_voltage_table
/* Driver internal use only flags of radeon_get_crtc_scanoutpos() */
#define USE_REAL_VBLANKSTART (1 << 30)
-#define GET_DISTANCE_TO_VBLANKSTART (1 << 31)
+#define GET_DISTANCE_TO_VBLANKSTART (1U << 31)
extern void
radeon_add_atom_connector(struct drm_device *dev,
Index: src/sys/external/bsd/drm2/dist/drm/radeon/radeon_si_smc.c
diff -u src/sys/external/bsd/drm2/dist/drm/radeon/radeon_si_smc.c:1.1 src/sys/external/bsd/drm2/dist/drm/radeon/radeon_si_smc.c:1.2
--- src/sys/external/bsd/drm2/dist/drm/radeon/radeon_si_smc.c:1.1 Mon Aug 27 14:38:20 2018
+++ src/sys/external/bsd/drm2/dist/drm/radeon/radeon_si_smc.c Fri Aug 9 06:27:21 2019
@@ -1,4 +1,4 @@
-/* $NetBSD: radeon_si_smc.c,v 1.1 2018/08/27 14:38:20 riastradh Exp $ */
+/* $NetBSD: radeon_si_smc.c,v 1.2 2019/08/09 06:27:21 msaitoh Exp $ */
/*
* Copyright 2011 Advanced Micro Devices, Inc.
@@ -25,7 +25,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: radeon_si_smc.c,v 1.1 2018/08/27 14:38:20 riastradh Exp $");
+__KERNEL_RCSID(0, "$NetBSD: radeon_si_smc.c,v 1.2 2019/08/09 06:27:21 msaitoh Exp $");
#include <linux/firmware.h>
#include "drmP.h"
@@ -67,7 +67,7 @@ int si_copy_bytes_to_smc(struct radeon_d
spin_lock_irqsave(&rdev->smc_idx_lock, flags);
while (byte_count >= 4) {
/* SMC address space is BE */
- data = (src[0] << 24) | (src[1] << 16) | (src[2] << 8) | src[3];
+ data = ((u32)src[0] << 24) | (src[1] << 16) | (src[2] << 8) | src[3];
ret = si_set_smc_sram_address(rdev, addr, limit);
if (ret)
@@ -271,7 +271,7 @@ int si_load_smc_ucode(struct radeon_devi
WREG32_P(SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_0, ~AUTO_INCREMENT_IND_0);
while (ucode_size >= 4) {
/* SMC address space is BE */
- data = (src[0] << 24) | (src[1] << 16) | (src[2] << 8) | src[3];
+ data = ((u32)src[0] << 24) | (src[1] << 16) | (src[2] << 8) | src[3];
WREG32(SMC_IND_DATA_0, data);
Index: src/sys/external/bsd/drm2/dist/drm/radeon/radeon_uvd_v1_0.c
diff -u src/sys/external/bsd/drm2/dist/drm/radeon/radeon_uvd_v1_0.c:1.1 src/sys/external/bsd/drm2/dist/drm/radeon/radeon_uvd_v1_0.c:1.2
--- src/sys/external/bsd/drm2/dist/drm/radeon/radeon_uvd_v1_0.c:1.1 Mon Aug 27 14:38:20 2018
+++ src/sys/external/bsd/drm2/dist/drm/radeon/radeon_uvd_v1_0.c Fri Aug 9 06:27:21 2019
@@ -1,4 +1,4 @@
-/* $NetBSD: radeon_uvd_v1_0.c,v 1.1 2018/08/27 14:38:20 riastradh Exp $ */
+/* $NetBSD: radeon_uvd_v1_0.c,v 1.2 2019/08/09 06:27:21 msaitoh Exp $ */
/*
* Copyright 2013 Advanced Micro Devices, Inc.
@@ -25,7 +25,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: radeon_uvd_v1_0.c,v 1.1 2018/08/27 14:38:20 riastradh Exp $");
+__KERNEL_RCSID(0, "$NetBSD: radeon_uvd_v1_0.c,v 1.2 2019/08/09 06:27:21 msaitoh Exp $");
#include <linux/firmware.h>
#include <drm/drmP.h>
@@ -366,7 +366,7 @@ int uvd_v1_0_start(struct radeon_device
/* programm the 4GB memory segment for rptr and ring buffer */
WREG32(UVD_LMI_EXT40_ADDR, upper_32_bits(ring->gpu_addr) |
- (0x7 << 16) | (0x1 << 31));
+ (0x7 << 16) | (0x1U << 31));
/* Initialize the ring buffer's read and write pointers */
WREG32(UVD_RBC_RB_RPTR, 0x0);
Index: src/sys/external/bsd/drm2/dist/drm/radeon/radeon_uvd_v2_2.c
diff -u src/sys/external/bsd/drm2/dist/drm/radeon/radeon_uvd_v2_2.c:1.1 src/sys/external/bsd/drm2/dist/drm/radeon/radeon_uvd_v2_2.c:1.2
--- src/sys/external/bsd/drm2/dist/drm/radeon/radeon_uvd_v2_2.c:1.1 Mon Aug 27 14:38:20 2018
+++ src/sys/external/bsd/drm2/dist/drm/radeon/radeon_uvd_v2_2.c Fri Aug 9 06:27:21 2019
@@ -1,4 +1,4 @@
-/* $NetBSD: radeon_uvd_v2_2.c,v 1.1 2018/08/27 14:38:20 riastradh Exp $ */
+/* $NetBSD: radeon_uvd_v2_2.c,v 1.2 2019/08/09 06:27:21 msaitoh Exp $ */
/*
* Copyright 2013 Advanced Micro Devices, Inc.
@@ -25,7 +25,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: radeon_uvd_v2_2.c,v 1.1 2018/08/27 14:38:20 riastradh Exp $");
+__KERNEL_RCSID(0, "$NetBSD: radeon_uvd_v2_2.c,v 1.2 2019/08/09 06:27:21 msaitoh Exp $");
#include <linux/firmware.h>
#include <drm/drmP.h>
@@ -136,7 +136,7 @@ int uvd_v2_2_resume(struct radeon_device
/* bits 32-39 */
addr = (rdev->uvd.gpu_addr >> 32) & 0xFF;
- WREG32(UVD_LMI_EXT40_ADDR, addr | (0x9 << 16) | (0x1 << 31));
+ WREG32(UVD_LMI_EXT40_ADDR, addr | (0x9 << 16) | (0x1U << 31));
/* tell firmware which hardware it is running on */
switch (rdev->family) {
Index: src/sys/external/bsd/drm2/dist/drm/radeon/radeon_uvd_v4_2.c
diff -u src/sys/external/bsd/drm2/dist/drm/radeon/radeon_uvd_v4_2.c:1.1 src/sys/external/bsd/drm2/dist/drm/radeon/radeon_uvd_v4_2.c:1.2
--- src/sys/external/bsd/drm2/dist/drm/radeon/radeon_uvd_v4_2.c:1.1 Mon Aug 27 14:38:20 2018
+++ src/sys/external/bsd/drm2/dist/drm/radeon/radeon_uvd_v4_2.c Fri Aug 9 06:27:21 2019
@@ -1,4 +1,4 @@
-/* $NetBSD: radeon_uvd_v4_2.c,v 1.1 2018/08/27 14:38:20 riastradh Exp $ */
+/* $NetBSD: radeon_uvd_v4_2.c,v 1.2 2019/08/09 06:27:21 msaitoh Exp $ */
/*
* Copyright 2013 Advanced Micro Devices, Inc.
@@ -25,7 +25,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: radeon_uvd_v4_2.c,v 1.1 2018/08/27 14:38:20 riastradh Exp $");
+__KERNEL_RCSID(0, "$NetBSD: radeon_uvd_v4_2.c,v 1.2 2019/08/09 06:27:21 msaitoh Exp $");
#include <linux/firmware.h>
#include <drm/drmP.h>
@@ -67,7 +67,7 @@ int uvd_v4_2_resume(struct radeon_device
/* bits 32-39 */
addr = (rdev->uvd.gpu_addr >> 32) & 0xFF;
- WREG32(UVD_LMI_EXT40_ADDR, addr | (0x9 << 16) | (0x1 << 31));
+ WREG32(UVD_LMI_EXT40_ADDR, addr | (0x9 << 16) | (0x1U << 31));
return 0;
}
