Module Name: src
Committed By: martin
Date: Fri Aug 16 15:36:17 UTC 2019
Modified Files:
src/sys/arch/x86/include [netbsd-8]: cacheinfo.h specialreg.h
src/sys/arch/x86/x86 [netbsd-8]: identcpu.c
src/usr.sbin/cpuctl/arch [netbsd-8]: i386.c
Log Message:
Pull up following revision(s) (requested by msaitoh in ticket #1338):
usr.sbin/cpuctl/arch/i386.c: revision 1.104
sys/arch/x86/x86/identcpu.c: revision 1.93
sys/arch/x86/include/cacheinfo.h: revision 1.28
sys/arch/x86/include/specialreg.h: revision 1.150
- AMD CPUID Fn8000_0001d Cache Topology Information leaf is almost the same as
Intel Deterministic Cache Parameter Leaf(0x04), so make new
cpu_dcp_cacheinfo() and share it.
- AMD's L2 and L3's cache descriptor's definition is the same, so use one
common definition.
- KNF.
XXX Split some common functions to new identcpu_subr.c or use #ifdef _KERNEK
... #endif in identcpu.c to share from both kernel and cpuctl?
To generate a diff of this commit:
cvs rdiff -u -r1.22.10.3 -r1.22.10.4 src/sys/arch/x86/include/cacheinfo.h
cvs rdiff -u -r1.98.2.14 -r1.98.2.15 src/sys/arch/x86/include/specialreg.h
cvs rdiff -u -r1.55.2.8 -r1.55.2.9 src/sys/arch/x86/x86/identcpu.c
cvs rdiff -u -r1.74.6.6 -r1.74.6.7 src/usr.sbin/cpuctl/arch/i386.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/x86/include/cacheinfo.h
diff -u src/sys/arch/x86/include/cacheinfo.h:1.22.10.3 src/sys/arch/x86/include/cacheinfo.h:1.22.10.4
--- src/sys/arch/x86/include/cacheinfo.h:1.22.10.3 Fri Aug 16 15:28:38 2019
+++ src/sys/arch/x86/include/cacheinfo.h Fri Aug 16 15:36:17 2019
@@ -1,4 +1,4 @@
-/* $NetBSD: cacheinfo.h,v 1.22.10.3 2019/08/16 15:28:38 martin Exp $ */
+/* $NetBSD: cacheinfo.h,v 1.22.10.4 2019/08/16 15:36:17 martin Exp $ */
#ifndef _X86_CACHEINFO_H_
#define _X86_CACHEINFO_H_
@@ -339,7 +339,7 @@ __CI_TBL(CAI_PREFETCH, 0xf1, 0,
__CI_TBL(0, 0, 0, 0, 0, NULL) \
}
-#define AMD_L2CACHE_INFO { \
+#define AMD_L2L3CACHE_INFO { \
__CI_TBL(0, 0x01, 1, 0, 0, NULL), \
__CI_TBL(0, 0x02, 2, 0, 0, NULL), \
__CI_TBL(0, 0x03, 3, 0, 0, NULL), \
@@ -347,22 +347,7 @@ __CI_TBL(0, 0x04, 4, 0, 0, NULL), \
__CI_TBL(0, 0x05, 6, 0, 0, NULL), \
__CI_TBL(0, 0x06, 8, 0, 0, NULL), \
__CI_TBL(0, 0x08, 16, 0, 0, NULL), \
-__CI_TBL(0, 0x0a, 32, 0, 0, NULL), \
-__CI_TBL(0, 0x0b, 48, 0, 0, NULL), \
-__CI_TBL(0, 0x0c, 64, 0, 0, NULL), \
-__CI_TBL(0, 0x0d, 96, 0, 0, NULL), \
-__CI_TBL(0, 0x0e, 128, 0, 0, NULL), \
-__CI_TBL(0, 0x0f, 0xff, 0, 0, NULL), \
-__CI_TBL(0, 0x00, 0, 0, 0, NULL) \
-}
-
-#define AMD_L3CACHE_INFO { \
-__CI_TBL(0, 0x01, 1, 0, 0, NULL), \
-__CI_TBL(0, 0x02, 2, 0, 0, NULL), \
-__CI_TBL(0, 0x04, 4, 0, 0, NULL), \
-__CI_TBL(0, 0x06, 8, 0, 0, NULL), \
-__CI_TBL(0, 0x08, 16, 0, 0, NULL), \
-__CI_TBL(0, 0x09, 16, 0, 0, NULL), \
+ /* 0x09:Use Fn8000_001D */ \
__CI_TBL(0, 0x0a, 32, 0, 0, NULL), \
__CI_TBL(0, 0x0b, 48, 0, 0, NULL), \
__CI_TBL(0, 0x0c, 64, 0, 0, NULL), \
Index: src/sys/arch/x86/include/specialreg.h
diff -u src/sys/arch/x86/include/specialreg.h:1.98.2.14 src/sys/arch/x86/include/specialreg.h:1.98.2.15
--- src/sys/arch/x86/include/specialreg.h:1.98.2.14 Wed Jul 17 15:37:33 2019
+++ src/sys/arch/x86/include/specialreg.h Fri Aug 16 15:36:17 2019
@@ -1,4 +1,4 @@
-/* $NetBSD: specialreg.h,v 1.98.2.14 2019/07/17 15:37:33 martin Exp $ */
+/* $NetBSD: specialreg.h,v 1.98.2.15 2019/08/16 15:36:17 martin Exp $ */
/*-
* Copyright (c) 1991 The Regents of the University of California.
@@ -689,6 +689,14 @@
"\21" "VGIF"
/*
+ * AMD Fn8000_0001d Cache Topology Information.
+ * It's almost the same as Intel Deterministic Cache Parameter Leaf(0x04)
+ * except the following:
+ * No Cores/package (%eax bit 31..26)
+ * No Complex cache indexing (%edx bit 2)
+ */
+
+/*
* Centaur Extended Feature flags
*/
#define CPUID_VIA_HAS_RNG 0x00000004 /* Random number generator */
Index: src/sys/arch/x86/x86/identcpu.c
diff -u src/sys/arch/x86/x86/identcpu.c:1.55.2.8 src/sys/arch/x86/x86/identcpu.c:1.55.2.9
--- src/sys/arch/x86/x86/identcpu.c:1.55.2.8 Fri Aug 16 15:28:38 2019
+++ src/sys/arch/x86/x86/identcpu.c Fri Aug 16 15:36:17 2019
@@ -1,4 +1,4 @@
-/* $NetBSD: identcpu.c,v 1.55.2.8 2019/08/16 15:28:38 martin Exp $ */
+/* $NetBSD: identcpu.c,v 1.55.2.9 2019/08/16 15:36:17 martin Exp $ */
/*-
* Copyright (c) 1999, 2000, 2001, 2006, 2007, 2008 The NetBSD Foundation, Inc.
@@ -30,7 +30,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: identcpu.c,v 1.55.2.8 2019/08/16 15:28:38 martin Exp $");
+__KERNEL_RCSID(0, "$NetBSD: identcpu.c,v 1.55.2.9 2019/08/16 15:36:17 martin Exp $");
#include "opt_xen.h"
@@ -62,11 +62,8 @@ __KERNEL_RCSID(0, "$NetBSD: identcpu.c,v
static const struct x86_cache_info intel_cpuid_cache_info[] = INTEL_CACHE_INFO;
-static const struct x86_cache_info amd_cpuid_l2cache_assoc_info[] =
- AMD_L2CACHE_INFO;
-
-static const struct x86_cache_info amd_cpuid_l3cache_assoc_info[] =
- AMD_L3CACHE_INFO;
+static const struct x86_cache_info amd_cpuid_l2l3cache_assoc_info[] =
+ AMD_L2L3CACHE_INFO;
int cpu_vendor;
char cpu_brand_string[49];
@@ -107,6 +104,66 @@ cache_info_lookup(const struct x86_cache
return (NULL);
}
+/*
+ * Get cache info from one of the following:
+ * Intel Deterministic Cache Parameter Leaf (0x04)
+ * AMD Cache Topology Information Leaf (0x8000001d)
+ */
+static void
+cpu_dcp_cacheinfo(struct cpu_info *ci, uint32_t leaf)
+{
+ u_int descs[4];
+ int type, level, ways, partitions, linesize, sets, totalsize;
+ int caitype = -1;
+ int i;
+
+ for (i = 0; ; i++) {
+ x86_cpuid2(leaf, i, descs);
+ type = __SHIFTOUT(descs[0], CPUID_DCP_CACHETYPE);
+ if (type == CPUID_DCP_CACHETYPE_N)
+ break;
+ level = __SHIFTOUT(descs[0], CPUID_DCP_CACHELEVEL);
+ switch (level) {
+ case 1:
+ if (type == CPUID_DCP_CACHETYPE_I)
+ caitype = CAI_ICACHE;
+ else if (type == CPUID_DCP_CACHETYPE_D)
+ caitype = CAI_DCACHE;
+ else
+ caitype = -1;
+ break;
+ case 2:
+ if (type == CPUID_DCP_CACHETYPE_U)
+ caitype = CAI_L2CACHE;
+ else
+ caitype = -1;
+ break;
+ case 3:
+ if (type == CPUID_DCP_CACHETYPE_U)
+ caitype = CAI_L3CACHE;
+ else
+ caitype = -1;
+ break;
+ default:
+ caitype = -1;
+ break;
+ }
+ if (caitype == -1)
+ continue;
+
+ ways = __SHIFTOUT(descs[1], CPUID_DCP_WAYS) + 1;
+ partitions =__SHIFTOUT(descs[1], CPUID_DCP_PARTITIONS)
+ + 1;
+ linesize = __SHIFTOUT(descs[1], CPUID_DCP_LINESIZE)
+ + 1;
+ sets = descs[2] + 1;
+ totalsize = ways * partitions * linesize * sets;
+ ci->ci_cinfo[caitype].cai_totalsize = totalsize;
+ ci->ci_cinfo[caitype].cai_associativity = ways;
+ ci->ci_cinfo[caitype].cai_linesize = linesize;
+ }
+}
+
static void
cpu_probe_intel_cache(struct cpu_info *ci)
{
@@ -140,59 +197,11 @@ cpu_probe_intel_cache(struct cpu_info *c
}
}
- if (cpuid_level >= 4) {
- int type, level;
- int ways, partitions, linesize, sets;
- int caitype = -1;
- int totalsize;
-
- /* Parse the cache info from `cpuid leaf 4', if we have it. */
- for (i = 0; ; i++) {
- x86_cpuid2(4, i, descs);
- type = __SHIFTOUT(descs[0], CPUID_DCP_CACHETYPE);
- if (type == CPUID_DCP_CACHETYPE_N)
- break;
- level = __SHIFTOUT(descs[0], CPUID_DCP_CACHELEVEL);
- switch (level) {
- case 1:
- if (type == CPUID_DCP_CACHETYPE_I)
- caitype = CAI_ICACHE;
- else if (type == CPUID_DCP_CACHETYPE_D)
- caitype = CAI_DCACHE;
- else
- caitype = -1;
- break;
- case 2:
- if (type == CPUID_DCP_CACHETYPE_U)
- caitype = CAI_L2CACHE;
- else
- caitype = -1;
- break;
- case 3:
- if (type == CPUID_DCP_CACHETYPE_U)
- caitype = CAI_L3CACHE;
- else
- caitype = -1;
- break;
- default:
- caitype = -1;
- break;
- }
- if (caitype == -1)
- continue;
+ if (cpuid_level < 4)
+ return;
- ways = __SHIFTOUT(descs[1], CPUID_DCP_WAYS) + 1;
- partitions =__SHIFTOUT(descs[1], CPUID_DCP_PARTITIONS)
- + 1;
- linesize = __SHIFTOUT(descs[1], CPUID_DCP_LINESIZE)
- + 1;
- sets = descs[2] + 1;
- totalsize = ways * partitions * linesize * sets;
- ci->ci_cinfo[caitype].cai_totalsize = totalsize;
- ci->ci_cinfo[caitype].cai_associativity = ways;
- ci->ci_cinfo[caitype].cai_linesize = linesize;
- }
- }
+ /* Parse the cache info from `cpuid leaf 4', if we have it. */
+ cpu_dcp_cacheinfo(ci, 4);
}
static void
@@ -236,31 +245,21 @@ cpu_probe_amd_cache(struct cpu_info *ci)
family = CPUID_TO_FAMILY(ci->ci_signature);
model = CPUID_TO_MODEL(ci->ci_signature);
- /*
- * K5 model 0 has none of this info.
- */
+ /* K5 model 0 has none of this info. */
if (family == 5 && model == 0)
return;
- /*
- * Determine the largest extended function value.
- */
+ /* Determine the largest extended function value. */
x86_cpuid(0x80000000, descs);
lfunc = descs[0];
- /*
- * Determine L1 cache/TLB info.
- */
- if (lfunc < 0x80000005) {
- /* No L1 cache info available. */
+ if (lfunc < 0x80000005)
return;
- }
+ /* Determine L1 cache/TLB info. */
x86_cpuid(0x80000005, descs);
- /*
- * K6-III and higher have large page TLBs.
- */
+ /* K6-III and higher have large page TLBs. */
if ((family == 5 && model >= 9) || family >= 6) {
cai = &ci->ci_cinfo[CAI_ITLB2];
cai->cai_totalsize = AMD_L1_EAX_ITLB_ENTRIES(descs[0]);
@@ -293,14 +292,10 @@ cpu_probe_amd_cache(struct cpu_info *ci)
cai->cai_associativity = AMD_L1_EDX_IC_ASSOC(descs[3]);
cai->cai_linesize = AMD_L1_EDX_IC_LS(descs[3]);
- /*
- * Determine L2 cache/TLB info.
- */
- if (lfunc < 0x80000006) {
- /* No L2 cache info available. */
+ if (lfunc < 0x80000006)
return;
- }
+ /* Determine L2 cache/TLB info. */
x86_cpuid(0x80000006, descs);
cai = &ci->ci_cinfo[CAI_L2CACHE];
@@ -308,35 +303,33 @@ cpu_probe_amd_cache(struct cpu_info *ci)
cai->cai_associativity = AMD_L2_ECX_C_ASSOC(descs[2]);
cai->cai_linesize = AMD_L2_ECX_C_LS(descs[2]);
- cp = cache_info_lookup(amd_cpuid_l2cache_assoc_info,
+ cp = cache_info_lookup(amd_cpuid_l2l3cache_assoc_info,
cai->cai_associativity);
if (cp != NULL)
cai->cai_associativity = cp->cai_associativity;
else
cai->cai_associativity = 0; /* XXX Unknown/reserved */
- if (family < 0xf) {
- /* No L3 cache info available. */
+ if (family < 0xf)
return;
- }
+ /* Determine L3 cache info on AMD Family 10h and newer processors */
cai = &ci->ci_cinfo[CAI_L3CACHE];
cai->cai_totalsize = AMD_L3_EDX_C_SIZE(descs[3]);
cai->cai_associativity = AMD_L3_EDX_C_ASSOC(descs[3]);
cai->cai_linesize = AMD_L3_EDX_C_LS(descs[3]);
- cp = cache_info_lookup(amd_cpuid_l3cache_assoc_info,
+ cp = cache_info_lookup(amd_cpuid_l2l3cache_assoc_info,
cai->cai_associativity);
if (cp != NULL)
cai->cai_associativity = cp->cai_associativity;
else
cai->cai_associativity = 0; /* XXX Unknown reserved */
- if (lfunc < 0x80000019) {
- /* No 1GB Page TLB */
+ if (lfunc < 0x80000019)
return;
- }
+ /* Determine 1GB TLB info. */
x86_cpuid(0x80000019, descs);
cai = &ci->ci_cinfo[CAI_L1_1GBDTLB];
@@ -358,6 +351,11 @@ cpu_probe_amd_cache(struct cpu_info *ci)
cai->cai_totalsize = AMD_L2_1GB_EBX_IUTLB_ENTRIES(descs[0]);
cai->cai_associativity = AMD_L2_1GB_EBX_IUTLB_ASSOC(descs[0]);
cai->cai_linesize = (1 * 1024);
+
+ if (lfunc < 0x8000001d)
+ return;
+
+ cpu_dcp_cacheinfo(ci, 0x8000001d);
}
static void
Index: src/usr.sbin/cpuctl/arch/i386.c
diff -u src/usr.sbin/cpuctl/arch/i386.c:1.74.6.6 src/usr.sbin/cpuctl/arch/i386.c:1.74.6.7
--- src/usr.sbin/cpuctl/arch/i386.c:1.74.6.6 Wed Jul 17 16:01:43 2019
+++ src/usr.sbin/cpuctl/arch/i386.c Fri Aug 16 15:36:17 2019
@@ -1,4 +1,4 @@
-/* $NetBSD: i386.c,v 1.74.6.6 2019/07/17 16:01:43 martin Exp $ */
+/* $NetBSD: i386.c,v 1.74.6.7 2019/08/16 15:36:17 martin Exp $ */
/*-
* Copyright (c) 1999, 2000, 2001, 2006, 2007, 2008 The NetBSD Foundation, Inc.
@@ -57,7 +57,7 @@
#include <sys/cdefs.h>
#ifndef lint
-__RCSID("$NetBSD: i386.c,v 1.74.6.6 2019/07/17 16:01:43 martin Exp $");
+__RCSID("$NetBSD: i386.c,v 1.74.6.7 2019/08/16 15:36:17 martin Exp $");
#endif /* not lint */
#include <sys/types.h>
@@ -216,6 +216,7 @@ static void powernow_probe(struct cpu_in
static void intel_family_new_probe(struct cpu_info *);
static void via_cpu_probe(struct cpu_info *);
/* (Cache) Info functions */
+static void cpu_dcp_cacheinfo(struct cpu_info *, uint32_t);
static void intel_cpu_cacheinfo(struct cpu_info *);
static void amd_cpu_cacheinfo(struct cpu_info *);
static void via_cpu_cacheinfo(struct cpu_info *);
@@ -987,16 +988,77 @@ amd_family6_probe(struct cpu_info *ci)
}
}
+/*
+ * Get cache info from one of the following:
+ * Intel Deterministic Cache Parameter Leaf (0x04)
+ * AMD Cache Topology Information Leaf (0x8000001d)
+ */
+static void
+cpu_dcp_cacheinfo(struct cpu_info *ci, uint32_t leaf)
+{
+ u_int descs[4];
+ int type, level, ways, partitions, linesize, sets, totalsize;
+ int caitype = -1;
+ int i;
+
+ for (i = 0; ; i++) {
+ x86_cpuid2(leaf, i, descs);
+ type = __SHIFTOUT(descs[0], CPUID_DCP_CACHETYPE);
+ if (type == CPUID_DCP_CACHETYPE_N)
+ break;
+ level = __SHIFTOUT(descs[0], CPUID_DCP_CACHELEVEL);
+ switch (level) {
+ case 1:
+ if (type == CPUID_DCP_CACHETYPE_I)
+ caitype = CAI_ICACHE;
+ else if (type == CPUID_DCP_CACHETYPE_D)
+ caitype = CAI_DCACHE;
+ else
+ caitype = -1;
+ break;
+ case 2:
+ if (type == CPUID_DCP_CACHETYPE_U)
+ caitype = CAI_L2CACHE;
+ else
+ caitype = -1;
+ break;
+ case 3:
+ if (type == CPUID_DCP_CACHETYPE_U)
+ caitype = CAI_L3CACHE;
+ else
+ caitype = -1;
+ break;
+ default:
+ caitype = -1;
+ break;
+ }
+ if (caitype == -1) {
+ aprint_error_dev(ci->ci_dev,
+ "error: unknown cache level&type (%d & %d)\n",
+ level, type);
+ continue;
+ }
+ ways = __SHIFTOUT(descs[1], CPUID_DCP_WAYS) + 1;
+ partitions =__SHIFTOUT(descs[1], CPUID_DCP_PARTITIONS)
+ + 1;
+ linesize = __SHIFTOUT(descs[1], CPUID_DCP_LINESIZE)
+ + 1;
+ sets = descs[2] + 1;
+ totalsize = ways * partitions * linesize * sets;
+ ci->ci_cinfo[caitype].cai_totalsize = totalsize;
+ ci->ci_cinfo[caitype].cai_associativity = ways;
+ ci->ci_cinfo[caitype].cai_linesize = linesize;
+ }
+}
+
static void
intel_cpu_cacheinfo(struct cpu_info *ci)
{
const struct x86_cache_info *cai;
u_int descs[4];
int iterations, i, j;
- int type, level;
- int ways, partitions, linesize, sets;
+ int type, level, ways, linesize, sets;
int caitype = -1;
- int totalsize;
uint8_t desc;
/* Return if the cpu is old pre-cpuid instruction cpu */
@@ -1045,54 +1107,7 @@ intel_cpu_cacheinfo(struct cpu_info *ci)
return;
/* Parse the cache info from `cpuid leaf 4', if we have it. */
- for (i = 0; ; i++) {
- x86_cpuid2(4, i, descs);
- type = __SHIFTOUT(descs[0], CPUID_DCP_CACHETYPE);
- if (type == CPUID_DCP_CACHETYPE_N)
- break;
- level = __SHIFTOUT(descs[0], CPUID_DCP_CACHELEVEL);
- switch (level) {
- case 1:
- if (type == CPUID_DCP_CACHETYPE_I)
- caitype = CAI_ICACHE;
- else if (type == CPUID_DCP_CACHETYPE_D)
- caitype = CAI_DCACHE;
- else
- caitype = -1;
- break;
- case 2:
- if (type == CPUID_DCP_CACHETYPE_U)
- caitype = CAI_L2CACHE;
- else
- caitype = -1;
- break;
- case 3:
- if (type == CPUID_DCP_CACHETYPE_U)
- caitype = CAI_L3CACHE;
- else
- caitype = -1;
- break;
- default:
- caitype = -1;
- break;
- }
- if (caitype == -1) {
- aprint_error_dev(ci->ci_dev,
- "error: unknown cache level&type (%d & %d)\n",
- level, type);
- continue;
- }
- ways = __SHIFTOUT(descs[1], CPUID_DCP_WAYS) + 1;
- partitions =__SHIFTOUT(descs[1], CPUID_DCP_PARTITIONS)
- + 1;
- linesize = __SHIFTOUT(descs[1], CPUID_DCP_LINESIZE)
- + 1;
- sets = descs[2] + 1;
- totalsize = ways * partitions * linesize * sets;
- ci->ci_cinfo[caitype].cai_totalsize = totalsize;
- ci->ci_cinfo[caitype].cai_associativity = ways;
- ci->ci_cinfo[caitype].cai_linesize = linesize;
- }
+ cpu_dcp_cacheinfo(ci, 4);
if (ci->ci_cpuid_level < 0x18)
return;
@@ -1229,11 +1244,8 @@ intel_cpu_cacheinfo(struct cpu_info *ci)
}
}
-static const struct x86_cache_info amd_cpuid_l2cache_assoc_info[] =
- AMD_L2CACHE_INFO;
-
-static const struct x86_cache_info amd_cpuid_l3cache_assoc_info[] =
- AMD_L3CACHE_INFO;
+static const struct x86_cache_info amd_cpuid_l2l3cache_assoc_info[] =
+ AMD_L2L3CACHE_INFO;
static void
amd_cpu_cacheinfo(struct cpu_info *ci)
@@ -1243,31 +1255,21 @@ amd_cpu_cacheinfo(struct cpu_info *ci)
u_int descs[4];
u_int lfunc;
- /*
- * K5 model 0 has none of this info.
- */
+ /* K5 model 0 has none of this info. */
if (ci->ci_family == 5 && ci->ci_model == 0)
return;
- /*
- * Determine the largest extended function value.
- */
+ /* Determine the largest extended function value. */
x86_cpuid(0x80000000, descs);
lfunc = descs[0];
- /*
- * Determine L1 cache/TLB info.
- */
- if (lfunc < 0x80000005) {
- /* No L1 cache info available. */
+ if (lfunc < 0x80000005)
return;
- }
+ /* Determine L1 cache/TLB info. */
x86_cpuid(0x80000005, descs);
- /*
- * K6-III and higher have large page TLBs.
- */
+ /* K6-III and higher have large page TLBs. */
if ((ci->ci_family == 5 && ci->ci_model >= 9) || ci->ci_family >= 6) {
cai = &ci->ci_cinfo[CAI_ITLB2];
cai->cai_totalsize = AMD_L1_EAX_ITLB_ENTRIES(descs[0]);
@@ -1300,21 +1302,17 @@ amd_cpu_cacheinfo(struct cpu_info *ci)
cai->cai_associativity = AMD_L1_EDX_IC_ASSOC(descs[3]);
cai->cai_linesize = AMD_L1_EDX_IC_LS(descs[3]);
- /*
- * Determine L2 cache/TLB info.
- */
- if (lfunc < 0x80000006) {
- /* No L2 cache info available. */
+ if (lfunc < 0x80000006)
return;
- }
+ /* Determine L2 cache/TLB info. */
x86_cpuid(0x80000006, descs);
cai = &ci->ci_cinfo[CAI_L2_ITLB];
cai->cai_totalsize = AMD_L2_EBX_IUTLB_ENTRIES(descs[1]);
cai->cai_associativity = AMD_L2_EBX_IUTLB_ASSOC(descs[1]);
cai->cai_linesize = (4 * 1024);
- cp = cache_info_lookup(amd_cpuid_l2cache_assoc_info,
+ cp = cache_info_lookup(amd_cpuid_l2l3cache_assoc_info,
cai->cai_associativity);
if (cp != NULL)
cai->cai_associativity = cp->cai_associativity;
@@ -1325,7 +1323,7 @@ amd_cpu_cacheinfo(struct cpu_info *ci)
cai->cai_totalsize = AMD_L2_EAX_IUTLB_ENTRIES(descs[0]);
cai->cai_associativity = AMD_L2_EAX_IUTLB_ASSOC(descs[0]);
cai->cai_linesize = largepagesize;
- cp = cache_info_lookup(amd_cpuid_l2cache_assoc_info,
+ cp = cache_info_lookup(amd_cpuid_l2l3cache_assoc_info,
cai->cai_associativity);
if (cp != NULL)
cai->cai_associativity = cp->cai_associativity;
@@ -1336,7 +1334,7 @@ amd_cpu_cacheinfo(struct cpu_info *ci)
cai->cai_totalsize = AMD_L2_EBX_DTLB_ENTRIES(descs[1]);
cai->cai_associativity = AMD_L2_EBX_DTLB_ASSOC(descs[1]);
cai->cai_linesize = (4 * 1024);
- cp = cache_info_lookup(amd_cpuid_l2cache_assoc_info,
+ cp = cache_info_lookup(amd_cpuid_l2l3cache_assoc_info,
cai->cai_associativity);
if (cp != NULL)
cai->cai_associativity = cp->cai_associativity;
@@ -1347,7 +1345,7 @@ amd_cpu_cacheinfo(struct cpu_info *ci)
cai->cai_totalsize = AMD_L2_EAX_DTLB_ENTRIES(descs[0]);
cai->cai_associativity = AMD_L2_EAX_DTLB_ASSOC(descs[0]);
cai->cai_linesize = largepagesize;
- cp = cache_info_lookup(amd_cpuid_l2cache_assoc_info,
+ cp = cache_info_lookup(amd_cpuid_l2l3cache_assoc_info,
cai->cai_associativity);
if (cp != NULL)
cai->cai_associativity = cp->cai_associativity;
@@ -1359,23 +1357,21 @@ amd_cpu_cacheinfo(struct cpu_info *ci)
cai->cai_associativity = AMD_L2_ECX_C_ASSOC(descs[2]);
cai->cai_linesize = AMD_L2_ECX_C_LS(descs[2]);
- cp = cache_info_lookup(amd_cpuid_l2cache_assoc_info,
+ cp = cache_info_lookup(amd_cpuid_l2l3cache_assoc_info,
cai->cai_associativity);
if (cp != NULL)
cai->cai_associativity = cp->cai_associativity;
else
cai->cai_associativity = 0; /* XXX Unknown/reserved */
- /*
- * Determine L3 cache info on AMD Family 10h and newer processors
- */
+ /* Determine L3 cache info on AMD Family 10h and newer processors */
if (ci->ci_family >= 0x10) {
cai = &ci->ci_cinfo[CAI_L3CACHE];
cai->cai_totalsize = AMD_L3_EDX_C_SIZE(descs[3]);
cai->cai_associativity = AMD_L3_EDX_C_ASSOC(descs[3]);
cai->cai_linesize = AMD_L3_EDX_C_LS(descs[3]);
- cp = cache_info_lookup(amd_cpuid_l3cache_assoc_info,
+ cp = cache_info_lookup(amd_cpuid_l2l3cache_assoc_info,
cai->cai_associativity);
if (cp != NULL)
cai->cai_associativity = cp->cai_associativity;
@@ -1383,21 +1379,17 @@ amd_cpu_cacheinfo(struct cpu_info *ci)
cai->cai_associativity = 0; /* XXX Unkn/Rsvd */
}
- /*
- * Determine 1GB TLB info.
- */
- if (lfunc < 0x80000019) {
- /* No 1GB TLB info available. */
+ if (lfunc < 0x80000019)
return;
- }
+ /* Determine 1GB TLB info. */
x86_cpuid(0x80000019, descs);
cai = &ci->ci_cinfo[CAI_L1_1GBITLB];
cai->cai_totalsize = AMD_L1_1GB_EAX_IUTLB_ENTRIES(descs[0]);
cai->cai_associativity = AMD_L1_1GB_EAX_IUTLB_ASSOC(descs[0]);
cai->cai_linesize = (1024 * 1024 * 1024);
- cp = cache_info_lookup(amd_cpuid_l2cache_assoc_info,
+ cp = cache_info_lookup(amd_cpuid_l2l3cache_assoc_info,
cai->cai_associativity);
if (cp != NULL)
cai->cai_associativity = cp->cai_associativity;
@@ -1408,7 +1400,7 @@ amd_cpu_cacheinfo(struct cpu_info *ci)
cai->cai_totalsize = AMD_L1_1GB_EAX_DTLB_ENTRIES(descs[0]);
cai->cai_associativity = AMD_L1_1GB_EAX_DTLB_ASSOC(descs[0]);
cai->cai_linesize = (1024 * 1024 * 1024);
- cp = cache_info_lookup(amd_cpuid_l2cache_assoc_info,
+ cp = cache_info_lookup(amd_cpuid_l2l3cache_assoc_info,
cai->cai_associativity);
if (cp != NULL)
cai->cai_associativity = cp->cai_associativity;
@@ -1419,7 +1411,7 @@ amd_cpu_cacheinfo(struct cpu_info *ci)
cai->cai_totalsize = AMD_L2_1GB_EBX_IUTLB_ENTRIES(descs[1]);
cai->cai_associativity = AMD_L2_1GB_EBX_IUTLB_ASSOC(descs[1]);
cai->cai_linesize = (1024 * 1024 * 1024);
- cp = cache_info_lookup(amd_cpuid_l2cache_assoc_info,
+ cp = cache_info_lookup(amd_cpuid_l2l3cache_assoc_info,
cai->cai_associativity);
if (cp != NULL)
cai->cai_associativity = cp->cai_associativity;
@@ -1430,12 +1422,17 @@ amd_cpu_cacheinfo(struct cpu_info *ci)
cai->cai_totalsize = AMD_L2_1GB_EBX_DUTLB_ENTRIES(descs[1]);
cai->cai_associativity = AMD_L2_1GB_EBX_DUTLB_ASSOC(descs[1]);
cai->cai_linesize = (1024 * 1024 * 1024);
- cp = cache_info_lookup(amd_cpuid_l2cache_assoc_info,
+ cp = cache_info_lookup(amd_cpuid_l2l3cache_assoc_info,
cai->cai_associativity);
if (cp != NULL)
cai->cai_associativity = cp->cai_associativity;
else
cai->cai_associativity = 0; /* XXX Unknown/reserved */
+
+ if (lfunc < 0x8000001d)
+ return;
+
+ cpu_dcp_cacheinfo(ci, 0x8000001d);
}
static void
