Module Name: src
Committed By: tnn
Date: Sat Sep 7 19:42:42 UTC 2019
Modified Files:
src/sys/arch/arm/arm32: cpu.c
src/sys/arch/arm/include: cputypes.h vfpreg.h
src/sys/arch/arm/vfp: vfp_init.c
Log Message:
Cortex A12 is marketed as A17 but has a distinct part number
observed on Rockchip RK3288
To generate a diff of this commit:
cvs rdiff -u -r1.129 -r1.130 src/sys/arch/arm/arm32/cpu.c
cvs rdiff -u -r1.8 -r1.9 src/sys/arch/arm/include/cputypes.h
cvs rdiff -u -r1.16 -r1.17 src/sys/arch/arm/include/vfpreg.h
cvs rdiff -u -r1.62 -r1.63 src/sys/arch/arm/vfp/vfp_init.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/arm32/cpu.c
diff -u src/sys/arch/arm/arm32/cpu.c:1.129 src/sys/arch/arm/arm32/cpu.c:1.130
--- src/sys/arch/arm/arm32/cpu.c:1.129 Sun Mar 17 08:37:55 2019
+++ src/sys/arch/arm/arm32/cpu.c Sat Sep 7 19:42:42 2019
@@ -1,4 +1,4 @@
-/* $NetBSD: cpu.c,v 1.129 2019/03/17 08:37:55 skrll Exp $ */
+/* $NetBSD: cpu.c,v 1.130 2019/09/07 19:42:42 tnn Exp $ */
/*
* Copyright (c) 1995 Mark Brinicombe.
@@ -46,7 +46,7 @@
#include "opt_multiprocessor.h"
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.129 2019/03/17 08:37:55 skrll Exp $");
+__KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.130 2019/09/07 19:42:42 tnn Exp $");
#include <sys/param.h>
#include <sys/conf.h>
@@ -518,6 +518,8 @@ const struct cpuidtab cpuids[] = {
pN_steppings, "7A" },
{ CPU_ID_CORTEXA9R4, CPU_CLASS_CORTEX, "Cortex-A9 r4",
pN_steppings, "7A" },
+ { CPU_ID_CORTEXA12R0, CPU_CLASS_CORTEX, "Cortex-A12 r0",
+ pN_steppings, "7A" },
{ CPU_ID_CORTEXA15R2, CPU_CLASS_CORTEX, "Cortex-A15 r2",
pN_steppings, "7A" },
{ CPU_ID_CORTEXA15R3, CPU_CLASS_CORTEX, "Cortex-A15 r3",
Index: src/sys/arch/arm/include/cputypes.h
diff -u src/sys/arch/arm/include/cputypes.h:1.8 src/sys/arch/arm/include/cputypes.h:1.9
--- src/sys/arch/arm/include/cputypes.h:1.8 Tue Jul 16 10:37:12 2019
+++ src/sys/arch/arm/include/cputypes.h Sat Sep 7 19:42:42 2019
@@ -1,4 +1,4 @@
-/* $NetBSD: cputypes.h,v 1.8 2019/07/16 10:37:12 jmcneill Exp $ */
+/* $NetBSD: cputypes.h,v 1.9 2019/09/07 19:42:42 tnn Exp $ */
/*
* Copyright (c) 1998, 2001 Ben Harris
@@ -153,6 +153,7 @@
#define CPU_ID_CORTEXA9R2 0x412fc090
#define CPU_ID_CORTEXA9R3 0x413fc090
#define CPU_ID_CORTEXA9R4 0x414fc090
+#define CPU_ID_CORTEXA12R0 0x410fc0d0
#define CPU_ID_CORTEXA15R2 0x412fc0f0
#define CPU_ID_CORTEXA15R3 0x413fc0f0
#define CPU_ID_CORTEXA15R4 0x414fc0f0
Index: src/sys/arch/arm/include/vfpreg.h
diff -u src/sys/arch/arm/include/vfpreg.h:1.16 src/sys/arch/arm/include/vfpreg.h:1.17
--- src/sys/arch/arm/include/vfpreg.h:1.16 Fri May 26 21:17:46 2017
+++ src/sys/arch/arm/include/vfpreg.h Sat Sep 7 19:42:42 2019
@@ -1,4 +1,4 @@
-/* $NetBSD: vfpreg.h,v 1.16 2017/05/26 21:17:46 jmcneill Exp $ */
+/* $NetBSD: vfpreg.h,v 1.17 2019/09/07 19:42:42 tnn Exp $ */
/*
* Copyright (c) 2008 ARM Ltd
@@ -63,8 +63,10 @@
#define FPU_VFP_CORTEXA7 0x41023070
#define FPU_VFP_CORTEXA8 0x410330c0
#define FPU_VFP_CORTEXA9 0x41033090
+#define FPU_VFP_CORTEXA12 0x410330d0
#define FPU_VFP_CORTEXA15 0x410330f0
#define FPU_VFP_CORTEXA15_QEMU 0x410430f0
+#define FPU_VFP_CORTEXA17 0x410330e0
#define FPU_VFP_CORTEXA53 0x41034030
#define FPU_VFP_CORTEXA57 0x41034070
#define FPU_VFP_MV88SV58XX 0x56022090
Index: src/sys/arch/arm/vfp/vfp_init.c
diff -u src/sys/arch/arm/vfp/vfp_init.c:1.62 src/sys/arch/arm/vfp/vfp_init.c:1.63
--- src/sys/arch/arm/vfp/vfp_init.c:1.62 Sat Apr 6 08:48:53 2019
+++ src/sys/arch/arm/vfp/vfp_init.c Sat Sep 7 19:42:42 2019
@@ -1,4 +1,4 @@
-/* $NetBSD: vfp_init.c,v 1.62 2019/04/06 08:48:53 skrll Exp $ */
+/* $NetBSD: vfp_init.c,v 1.63 2019/09/07 19:42:42 tnn Exp $ */
/*
* Copyright (c) 2008 ARM Ltd
@@ -32,7 +32,7 @@
#include "opt_cputypes.h"
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: vfp_init.c,v 1.62 2019/04/06 08:48:53 skrll Exp $");
+__KERNEL_RCSID(0, "$NetBSD: vfp_init.c,v 1.63 2019/09/07 19:42:42 tnn Exp $");
#include <sys/param.h>
#include <sys/types.h>
@@ -332,8 +332,10 @@ vfp_attach(struct cpu_info *ci)
case FPU_VFP_CORTEXA7:
case FPU_VFP_CORTEXA8:
case FPU_VFP_CORTEXA9:
+ case FPU_VFP_CORTEXA12:
case FPU_VFP_CORTEXA15:
case FPU_VFP_CORTEXA15_QEMU:
+ case FPU_VFP_CORTEXA17:
case FPU_VFP_CORTEXA53:
case FPU_VFP_CORTEXA57:
if (armreg_cpacr_read() & CPACR_V7_ASEDIS) {
