Module Name: src
Committed By: skrll
Date: Wed Sep 11 18:19:35 UTC 2019
Modified Files:
src/sys/arch/aarch64/include: armreg.h pte.h
Log Message:
Move the TCR and TTBR defines into armreg.h where they below. NFCI.
To generate a diff of this commit:
cvs rdiff -u -r1.26 -r1.27 src/sys/arch/aarch64/include/armreg.h
cvs rdiff -u -r1.8 -r1.9 src/sys/arch/aarch64/include/pte.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/aarch64/include/armreg.h
diff -u src/sys/arch/aarch64/include/armreg.h:1.26 src/sys/arch/aarch64/include/armreg.h:1.27
--- src/sys/arch/aarch64/include/armreg.h:1.26 Mon Aug 12 23:31:48 2019
+++ src/sys/arch/aarch64/include/armreg.h Wed Sep 11 18:19:35 2019
@@ -1,4 +1,4 @@
-/* $NetBSD: armreg.h,v 1.26 2019/08/12 23:31:48 jmcneill Exp $ */
+/* $NetBSD: armreg.h,v 1.27 2019/09/11 18:19:35 skrll Exp $ */
/*-
* Copyright (c) 2014 The NetBSD Foundation, Inc.
@@ -646,7 +646,60 @@ AARCH64REG_WRITE_INLINE(spsr_el1)
AARCH64REG_READ_INLINE(tcr_el1) // Translation Control Register
AARCH64REG_WRITE_INLINE(tcr_el1)
-#define TCR_PAGE_SIZE1(tcr) (1L << ((1L << __SHIFTOUT(tcr, TCR_TG1)) + 8))
+
+/* TCR_EL1 - Translation Control Register */
+#define TCR_TBI1 __BIT(38) /* ignore Top Byte TTBR1_EL1 */
+#define TCR_TBI0 __BIT(37) /* ignore Top Byte TTBR0_EL1 */
+#define TCR_AS64K __BIT(36) /* Use 64K ASIDs */
+#define TCR_IPS __BITS(34,32) /* Intermediate PhysAdr Size */
+#define TCR_IPS_4PB __SHIFTIN(6,TCR_IPS) /* 52 bits ( 4 PB) */
+#define TCR_IPS_256TB __SHIFTIN(5,TCR_IPS) /* 48 bits (256 TB) */
+#define TCR_IPS_16TB __SHIFTIN(4,TCR_IPS) /* 44 bits (16 TB) */
+#define TCR_IPS_4TB __SHIFTIN(3,TCR_IPS) /* 42 bits ( 4 TB) */
+#define TCR_IPS_1TB __SHIFTIN(2,TCR_IPS) /* 40 bits ( 1 TB) */
+#define TCR_IPS_64GB __SHIFTIN(1,TCR_IPS) /* 36 bits (64 GB) */
+#define TCR_IPS_4GB __SHIFTIN(0,TCR_IPS) /* 32 bits (4 GB) */
+#define TCR_TG1 __BITS(31,30) /* TTBR1 Page Granule Size */
+#define TCR_TG1_16KB __SHIFTIN(1,TCR_TG1) /* 16KB page size */
+#define TCR_TG1_4KB __SHIFTIN(2,TCR_TG1) /* 4KB page size */
+#define TCR_TG1_64KB __SHIFTIN(3,TCR_TG1) /* 64KB page size */
+#define TCR_SH1 __BITS(29,28)
+#define TCR_SH1_NONE __SHIFTIN(0,TCR_SH1)
+#define TCR_SH1_OUTER __SHIFTIN(2,TCR_SH1)
+#define TCR_SH1_INNER __SHIFTIN(3,TCR_SH1)
+#define TCR_ORGN1 __BITS(27,26) /* TTBR1 Outer cacheability */
+#define TCR_ORGN1_NC __SHIFTIN(0,TCR_ORGN1) /* Non Cacheable */
+#define TCR_ORGN1_WB_WA __SHIFTIN(1,TCR_ORGN1) /* WriteBack WriteAllocate */
+#define TCR_ORGN1_WT __SHIFTIN(2,TCR_ORGN1) /* WriteThrough */
+#define TCR_ORGN1_WB __SHIFTIN(3,TCR_ORGN1) /* WriteBack */
+#define TCR_IRGN1 __BITS(25,24) /* TTBR1 Inner cacheability */
+#define TCR_IRGN1_NC __SHIFTIN(0,TCR_IRGN1) /* Non Cacheable */
+#define TCR_IRGN1_WB_WA __SHIFTIN(1,TCR_IRGN1) /* WriteBack WriteAllocate */
+#define TCR_IRGN1_WT __SHIFTIN(2,TCR_IRGN1) /* WriteThrough */
+#define TCR_IRGN1_WB __SHIFTIN(3,TCR_IRGN1) /* WriteBack */
+#define TCR_EPD1 __BIT(23) /* Walk Disable for TTBR1_EL1 */
+#define TCR_A1 __BIT(22) /* ASID is in TTBR1_EL1 */
+#define TCR_T1SZ __BITS(21,16) /* Size offset for TTBR1_EL1 */
+#define TCR_TG0 __BITS(15,14) /* TTBR0 Page Granule Size */
+#define TCR_TG0_4KB __SHIFTIN(0,TCR_TG0) /* 4KB page size */
+#define TCR_TG0_64KB __SHIFTIN(1,TCR_TG0) /* 64KB page size */
+#define TCR_TG0_16KB __SHIFTIN(2,TCR_TG0) /* 16KB page size */
+#define TCR_SH0 __BITS(13,12)
+#define TCR_SH0_NONE __SHIFTIN(0,TCR_SH0)
+#define TCR_SH0_OUTER __SHIFTIN(2,TCR_SH0)
+#define TCR_SH0_INNER __SHIFTIN(3,TCR_SH0)
+#define TCR_ORGN0 __BITS(11,10) /* TTBR0 Outer cacheability */
+#define TCR_ORGN0_NC __SHIFTIN(0,TCR_ORGN0) /* Non Cacheable */
+#define TCR_ORGN0_WB_WA __SHIFTIN(1,TCR_ORGN0) /* WriteBack WriteAllocate */
+#define TCR_ORGN0_WT __SHIFTIN(2,TCR_ORGN0) /* WriteThrough */
+#define TCR_ORGN0_WB __SHIFTIN(3,TCR_ORGN0) /* WriteBack */
+#define TCR_IRGN0 __BITS(9,8) /* TTBR0 Inner cacheability */
+#define TCR_IRGN0_NC __SHIFTIN(0,TCR_IRGN0) /* Non Cacheable */
+#define TCR_IRGN0_WB_WA __SHIFTIN(1,TCR_IRGN0) /* WriteBack WriteAllocate */
+#define TCR_IRGN0_WT __SHIFTIN(2,TCR_IRGN0) /* WriteThrough */
+#define TCR_IRGN0_WB __SHIFTIN(3,TCR_IRGN0) /* WriteBack */
+#define TCR_EPD0 __BIT(7) /* Walk Disable for TTBR0 */
+#define TCR_T0SZ __BITS(5,0) /* Size offset for TTBR0_EL1 */
AARCH64REG_READ_INLINE(tpidr_el1) // Thread ID Register (EL1)
AARCH64REG_WRITE_INLINE(tpidr_el1)
@@ -659,6 +712,9 @@ AARCH64REG_WRITE_INLINE(ttbr0_el1)
AARCH64REG_READ_INLINE(ttbr1_el1) // Translation Table Base Register 1 EL1
AARCH64REG_WRITE_INLINE(ttbr1_el1)
+#define TTBR_ASID __BITS(63,48)
+#define TTBR_BADDR __BITS(47,0)
+
AARCH64REG_READ_INLINE(vbar_el1) // Vector Base Address Register
AARCH64REG_WRITE_INLINE(vbar_el1)
Index: src/sys/arch/aarch64/include/pte.h
diff -u src/sys/arch/aarch64/include/pte.h:1.8 src/sys/arch/aarch64/include/pte.h:1.9
--- src/sys/arch/aarch64/include/pte.h:1.8 Wed Sep 11 11:43:15 2019
+++ src/sys/arch/aarch64/include/pte.h Wed Sep 11 18:19:35 2019
@@ -1,4 +1,4 @@
-/* $NetBSD: pte.h,v 1.8 2019/09/11 11:43:15 jmcneill Exp $ */
+/* $NetBSD: pte.h,v 1.9 2019/09/11 18:19:35 skrll Exp $ */
/*-
* Copyright (c) 2014 The NetBSD Foundation, Inc.
@@ -128,69 +128,8 @@ typedef uint64_t pt_entry_t; /* L3(4k) t
#define Ln_ENTRIES (1 << Ln_ENTRIES_SHIFT)
#define Ln_TABLE_SIZE (8 << Ln_ENTRIES_SHIFT)
-
-/* TCR_EL1 - Translation Control Register */
-#define TCR_TBI1 __BIT(38) /* ignore Top Byte TTBR1_EL1 */
-#define TCR_TBI0 __BIT(37) /* ignore Top Byte TTBR0_EL1 */
-#define TCR_AS64K __BIT(36) /* Use 64K ASIDs */
-#define TCR_IPS __BITS(34,32) /* Intermediate PhysAdr Size */
-#define TCR_IPS_4PB __SHIFTIN(6,TCR_IPS) /* 52 bits ( 4 PB) */
-#define TCR_IPS_256TB __SHIFTIN(5,TCR_IPS) /* 48 bits (256 TB) */
-#define TCR_IPS_16TB __SHIFTIN(4,TCR_IPS) /* 44 bits (16 TB) */
-#define TCR_IPS_4TB __SHIFTIN(3,TCR_IPS) /* 42 bits ( 4 TB) */
-#define TCR_IPS_1TB __SHIFTIN(2,TCR_IPS) /* 40 bits ( 1 TB) */
-#define TCR_IPS_64GB __SHIFTIN(1,TCR_IPS) /* 36 bits (64 GB) */
-#define TCR_IPS_4GB __SHIFTIN(0,TCR_IPS) /* 32 bits (4 GB) */
-#define TCR_TG1 __BITS(31,30) /* TTBR1 Page Granule Size */
-#define TCR_TG1_16KB __SHIFTIN(1,TCR_TG1) /* 16KB page size */
-#define TCR_TG1_4KB __SHIFTIN(2,TCR_TG1) /* 4KB page size */
-#define TCR_TG1_64KB __SHIFTIN(3,TCR_TG1) /* 64KB page size */
-#define TCR_SH1 __BITS(29,28)
-#define TCR_SH1_NONE __SHIFTIN(0,TCR_SH1)
-#define TCR_SH1_OUTER __SHIFTIN(2,TCR_SH1)
-#define TCR_SH1_INNER __SHIFTIN(3,TCR_SH1)
-#define TCR_ORGN1 __BITS(27,26) /* TTBR1 Outer cacheability */
-#define TCR_ORGN1_NC __SHIFTIN(0,TCR_ORGN1) /* Non Cacheable */
-#define TCR_ORGN1_WB_WA __SHIFTIN(1,TCR_ORGN1) /* WriteBack WriteAllocate */
-#define TCR_ORGN1_WT __SHIFTIN(2,TCR_ORGN1) /* WriteThrough */
-#define TCR_ORGN1_WB __SHIFTIN(3,TCR_ORGN1) /* WriteBack */
-#define TCR_IRGN1 __BITS(25,24) /* TTBR1 Inner cacheability */
-#define TCR_IRGN1_NC __SHIFTIN(0,TCR_IRGN1) /* Non Cacheable */
-#define TCR_IRGN1_WB_WA __SHIFTIN(1,TCR_IRGN1) /* WriteBack WriteAllocate */
-#define TCR_IRGN1_WT __SHIFTIN(2,TCR_IRGN1) /* WriteThrough */
-#define TCR_IRGN1_WB __SHIFTIN(3,TCR_IRGN1) /* WriteBack */
-#define TCR_EPD1 __BIT(23) /* Walk Disable for TTBR1_EL1 */
-#define TCR_A1 __BIT(22) /* ASID is in TTBR1_EL1 */
-#define TCR_T1SZ __BITS(21,16) /* Size offset for TTBR1_EL1 */
-#define TCR_TG0 __BITS(15,14) /* TTBR0 Page Granule Size */
-#define TCR_TG0_4KB __SHIFTIN(0,TCR_TG0) /* 4KB page size */
-#define TCR_TG0_64KB __SHIFTIN(1,TCR_TG0) /* 64KB page size */
-#define TCR_TG0_16KB __SHIFTIN(2,TCR_TG0) /* 16KB page size */
-#define TCR_SH0 __BITS(13,12)
-#define TCR_SH0_NONE __SHIFTIN(0,TCR_SH0)
-#define TCR_SH0_OUTER __SHIFTIN(2,TCR_SH0)
-#define TCR_SH0_INNER __SHIFTIN(3,TCR_SH0)
-#define TCR_ORGN0 __BITS(11,10) /* TTBR0 Outer cacheability */
-#define TCR_ORGN0_NC __SHIFTIN(0,TCR_ORGN0) /* Non Cacheable */
-#define TCR_ORGN0_WB_WA __SHIFTIN(1,TCR_ORGN0) /* WriteBack WriteAllocate */
-#define TCR_ORGN0_WT __SHIFTIN(2,TCR_ORGN0) /* WriteThrough */
-#define TCR_ORGN0_WB __SHIFTIN(3,TCR_ORGN0) /* WriteBack */
-#define TCR_IRGN0 __BITS(9,8) /* TTBR0 Inner cacheability */
-#define TCR_IRGN0_NC __SHIFTIN(0,TCR_IRGN0) /* Non Cacheable */
-#define TCR_IRGN0_WB_WA __SHIFTIN(1,TCR_IRGN0) /* WriteBack WriteAllocate */
-#define TCR_IRGN0_WT __SHIFTIN(2,TCR_IRGN0) /* WriteThrough */
-#define TCR_IRGN0_WB __SHIFTIN(3,TCR_IRGN0) /* WriteBack */
-#define TCR_EPD0 __BIT(7) /* Walk Disable for TTBR0 */
-#define TCR_T0SZ __BITS(5,0) /* Size offset for TTBR0_EL1 */
-
-
-/* TTBR0_EL1, TTBR1_EL1 - Translation Table Base Register */
-#define TTBR_ASID __BITS(63,48)
-#define TTBR_BADDR __BITS(47,0)
-
#define TTBR_SEL_VA __BIT(63) /* which TTBR is selected */
-
#elif defined(__arm__)
#include <arm/pte.h>
