Module Name: src Committed By: martin Date: Thu Sep 26 18:14:54 UTC 2019
Modified Files: src/sys/dev/pci [netbsd-8]: pci_subr.c pcireg.h Log Message: Pull up the following revisions, requested by msaitoh in ticket #1388: sys/dev/pci/pcireg.h 1.147 via patch sys/dev/pci/pci_subr.c 1.212, 1.215-1.217 via patch - Change fast back-to-back "capable" to "enable" in pci_subr.c. - Print Primary Discard Timer, Secondary Discard Timer, Discard Timer Status and Discard Timer SERR# Enable bit in pci_subr.c. - Print some DPC register values not with %04x but with %08x because those are 32bit. - Remove whitespace for consistency. - Use macro. - Whitespace fixes. To generate a diff of this commit: cvs rdiff -u -r1.183.2.11 -r1.183.2.12 src/sys/dev/pci/pci_subr.c cvs rdiff -u -r1.130.2.8 -r1.130.2.9 src/sys/dev/pci/pcireg.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
Modified files: Index: src/sys/dev/pci/pci_subr.c diff -u src/sys/dev/pci/pci_subr.c:1.183.2.11 src/sys/dev/pci/pci_subr.c:1.183.2.12 --- src/sys/dev/pci/pci_subr.c:1.183.2.11 Wed Jul 17 15:55:31 2019 +++ src/sys/dev/pci/pci_subr.c Thu Sep 26 18:14:54 2019 @@ -1,4 +1,4 @@ -/* $NetBSD: pci_subr.c,v 1.183.2.11 2019/07/17 15:55:31 martin Exp $ */ +/* $NetBSD: pci_subr.c,v 1.183.2.12 2019/09/26 18:14:54 martin Exp $ */ /* * Copyright (c) 1997 Zubin D. Dittia. All rights reserved. @@ -40,7 +40,7 @@ */ #include <sys/cdefs.h> -__KERNEL_RCSID(0, "$NetBSD: pci_subr.c,v 1.183.2.11 2019/07/17 15:55:31 martin Exp $"); +__KERNEL_RCSID(0, "$NetBSD: pci_subr.c,v 1.183.2.12 2019/09/26 18:14:54 martin Exp $"); #ifdef _KERNEL_OPT #include "opt_pci.h" @@ -209,7 +209,7 @@ static const struct pci_class pci_subcla /* PCI bridge programming interface */ static const struct pci_class pci_interface_pcibridge[] = { - { "", PCI_INTERFACE_BRIDGE_PCI_PCI, NULL, }, + { "", PCI_INTERFACE_BRIDGE_PCI_PCI, NULL, }, { "subtractive decode", PCI_INTERFACE_BRIDGE_PCI_SUBDEC, NULL, }, { NULL, 0, NULL, }, }; @@ -223,8 +223,8 @@ static const struct pci_class pci_interf /* Advanced Switching programming interface */ static const struct pci_class pci_interface_advsw[] = { - { "custom interface", PCI_INTERFACE_ADVSW_CUSTOM, NULL, }, - { "ASI-SIG", PCI_INTERFACE_ADVSW_ASISIG, NULL, }, + { "custom interface", PCI_INTERFACE_ADVSW_CUSTOM, NULL, }, + { "ASI-SIG", PCI_INTERFACE_ADVSW_ASISIG, NULL, }, { NULL, 0, NULL, }, }; @@ -304,7 +304,7 @@ static const struct pci_class pci_subcla /* * Class 0x08. * Base system peripheral. - */ + */ /* PIC programming interface */ static const struct pci_class pci_interface_pic[] = { @@ -429,10 +429,10 @@ static const struct pci_class pci_interf /* IPMI programming interface */ static const struct pci_class pci_interface_ipmi[] = { - { "SMIC", PCI_INTERFACE_IPMI_SMIC, NULL,}, - { "keyboard", PCI_INTERFACE_IPMI_KBD, NULL,}, - { "block transfer", PCI_INTERFACE_IPMI_BLOCKXFER, NULL,}, - { NULL, 0, NULL,}, + { "SMIC", PCI_INTERFACE_IPMI_SMIC, NULL, }, + { "keyboard", PCI_INTERFACE_IPMI_KBD, NULL, }, + { "block transfer", PCI_INTERFACE_IPMI_BLOCKXFER, NULL, }, + { NULL, 0, NULL, }, }; /* Subclasses */ @@ -478,8 +478,8 @@ static const struct pci_class pci_subcla /* Intelligent IO programming interface */ static const struct pci_class pci_interface_i2o[] = { - { "FIFO at offset 0x40", PCI_INTERFACE_I2O_FIFOAT40, NULL,}, - { NULL, 0, NULL,}, + { "FIFO at offset 0x40", PCI_INTERFACE_I2O_FIFOAT40, NULL, }, + { NULL, 0, NULL, }, }; /* Subclasses */ @@ -494,9 +494,9 @@ static const struct pci_class pci_subcla * Satellite communication controller. */ static const struct pci_class pci_subclass_satcom[] = { - { "TV", PCI_SUBCLASS_SATCOM_TV, NULL, }, - { "audio", PCI_SUBCLASS_SATCOM_AUDIO, NULL, }, - { "voice", PCI_SUBCLASS_SATCOM_VOICE, NULL, }, + { "TV", PCI_SUBCLASS_SATCOM_TV, NULL, }, + { "audio", PCI_SUBCLASS_SATCOM_AUDIO, NULL, }, + { "voice", PCI_SUBCLASS_SATCOM_VOICE, NULL, }, { "data", PCI_SUBCLASS_SATCOM_DATA, NULL, }, { "miscellaneous", PCI_SUBCLASS_SATCOM_MISC, NULL, }, { NULL, 0, NULL, }, @@ -507,9 +507,9 @@ static const struct pci_class pci_subcla * Encryption/Decryption controller. */ static const struct pci_class pci_subclass_crypto[] = { - { "network/computing", PCI_SUBCLASS_CRYPTO_NETCOMP, NULL, }, + { "network/computing", PCI_SUBCLASS_CRYPTO_NETCOMP, NULL, }, { "entertainment", PCI_SUBCLASS_CRYPTO_ENTERTAINMENT, NULL,}, - { "miscellaneous", PCI_SUBCLASS_CRYPTO_MISC, NULL, }, + { "miscellaneous", PCI_SUBCLASS_CRYPTO_MISC, NULL, }, { NULL, 0, NULL, }, }; @@ -585,7 +585,7 @@ DEV_VERBOSE_DEFINE(pci); * a positive value if the dest buffer would have overflowed. */ -static int __printflike(3,4) +static int __printflike(3, 4) snappendf(char **dest, size_t *len, const char * restrict fmt, ...) { va_list ap; @@ -609,7 +609,7 @@ snappendf(char **dest, size_t *len, cons /* Update dest & len to point at trailing NUL */ *dest += count; *len -= count; - + return 0; } @@ -1285,7 +1285,7 @@ pci_conf_print_pcix_cap_2ndbusmode(int n printf("PCI-X 266 (Mode 2)\n"); else printf("PCI-X 533 (Mode 2)\n"); - + printf(" Error protection: %s\n", (num <= 3) ? "parity" : "ECC"); switch (num & 0x03) { default: @@ -1524,7 +1524,7 @@ pci_conf_print_subsystem_cap(const pcire reg = regs[o2i(capoff + PCI_CAP_SUBSYS_ID)]; printf("\n Subsystem ID Capability Register\n"); - printf(" Subsystem ID : 0x%08x\n", reg); + printf(" Subsystem ID: 0x%08x\n", reg); } /* XXX pci_conf_print_agp8_cap */ @@ -1564,16 +1564,16 @@ pci_conf_print_secure_cap(const pcireg_t onoff("IOMMU Miscellaneous Information Register 1", reg, PCI_SECURE_CAP_EXT); havemisc1 = reg & PCI_SECURE_CAP_EXT; - + reg = regs[o2i(capoff + PCI_SECURE_IOMMU_BAL)]; printf(" Base Address Low Register: 0x%08x\n", reg); onoff("Enable", reg, PCI_SECURE_IOMMU_BAL_EN); reg2 = regs[o2i(capoff + PCI_SECURE_IOMMU_BAH)]; printf(" Base Address High Register: 0x%08x\n", reg2); - printf(" Base Address : 0x%016" PRIx64 "\n", + printf(" Base Address: 0x%016" PRIx64 "\n", ((uint64_t)reg2 << 32) | (reg & (PCI_SECURE_IOMMU_BAL_H | PCI_SECURE_IOMMU_BAL_L))); - + reg = regs[o2i(capoff + PCI_SECURE_IOMMU_RANGE)]; printf(" IOMMU Range Register: 0x%08x\n", reg); printf(" HyperTransport UnitID: 0x%02x\n", @@ -1607,7 +1607,7 @@ pci_conf_print_secure_cap(const pcireg_t if (!havemisc1) return; - + reg = regs[o2i(capoff + PCI_SECURE_IOMMU_MISC1)]; printf(" Miscellaneous Information Register 1: 0x%08x\n", reg); printf(" MSI Message number (GA): 0x%02x\n", @@ -1985,7 +1985,7 @@ pci_conf_print_pcie_cap(const pcireg_t * if (check_slot == true) { pcireg_t slcap; - + /* Slot Capability Register */ slcap = reg = regs[o2i(capoff + PCIE_SLCAP)]; printf(" Slot Capability Register: 0x%08x\n", reg); @@ -2146,7 +2146,6 @@ pci_conf_print_pcie_cap(const pcireg_t * default: printf("(reserved value)\n"); break; - } printf(" LN System CLS: "); switch (__SHIFTOUT(reg, PCIE_DCAP2_LNSYSCLS)) { @@ -2340,7 +2339,7 @@ pci_conf_print_msix_cap(const pcireg_t * reg = regs[o2i(capoff + PCI_MSIX_CTL)]; printf(" Message Control register: 0x%04x\n", (reg >> 16) & 0xff); - printf(" Table Size: %d\n",PCI_MSIX_CTL_TBLSIZE(reg)); + printf(" Table Size: %d\n", PCI_MSIX_CTL_TBLSIZE(reg)); onoff("Function Mask", reg, PCI_MSIX_CTL_FUNCMASK); onoff("MSI-X Enable", reg, PCI_MSIX_CTL_ENABLE); reg = regs[o2i(capoff + PCI_MSIX_TBLOFFSET)]; @@ -2517,14 +2516,14 @@ pci_conf_print_ea_cap(const pcireg_t *re printf("Reserved\n"); break; } - + printf(" Primary Properties: "); pci_conf_print_ea_cap_prop(__SHIFTOUT(reg, PCI_EA_PP)); printf(" Secondary Properties: "); pci_conf_print_ea_cap_prop(__SHIFTOUT(reg, PCI_EA_SP)); onoff("Writable", reg, PCI_EA_W); onoff("Enable for this entry", reg, PCI_EA_E); - + if (entry_size == 0) { entoff += 4; continue; @@ -2577,7 +2576,7 @@ static struct { { PCI_CAP_AGP, "AGP", pci_conf_print_agp_cap }, { PCI_CAP_VPD, "VPD", NULL }, { PCI_CAP_SLOTID, "SlotID", NULL }, - { PCI_CAP_MSI, "MSI", pci_conf_print_msi_cap }, + { PCI_CAP_MSI, "MSI", pci_conf_print_msi_cap }, { PCI_CAP_CPCI_HOTSWAP, "CompactPCI Hot-swapping", NULL }, { PCI_CAP_PCIX, "PCI-X", pci_conf_print_pcix_cap }, { PCI_CAP_LDT, "HyperTransport", pci_conf_print_ht_cap }, @@ -2620,7 +2619,7 @@ pci_conf_find_cap(const pcireg_t *regs, default: return 0; } - + for (off = PCI_CAPLIST_PTR(regs[o2i(capptr)]); off != 0; off = PCI_CAPLIST_NEXT(rval)) { rval = regs[o2i(off)]; @@ -3150,7 +3149,7 @@ pci_conf_print_rclink_dcl_cap(const pcir reg = regs[o2i(extcapoff + PCI_RCLINK_DCL_LINKDESC(i))]; printf(" Link Entry %d:\n", i + 1); printf(" Link Description Register: 0x%08x\n", reg); - onoff(" Link Valid", reg,PCI_RCLINK_DCL_LINKDESC_LVALID); + onoff(" Link Valid", reg, PCI_RCLINK_DCL_LINKDESC_LVALID); linktype = reg & PCI_RCLINK_DCL_LINKDESC_LTYPE; onoff2(" Link Type", reg, PCI_RCLINK_DCL_LINKDESC_LTYPE, "Configuration Space", "Memory-Mapped Space"); @@ -3558,7 +3557,7 @@ pci_conf_print_resizbar_cap(const pcireg pcireg_t cap, ctl; unsigned int bars, i, n; char pbuf[MEM_PBUFSIZE]; - + printf("\n Resizable BAR\n"); /* Get Number of Resizable BARs */ @@ -4609,8 +4608,8 @@ pci_conf_print_type1( else printf(" Reserved @ 0x34: 0x%08x\n", regs[o2i(0x34)]); - /* XXX */ - printf(" Expansion ROM Base Address: 0x%08x\n", regs[o2i(0x38)]); + printf(" Expansion ROM Base Address: 0x%08x\n", + regs[o2i(PCI_BRIDGE_EXPROMADDR_REG)]); rval = regs[o2i(PCI_INTERRUPT_REG)]; printf(" Interrupt line: 0x%02x\n", @@ -4654,7 +4653,15 @@ pci_conf_print_type1( onoff("VGA 16bit enable", rval, PCI_BRIDGE_CONTROL_VGA16); onoff("Master abort reporting", rval, PCI_BRIDGE_CONTROL_MABRT); onoff("Secondary bus reset", rval, PCI_BRIDGE_CONTROL_SECBR); - onoff("Fast back-to-back capable", rval,PCI_BRIDGE_CONTROL_SECFASTB2B); + onoff("Fast back-to-back enable", rval, PCI_BRIDGE_CONTROL_SECFASTB2B); + onoff("Primary Discard Timer", rval, + PCI_BRIDGE_CONTROL_PRI_DISC_TIMER); + onoff("Secondary Discard Timer", + rval, PCI_BRIDGE_CONTROL_SEC_DISC_TIMER); + onoff("Discard Timer Status", rval, + PCI_BRIDGE_CONTROL_DISC_TIMER_STAT); + onoff("Discard Timer SERR# Enable", rval, + PCI_BRIDGE_CONTROL_DISC_TIMER_SERR); } static void Index: src/sys/dev/pci/pcireg.h diff -u src/sys/dev/pci/pcireg.h:1.130.2.8 src/sys/dev/pci/pcireg.h:1.130.2.9 --- src/sys/dev/pci/pcireg.h:1.130.2.8 Tue Dec 4 11:29:41 2018 +++ src/sys/dev/pci/pcireg.h Thu Sep 26 18:14:54 2019 @@ -1,4 +1,4 @@ -/* $NetBSD: pcireg.h,v 1.130.2.8 2018/12/04 11:29:41 martin Exp $ */ +/* $NetBSD: pcireg.h,v 1.130.2.9 2019/09/26 18:14:54 martin Exp $ */ /* * Copyright (c) 1995, 1996, 1999, 2000 @@ -1336,6 +1336,8 @@ typedef u_int8_t pci_intr_line_t; #define PCI_BRIDGE_IOHIGH_BASE_MASK 0xffff #define PCI_BRIDGE_IOHIGH_LIMIT_MASK 0xffff +#define PCI_BRIDGE_EXPROMADDR_REG 0x38 + #define PCI_BRIDGE_CONTROL_REG 0x3c #define PCI_BRIDGE_CONTROL_SHIFT 16 #define PCI_BRIDGE_CONTROL_MASK 0xffff