Module Name: src
Committed By: mrg
Date: Fri Oct 4 12:23:37 UTC 2019
Modified Files:
src/sys/arch/x86/pci: pcib.c
Log Message:
add missing break.
surely it is not intended to treat viatech devices with
non VT82C686A's device id as maybe cyrix pci bridges.
To generate a diff of this commit:
cvs rdiff -u -r1.18 -r1.19 src/sys/arch/x86/pci/pcib.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/x86/pci/pcib.c
diff -u src/sys/arch/x86/pci/pcib.c:1.18 src/sys/arch/x86/pci/pcib.c:1.19
--- src/sys/arch/x86/pci/pcib.c:1.18 Mon Jun 17 06:38:29 2019
+++ src/sys/arch/x86/pci/pcib.c Fri Oct 4 12:23:37 2019
@@ -1,4 +1,4 @@
-/* $NetBSD: pcib.c,v 1.18 2019/06/17 06:38:29 msaitoh Exp $ */
+/* $NetBSD: pcib.c,v 1.19 2019/10/04 12:23:37 mrg Exp $ */
/*-
* Copyright (c) 1996, 1998 The NetBSD Foundation, Inc.
@@ -30,7 +30,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: pcib.c,v 1.18 2019/06/17 06:38:29 msaitoh Exp $");
+__KERNEL_RCSID(0, "$NetBSD: pcib.c,v 1.19 2019/10/04 12:23:37 mrg Exp $");
#include <sys/types.h>
#include <sys/param.h>
@@ -150,6 +150,7 @@ pcibmatch(device_t parent, cfdata_t matc
*/
return (0);
}
+ break;
/*
* The Cyrix cs5530 PCI host bridge does not have a broken
* latch on the i8254 clock core, unlike its predecessors
