Module Name: src
Committed By: joerg
Date: Tue Oct 29 16:18:23 UTC 2019
Modified Files:
src/sys/arch/arm/arm32: cpuswitch.S
src/sys/arch/arm/include: armreg.h
src/sys/arch/arm/vfp: vfp_init.c
Log Message:
Explicitly annotate FPU requirements for LLVM MC.
When using GCC, this annotations change the global state, but there is
no push/pop functionality for .fpu to avoid this problem. The state is
local to each inline assembler block with LLVM MC.
To generate a diff of this commit:
cvs rdiff -u -r1.94 -r1.95 src/sys/arch/arm/arm32/cpuswitch.S
cvs rdiff -u -r1.128 -r1.129 src/sys/arch/arm/include/armreg.h
cvs rdiff -u -r1.63 -r1.64 src/sys/arch/arm/vfp/vfp_init.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/arm32/cpuswitch.S
diff -u src/sys/arch/arm/arm32/cpuswitch.S:1.94 src/sys/arch/arm/arm32/cpuswitch.S:1.95
--- src/sys/arch/arm/arm32/cpuswitch.S:1.94 Fri Sep 13 06:30:10 2019
+++ src/sys/arch/arm/arm32/cpuswitch.S Tue Oct 29 16:18:23 2019
@@ -1,4 +1,4 @@
-/* $NetBSD: cpuswitch.S,v 1.94 2019/09/13 06:30:10 skrll Exp $ */
+/* $NetBSD: cpuswitch.S,v 1.95 2019/10/29 16:18:23 joerg Exp $ */
/*
* Copyright 2003 Wasabi Systems, Inc.
@@ -87,10 +87,14 @@
#include <arm/asm.h>
#include <arm/locore.h>
- RCSID("$NetBSD: cpuswitch.S,v 1.94 2019/09/13 06:30:10 skrll Exp $")
+ RCSID("$NetBSD: cpuswitch.S,v 1.95 2019/10/29 16:18:23 joerg Exp $")
/* LINTSTUB: include <sys/param.h> */
+#ifdef FPU_VFP
+ .fpu vfpv2
+#endif
+
#undef IRQdisable
#undef IRQenable
Index: src/sys/arch/arm/include/armreg.h
diff -u src/sys/arch/arm/include/armreg.h:1.128 src/sys/arch/arm/include/armreg.h:1.129
--- src/sys/arch/arm/include/armreg.h:1.128 Mon Aug 12 23:31:48 2019
+++ src/sys/arch/arm/include/armreg.h Tue Oct 29 16:18:23 2019
@@ -1,4 +1,4 @@
-/* $NetBSD: armreg.h,v 1.128 2019/08/12 23:31:48 jmcneill Exp $ */
+/* $NetBSD: armreg.h,v 1.129 2019/10/29 16:18:23 joerg Exp $ */
/*
* Copyright (c) 1998, 2001 Ben Harris
@@ -745,17 +745,17 @@ static inline void armreg_##name##_write
}
/* cp10 registers */
-ARMREG_READ_INLINE2(fpsid, "vmrs\t%0, fpsid") /* VFP System ID */
-ARMREG_READ_INLINE2(fpscr, "vmrs\t%0, fpscr") /* VFP Status/Control Register */
-ARMREG_WRITE_INLINE2(fpscr, "vmsr\tfpscr, %0") /* VFP Status/Control Register */
-ARMREG_READ_INLINE2(mvfr1, "vmrs\t%0, mvfr1") /* Media and VFP Feature Register 1 */
-ARMREG_READ_INLINE2(mvfr0, "vmrs\t%0, mvfr0") /* Media and VFP Feature Register 0 */
-ARMREG_READ_INLINE2(fpexc, "vmrs\t%0, fpexc") /* VFP Exception Register */
-ARMREG_WRITE_INLINE2(fpexc, "vmsr\tfpexc, %0") /* VFP Exception Register */
-ARMREG_READ_INLINE2(fpinst, "fmrx\t%0, fpinst") /* VFP Exception Instruction */
-ARMREG_WRITE_INLINE2(fpinst, "fmxr\tfpinst, %0") /* VFP Exception Instruction */
-ARMREG_READ_INLINE2(fpinst2, "fmrx\t%0, fpinst2") /* VFP Exception Instruction 2 */
-ARMREG_WRITE_INLINE2(fpinst2, "fmxr\tfpinst2, %0") /* VFP Exception Instruction 2 */
+ARMREG_READ_INLINE2(fpsid, ".fpu vfp\n vmrs\t%0, fpsid") /* VFP System ID */
+ARMREG_READ_INLINE2(fpscr, ".fpu vfp\n vmrs\t%0, fpscr") /* VFP Status/Control Register */
+ARMREG_WRITE_INLINE2(fpscr, ".fpu vfp\n vmsr\tfpscr, %0") /* VFP Status/Control Register */
+ARMREG_READ_INLINE2(mvfr1, ".fpu vfp\n vmrs\t%0, mvfr1") /* Media and VFP Feature Register 1 */
+ARMREG_READ_INLINE2(mvfr0, ".fpu vfp\n vmrs\t%0, mvfr0") /* Media and VFP Feature Register 0 */
+ARMREG_READ_INLINE2(fpexc, ".fpu vfp\n vmrs\t%0, fpexc") /* VFP Exception Register */
+ARMREG_WRITE_INLINE2(fpexc, ".fpu vfp\n vmsr\tfpexc, %0") /* VFP Exception Register */
+ARMREG_READ_INLINE2(fpinst, ".fpu vfp\n fmrx\t%0, fpinst") /* VFP Exception Instruction */
+ARMREG_WRITE_INLINE2(fpinst, ".fpu vfp\n vmsr\tfpinst, %0") /* VFP Exception Instruction */
+ARMREG_READ_INLINE2(fpinst2, ".fpu vfp\n fmrx\t%0, fpinst2") /* VFP Exception Instruction 2 */
+ARMREG_WRITE_INLINE2(fpinst2, ".fpu vfp\n fmxr\tfpinst2, %0") /* VFP Exception Instruction 2 */
/* cp15 c0 registers */
ARMREG_READ_INLINE(midr, "p15,0,%0,c0,c0,0") /* Main ID Register */
Index: src/sys/arch/arm/vfp/vfp_init.c
diff -u src/sys/arch/arm/vfp/vfp_init.c:1.63 src/sys/arch/arm/vfp/vfp_init.c:1.64
--- src/sys/arch/arm/vfp/vfp_init.c:1.63 Sat Sep 7 19:42:42 2019
+++ src/sys/arch/arm/vfp/vfp_init.c Tue Oct 29 16:18:23 2019
@@ -1,4 +1,4 @@
-/* $NetBSD: vfp_init.c,v 1.63 2019/09/07 19:42:42 tnn Exp $ */
+/* $NetBSD: vfp_init.c,v 1.64 2019/10/29 16:18:23 joerg Exp $ */
/*
* Copyright (c) 2008 ARM Ltd
@@ -32,7 +32,7 @@
#include "opt_cputypes.h"
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: vfp_init.c,v 1.63 2019/09/07 19:42:42 tnn Exp $");
+__KERNEL_RCSID(0, "$NetBSD: vfp_init.c,v 1.64 2019/10/29 16:18:23 joerg Exp $");
#include <sys/param.h>
#include <sys/types.h>
@@ -63,7 +63,7 @@ static inline void
load_vfpregs_lo(const uint64_t *p)
{
SETFPU;
- __asm __volatile("vldmia\t%0, {d0-d15}" :: "r" (p) : "memory");
+ __asm __volatile(".fpu vfp\n vldmia\t%0, {d0-d15}" :: "r" (p) : "memory");
}
/* FSTMD <X>, {d0-d15} */
@@ -71,7 +71,7 @@ static inline void
save_vfpregs_lo(uint64_t *p)
{
SETFPU;
- __asm __volatile("vstmia\t%0, {d0-d15}" :: "r" (p) : "memory");
+ __asm __volatile(".fpu vfp\n vstmia\t%0, {d0-d15}" :: "r" (p) : "memory");
}
#ifdef CPU_CORTEX
@@ -80,7 +80,7 @@ static inline void
load_vfpregs_hi(const uint64_t *p)
{
SETFPU;
- __asm __volatile("vldmia\t%0, {d16-d31}" :: "r" (&p[16]) : "memory");
+ __asm __volatile(".fpu neon-vfpv4\n vldmia\t%0, {d16-d31}" :: "r" (&p[16]) : "memory");
}
/* FLDMD <X>, {d16-d31} */
@@ -88,7 +88,7 @@ static inline void
save_vfpregs_hi(uint64_t *p)
{
SETFPU;
- __asm __volatile("vstmia\t%0, {d16-d31}" :: "r" (&p[16]) : "memory");
+ __asm __volatile(".fpu neon-vfpv4\nvstmia\t%0, {d16-d31}" :: "r" (&p[16]) : "memory");
}
#endif
