Module Name: src Committed By: jmcneill Date: Fri Nov 1 11:53:35 UTC 2019
Modified Files: src/sys/arch/arm/ti: files.ti omap3_cm.c Added Files: src/sys/arch/arm/ti: omap2_gpmcreg.h omap2_nand.c ti_gpmc.c Log Message: Add NAND flash support. To generate a diff of this commit: cvs rdiff -u -r1.18 -r1.19 src/sys/arch/arm/ti/files.ti cvs rdiff -u -r0 -r1.1 src/sys/arch/arm/ti/omap2_gpmcreg.h \ src/sys/arch/arm/ti/omap2_nand.c src/sys/arch/arm/ti/ti_gpmc.c cvs rdiff -u -r1.3 -r1.4 src/sys/arch/arm/ti/omap3_cm.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
Modified files: Index: src/sys/arch/arm/ti/files.ti diff -u src/sys/arch/arm/ti/files.ti:1.18 src/sys/arch/arm/ti/files.ti:1.19 --- src/sys/arch/arm/ti/files.ti:1.18 Thu Oct 31 17:08:54 2019 +++ src/sys/arch/arm/ti/files.ti Fri Nov 1 11:53:35 2019 @@ -1,4 +1,4 @@ -# $NetBSD: files.ti,v 1.18 2019/10/31 17:08:54 jmcneill Exp $ +# $NetBSD: files.ti,v 1.19 2019/11/01 11:53:35 jmcneill Exp $ # file arch/arm/ti/ti_cpufreq.c soc_ti @@ -112,6 +112,16 @@ device omapfb: rasops16, rasops8, wsemul attach omapfb at fdt with omap3_dss file arch/arm/ti/omap3_dss.c omap3_dss +# Memory controller +device tigpmc { } : fdt +attach tigpmc at fdt with ti_gpmc +file arch/arm/ti/ti_gpmc.c ti_gpmc + +# NAND flash controller +device omapnand: nandbus +attach omapnand at fdt +file arch/arm/ti/omap2_nand.c omapnand + # SOC parameters defflag opt_soc.h SOC_TI defflag opt_soc.h SOC_AM33XX: SOC_TI Index: src/sys/arch/arm/ti/omap3_cm.c diff -u src/sys/arch/arm/ti/omap3_cm.c:1.3 src/sys/arch/arm/ti/omap3_cm.c:1.4 --- src/sys/arch/arm/ti/omap3_cm.c:1.3 Thu Oct 31 01:05:06 2019 +++ src/sys/arch/arm/ti/omap3_cm.c Fri Nov 1 11:53:35 2019 @@ -1,4 +1,4 @@ -/* $NetBSD: omap3_cm.c,v 1.3 2019/10/31 01:05:06 jmcneill Exp $ */ +/* $NetBSD: omap3_cm.c,v 1.4 2019/11/01 11:53:35 jmcneill Exp $ */ /*- * Copyright (c) 2017 Jared McNeill <jmcne...@invisible.ca> @@ -28,7 +28,7 @@ #include <sys/cdefs.h> -__KERNEL_RCSID(1, "$NetBSD: omap3_cm.c,v 1.3 2019/10/31 01:05:06 jmcneill Exp $"); +__KERNEL_RCSID(1, "$NetBSD: omap3_cm.c,v 1.4 2019/11/01 11:53:35 jmcneill Exp $"); #include <sys/param.h> #include <sys/bus.h> @@ -55,6 +55,12 @@ static int omap3_cm_match(device_t, cfda static void omap3_cm_attach(device_t, device_t, void *); static int +omap3_cm_hwmod_nopenable(struct ti_prcm_softc *sc, struct ti_prcm_clk *tc, int enable) +{ + return 0; +} + +static int omap3_cm_hwmod_enable(struct ti_prcm_softc *sc, struct ti_prcm_clk *tc, int enable) { uint32_t val; @@ -92,6 +98,8 @@ omap3_cm_hwmod_enable(struct ti_prcm_sof TI_PRCM_HWMOD_MASK((_name), CM_PER_BASE, __BIT(_bit), (_parent), omap3_cm_hwmod_enable, (_flags)) #define OMAP3_CM_HWMOD_USBHOST(_name, _bit, _parent, _flags) \ TI_PRCM_HWMOD_MASK((_name), CM_USBHOST_BASE, __BIT(_bit), (_parent), omap3_cm_hwmod_enable, (_flags)) +#define OMAP3_CM_HWMOD_NOP(_name, _parent) \ + TI_PRCM_HWMOD_MASK((_name), 0, 0, (_parent), omap3_cm_hwmod_nopenable, 0) static const char * const compatible[] = { "ti,omap3-cm", @@ -154,6 +162,8 @@ static struct ti_prcm_clk omap3_cm_clks[ OMAP3_CM_HWMOD_PER("gpio6", 17, "PERIPH_CLK", 0), OMAP3_CM_HWMOD_USBHOST("usb_host_hs", 0, "PERIPH_CLK", 0), + + OMAP3_CM_HWMOD_NOP("gpmc", "PERIPH_CLK"), }; static void Added files: Index: src/sys/arch/arm/ti/omap2_gpmcreg.h diff -u /dev/null src/sys/arch/arm/ti/omap2_gpmcreg.h:1.1 --- /dev/null Fri Nov 1 11:53:35 2019 +++ src/sys/arch/arm/ti/omap2_gpmcreg.h Fri Nov 1 11:53:35 2019 @@ -0,0 +1,236 @@ +/* $NetBSD: omap2_gpmcreg.h,v 1.1 2019/11/01 11:53:35 jmcneill Exp $ */ +/* + * Copyright (c) 2007 Microsoft + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by Microsoft + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTERS BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#ifndef _OMAP2430GPMCREG_H +#define _OMAP2430GPMCREG_H + +/* + * Header for OMAP2 General Purpose Memory Controller + */ + +#define GPMC_REVISION 0x000 +#define GPMC_SYSCONFIG 0x010 +#define GPMC_SYSSTATUS 0x014 +#define GPMC_IRQSTATUS 0x018 +#define GPMC_IRQENABLE 0x01C +#define GPMC_TIMEOUT_CONTROL 0x040 +#define GPMC_ERR_ADDRESS 0x044 +#define GPMC_ERR_TYPE 0x048 +#define GPMC_CONFIG 0x050 +#define GPMC_STATUS 0x054 +#define GPMC_CONFIG1_0 0x060 +#define GPMC_CONFIG2_0 0x064 +#define GPMC_CONFIG3_0 0x068 +#define GPMC_CONFIG4_0 0x06C +#define GPMC_CONFIG5_0 0x070 +#define GPMC_CONFIG6_0 0x074 +#define GPMC_CONFIG7_0 0x078 +#define GPMC_NAND_COMMAND_0 0x07C +#define GPMC_NAND_ADDRESS_0 0x080 +#define GPMC_NAND_DATA_0 0x084 +#define GPMC_CONFIG1_1 0x090 +#define GPMC_CONFIG2_1 0x094 +#define GPMC_CONFIG3_1 0x098 +#define GPMC_CONFIG4_1 0x09C +#define GPMC_CONFIG5_1 0x0A0 +#define GPMC_CONFIG6_1 0x0A4 +#define GPMC_CONFIG7_1 0x0A8 +#define GPMC_NAND_COMMAND_1 0x0AC +#define GPMC_NAND_ADDRESS_1 0x0B0 +#define GPMC_NAND_DATA_1 0x0B4 +#define GPMC_CONFIG1_2 0x0C0 +#define GPMC_CONFIG2_2 0x0C4 +#define GPMC_CONFIG3_2 0x0C8 +#define GPMC_CONFIG4_2 0x0CC +#define GPMC_CONFIG5_2 0x0D0 +#define GPMC_CONFIG6_2 0x0D4 +#define GPMC_CONFIG7_2 0x0D8 +#define GPMC_NAND_COMMAND_2 0x0DC +#define GPMC_NAND_ADDRESS_2 0x0E0 +#define GPMC_NAND_DATA_2 0x0E4 +#define GPMC_CONFIG1_3 0x0F0 +#define GPMC_CONFIG2_3 0x0F4 +#define GPMC_CONFIG3_3 0x0F8 +#define GPMC_CONFIG4_3 0x0FC +#define GPMC_CONFIG5_3 0x100 +#define GPMC_CONFIG6_3 0x104 +#define GPMC_CONFIG7_3 0x108 +#define GPMC_NAND_COMMAND_3 0x10C +#define GPMC_NAND_ADDRESS_3 0x110 +#define GPMC_NAND_DATA_3 0x114 +#define GPMC_CONFIG1_4 0x120 +#define GPMC_CONFIG2_4 0x124 +#define GPMC_CONFIG3_4 0x128 +#define GPMC_CONFIG4_4 0x12C +#define GPMC_CONFIG5_4 0x130 +#define GPMC_CONFIG6_4 0x134 +#define GPMC_CONFIG7_4 0x138 +#define GPMC_NAND_COMMAND_4 0x13C +#define GPMC_NAND_ADDRESS_4 0x140 +#define GPMC_NAND_DATA_4 0x144 +#define GPMC_CONFIG1_5 0x150 +#define GPMC_CONFIG2_5 0x154 +#define GPMC_CONFIG3_5 0x158 +#define GPMC_CONFIG4_5 0x15C +#define GPMC_CONFIG5_5 0x160 +#define GPMC_CONFIG6_5 0x164 +#define GPMC_CONFIG7_5 0x168 +#define GPMC_NAND_COMMAND_5 0x16C +#define GPMC_NAND_ADDRESS_5 0x170 +#define GPMC_NAND_DATA_5 0x174 +#define GPMC_CONFIG1_6 0x180 +#define GPMC_CONFIG2_6 0x184 +#define GPMC_CONFIG3_6 0x188 +#define GPMC_CONFIG4_6 0x18C +#define GPMC_CONFIG5_6 0x190 +#define GPMC_CONFIG6_6 0x194 +#define GPMC_CONFIG7_6 0x198 +#define GPMC_NAND_COMMAND_6 0x19C +#define GPMC_NAND_ADDRESS_6 0x1A0 +#define GPMC_NAND_DATA_6 0x1A4 +#define GPMC_CONFIG1_7 0x1B0 +#define GPMC_CONFIG2_7 0x1B4 +#define GPMC_CONFIG3_7 0x1B8 +#define GPMC_CONFIG4_7 0x1BC +#define GPMC_CONFIG5_7 0x1C0 +#define GPMC_CONFIG6_7 0x1C4 +#define GPMC_CONFIG7_7 0x1C8 +#define GPMC_NAND_COMMAND_7 0x1CC +#define GPMC_NAND_ADDRESS_7 0x1D0 +#define GPMC_NAND_DATA_7 0x1D4 +#define GPMC_PREFETCH_CONFIG1 0x1E0 +#define GPMC_PREFETCH_CONFIG2 0x1E4 +#define GPMC_PREFETCH_CONTROL 0x1EC +#define GPMC_CONFIG1_6 0x180 +#define GPMC_CONFIG2_6 0x184 +#define GPMC_CONFIG3_6 0x188 +#define GPMC_CONFIG4_6 0x18C +#define GPMC_CONFIG5_6 0x190 +#define GPMC_CONFIG6_6 0x194 +#define GPMC_CONFIG7_6 0x198 +#define GPMC_NAND_COMMAND_6 0x19C +#define GPMC_NAND_ADDRESS_6 0x1A0 +#define GPMC_NAND_DATA_6 0x1A4 +#define GPMC_CONFIG1_7 0x1B0 +#define GPMC_CONFIG2_7 0x1B4 +#define GPMC_CONFIG3_7 0x1B8 +#define GPMC_CONFIG4_7 0x1BC +#define GPMC_CONFIG5_7 0x1C0 +#define GPMC_CONFIG6_7 0x1C4 +#define GPMC_CONFIG7_7 0x1C8 +#define GPMC_NAND_COMMAND_7 0x1CC +#define GPMC_NAND_ADDRESS_7 0x1D0 +#define GPMC_NAND_DATA_7 0x1D4 +#define GPMC_PREFETCH_CONFIG1 0x1E0 +#define GPMC_PREFETCH_CONFIG2 0x1E4 +#define GPMC_PREFETCH_CONTROL 0x1EC +#define GPMC_PREFETCH_STATUS 0x1F0 +#define GPMC_ECC_CONFIG 0x1F4 +#define GPMC_ECC_CONTROL 0x1F8 +#define GPMC_ECC_SIZE_CONFIG 0x1FC +#define GPMC_ECC1_RESULT 0x200 +#define GPMC_ECC2_RESULT 0x204 +#define GPMC_ECC3_RESULT 0x208 +#define GPMC_ECC4_RESULT 0x20C +#define GPMC_ECC5_RESULT 0x210 +#define GPMC_ECC6_RESULT 0x214 +#define GPMC_ECC7_RESULT 0x218 +#define GPMC_ECC8_RESULT 0x21C +#define GPMC_ECC9_RESULT 0x220 +#define GPMC_TESTMODE_CTRL 0x230 +#define GPMC_PSA_LSB 0x234 +#define GPMC_PSA_MSB 0x238 + +#define GPMC_SIZE (GPMC_PSA_MSB + 4) +#define GPMC_NCS 8 /* # Chip Selects */ +#define GPMC_CS_SIZE (GPMC_CONFIG1_1 - GPMC_CONFIG1_0) + +#define GPMC_CS_CONFIG_BASE(base, cs) \ + ((base) + GPMC_CONFIG1_0 + (cs) * GPMC_CS_SIZE) +#define GPMC_CS_CONFIG(cs) \ + (GPMC_CONFIG1_0 + (cs) * GPMC_CS_SIZE) + +#define GPMC_CONFIG1_i (GPMC_CONFIG1_0 - GPMC_CONFIG1_0) +#define GPMC_CONFIG2_i (GPMC_CONFIG2_0 - GPMC_CONFIG1_0) +#define GPMC_CONFIG3_i (GPMC_CONFIG3_0 - GPMC_CONFIG1_0) +#define GPMC_CONFIG4_i (GPMC_CONFIG4_0 - GPMC_CONFIG1_0) +#define GPMC_CONFIG5_i (GPMC_CONFIG5_0 - GPMC_CONFIG1_0) +#define GPMC_CONFIG6_i (GPMC_CONFIG6_0 - GPMC_CONFIG1_0) +#define GPMC_CONFIG7_i (GPMC_CONFIG7_0 - GPMC_CONFIG1_0) + +/* + * GPMC OMAP2430_GPMC_REVISION + */ +#define GPMC_REVISION_REV __BITS(7,0) +#define GPMC_REVISION_REV_MAJ(r) (((r) >> 4) & 0xf) +#define GPMC_REVISION_REV_MIN(r) (((r) >> 0) & 0xf) + +/* + * GPMC CONFIG7_[0-7] bits + */ +#define GPMC_CONFIG7_BASEADDRESS __BITS(5,0) +#define GPMC_CONFIG7_CSVALID __BIT(6) +#define GPMC_CONFIG7_MASKADDRESS __BITS(11,8) +#define GPMC_CONFIG7(m, b) (((m) << 8) | (((b) >> 24) & 0x3f)) +#define GPMC_CONFIG7_MASK_256M 0x0 +#define GPMC_CONFIG7_MASK_128M 0x8 +#define GPMC_CONFIG7_MASK_64M 0xc +#define GPMC_CONFIG7_MASK_32M 0xe +#define GPMC_CONFIG7_MASK_16M 0xf + +static __inline ulong +omap_gpmc_config7_addr(uint32_t r) +{ + return ((r) & GPMC_CONFIG7_BASEADDRESS) << 24; +} +static __inline ulong +omap_gpmc_config7_size(uint32_t r) +{ + uint i; + uint mask; + const struct { + uint mask; + ulong size; + } gpmc_config7_size_tab[5] = { + { GPMC_CONFIG7_MASK_256M, (256 << 20) }, + { GPMC_CONFIG7_MASK_128M, (128 << 20) }, + { GPMC_CONFIG7_MASK_64M, ( 64 << 20) }, + { GPMC_CONFIG7_MASK_32M, ( 32 << 20) }, + { GPMC_CONFIG7_MASK_16M, ( 16 << 20) }, + }; + mask = ((r) & GPMC_CONFIG7_MASKADDRESS) >> 8; + for (i=0; i < 5; i++) { + if (gpmc_config7_size_tab[i].mask == mask) + return gpmc_config7_size_tab[i].size; + } + return 0; +} + +#endif /* _OMAP2430GPMCREG_H */ Index: src/sys/arch/arm/ti/omap2_nand.c diff -u /dev/null src/sys/arch/arm/ti/omap2_nand.c:1.1 --- /dev/null Fri Nov 1 11:53:35 2019 +++ src/sys/arch/arm/ti/omap2_nand.c Fri Nov 1 11:53:35 2019 @@ -0,0 +1,534 @@ +/* $NetBSD: omap2_nand.c,v 1.1 2019/11/01 11:53:35 jmcneill Exp $ */ + +/*- + * Copyright (c) 2010 Department of Software Engineering, + * University of Szeged, Hungary + * Copyright (c) 2010 Adam Hoka <ah...@netbsd.org> + * All rights reserved. + * + * This code is derived from software contributed to The NetBSD Foundation + * by the Department of Software Engineering, University of Szeged, Hungary + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +/* Device driver for the NAND controller found in Texas Instruments OMAP2 + * and later SOCs. + */ + +#include <sys/cdefs.h> +__KERNEL_RCSID(0, "$NetBSD: omap2_nand.c,v 1.1 2019/11/01 11:53:35 jmcneill Exp $"); + +/* TODO move to opt_* */ +#undef OMAP2_NAND_HARDWARE_ECC + +#include <sys/param.h> +#include <sys/systm.h> +#include <sys/cdefs.h> +#include <sys/device.h> + +#include <sys/bus.h> + +#include <arm/ti/omap2_gpmcreg.h> + +#include <dev/nand/nand.h> +#include <dev/nand/onfi.h> + +#include <dev/fdt/fdtvar.h> + +extern struct flash_interface nand_flash_if; +extern int flash_print(void *, const char *); + +/* GPMC_STATUS */ +#define WAIT0 __BIT(8) /* active low */ + +/* GPMC_ECC_CONTROL */ +#define ECCCLEAR __BIT(8) +#define ECCPOINTER __BITS(3,0) + +/* GPMC_ECC_CONFIG */ +#define ECCALGORITHM __BIT(16) +#define ECCCS __BITS(3,1) +#define ECC16B __BIT(7) +#define ECCENABLE __BIT(0) +/* GPMC_ECC_SIZE_CONFIG */ +#define ECCSIZE1 __BITS(29,22) + +/* GPMC_CONFIG1_i */ +#define DEVICETYPE __BITS(11,10) +#define DEVICESIZE __BITS(13,12) + +#define MASKEDINT(mask, integer) ((integer) << (ffs(mask) - 1) & mask) + +/* NAND status register */ +#define NAND_WP_BIT __BIT(4) + +static int omap2_nand_match(device_t, cfdata_t, void *); +static void omap2_nand_attach(device_t, device_t, void *); + +static void omap2_nand_command(device_t self, uint8_t command); +static void omap2_nand_address(device_t self, uint8_t address); +static void omap2_nand_busy(device_t self); +static void omap2_nand_read_1(device_t self, uint8_t *data); +static void omap2_nand_write_1(device_t self, uint8_t data); +static void omap2_nand_read_2(device_t self, uint16_t *data); +static void omap2_nand_write_2(device_t self, uint16_t data); +bool omap2_nand_isbusy(device_t self); +static void omap2_nand_read_buf_1(device_t self, void *buf, size_t len); +static void omap2_nand_read_buf_2(device_t self, void *buf, size_t len); +static void omap2_nand_write_buf_1(device_t self, const void *buf, size_t len); +static void omap2_nand_write_buf_2(device_t self, const void *buf, size_t len); + +#ifdef OMAP2_NAND_HARDWARE_ECC +static int omap2_nand_ecc_init(device_t self); +static int omap2_nand_ecc_prepare(device_t self, int mode); +static int omap2_nand_ecc_compute(device_t self, const uint8_t *data, uint8_t *ecc); +static int omap2_nand_ecc_correct(device_t self, uint8_t *data, const uint8_t *oldecc, + const uint8_t *calcecc); +#endif + +struct omap2_nand_softc { + device_t sc_dev; + device_t sc_nanddev; + + int sc_cs; + int sc_buswidth; /* 0: 8bit, 1: 16bit */ + + struct nand_interface sc_nand_if; + + bus_space_tag_t sc_iot; + bus_space_handle_t sc_ioh; + bus_space_handle_t sc_gpmc_ioh; + + bus_size_t sc_cmd_reg; + bus_size_t sc_addr_reg; + bus_size_t sc_data_reg; +}; + +static const char * compatible[] = { + "ti,omap2-nand", + NULL +}; + +CFATTACH_DECL_NEW(omapnand, sizeof(struct omap2_nand_softc), omap2_nand_match, + omap2_nand_attach, NULL, NULL); + +static inline uint32_t +gpmc_register_read(struct omap2_nand_softc *sc, bus_size_t reg) +{ + return bus_space_read_4(sc->sc_iot, sc->sc_gpmc_ioh, reg); +} + +static inline void +gpmc_register_write(struct omap2_nand_softc *sc, bus_size_t reg, const uint32_t data) +{ + bus_space_write_4(sc->sc_iot, sc->sc_gpmc_ioh, reg, data); +} + +static void +omap2_nand_command(device_t self, uint8_t command) +{ + struct omap2_nand_softc *sc = device_private(self); + + bus_space_write_1(sc->sc_iot, sc->sc_ioh, sc->sc_cmd_reg, command); +}; + +static void +omap2_nand_address(device_t self, uint8_t address) +{ + struct omap2_nand_softc *sc = device_private(self); + + bus_space_write_1(sc->sc_iot, sc->sc_ioh, sc->sc_addr_reg, address); +}; + +bool +omap2_nand_isbusy(device_t self) +{ + struct omap2_nand_softc *sc = device_private(self); + uint8_t status; + + DELAY(1); /* just to be sure we are not early */ + + bus_space_write_1(sc->sc_iot, sc->sc_ioh, + sc->sc_cmd_reg, ONFI_READ_STATUS); + + DELAY(1); + + status = bus_space_read_1(sc->sc_iot, + sc->sc_ioh, sc->sc_data_reg); + + return !(status & ONFI_STATUS_RDY); +}; + +static int +omap2_nand_match(device_t parent, cfdata_t match, void *aux) +{ + struct fdt_attach_args * const faa = aux; + + return of_match_compatible(faa->faa_phandle, compatible); +} + +static void +omap2_nand_attach(device_t parent, device_t self, void *aux) +{ + struct omap2_nand_softc *sc = device_private(self); + struct fdt_attach_args * const faa = aux; + const int phandle = faa->faa_phandle; + struct flash_attach_args flash; + bus_addr_t addr, part_addr; + bus_size_t size, part_size; + const u_int *prop; + uint32_t val; + int len, child; + + if (fdtbus_get_reg(OF_parent(phandle), 0, &addr, &size) != 0) { + aprint_error(": couldn't get registers\n"); + return; + } + + sc->sc_iot = faa->faa_bst; + sc->sc_dev = self; + + prop = fdtbus_get_prop(phandle, "reg", &len); + if (prop == NULL || len < 4) { + aprint_error(": couldn't read reg property\n"); + return; + } + + sc->sc_cs = be32toh(prop[0]); + + /* map i/o space */ + if (bus_space_map(sc->sc_iot, addr, size, 0, &sc->sc_gpmc_ioh) != 0) { + aprint_error(": couldn't map registers\n"); + return; + } + if (bus_space_subregion(sc->sc_iot, sc->sc_gpmc_ioh, GPMC_CS_CONFIG(sc->sc_cs), 0x30, &sc->sc_ioh) != 0) { + aprint_error(": couldn't map cs registers\n"); + return; + } + + aprint_naive("\n"); + aprint_normal(": CS%d\n", sc->sc_cs); + + sc->sc_cmd_reg = GPMC_NAND_COMMAND_0 - GPMC_CONFIG1_0; + sc->sc_addr_reg = GPMC_NAND_ADDRESS_0 - GPMC_CONFIG1_0; + sc->sc_data_reg = GPMC_NAND_DATA_0 - GPMC_CONFIG1_0; + + /* turn off write protection if enabled */ + val = gpmc_register_read(sc, GPMC_CONFIG); + val |= NAND_WP_BIT; + gpmc_register_write(sc, GPMC_CONFIG, val); + + /* + * do the reset dance for NAND + */ + bus_space_write_1(sc->sc_iot, sc->sc_ioh, + sc->sc_cmd_reg, ONFI_RESET); + + omap2_nand_busy(self); + + /* read GPMC_CONFIG1_i to get buswidth */ + val = bus_space_read_4(sc->sc_iot, sc->sc_ioh, GPMC_CONFIG1_i); + + if ((val & DEVICESIZE) == MASKEDINT(DEVICESIZE, 0x01)) { + /* 16bit */ + sc->sc_buswidth = 1; + } else if ((val & DEVICESIZE) == MASKEDINT(DEVICESIZE, 0x00)) { + /* 8bit */ + sc->sc_buswidth = 0; + } else { + panic("invalid buswidth reported by config1"); + } + + nand_init_interface(&sc->sc_nand_if); + + sc->sc_nand_if.command = &omap2_nand_command; + sc->sc_nand_if.address = &omap2_nand_address; + sc->sc_nand_if.read_buf_1 = &omap2_nand_read_buf_1; + sc->sc_nand_if.read_buf_2 = &omap2_nand_read_buf_2; + sc->sc_nand_if.read_1 = &omap2_nand_read_1; + sc->sc_nand_if.read_2 = &omap2_nand_read_2; + sc->sc_nand_if.write_buf_1 = &omap2_nand_write_buf_1; + sc->sc_nand_if.write_buf_2 = &omap2_nand_write_buf_2; + sc->sc_nand_if.write_1 = &omap2_nand_write_1; + sc->sc_nand_if.write_2 = &omap2_nand_write_2; + sc->sc_nand_if.busy = &omap2_nand_busy; + +#ifdef OMAP2_NAND_HARDWARE_ECC + omap2_nand_ecc_init(self); + sc->sc_nand_if.ecc_compute = &omap2_nand_ecc_compute; + sc->sc_nand_if.ecc_correct = &omap2_nand_ecc_correct; + sc->sc_nand_if.ecc_prepare = &omap2_nand_ecc_prepare; + sc->sc_nand_if.ecc.necc_code_size = 3; + sc->sc_nand_if.ecc.necc_block_size = 512; + sc->sc_nand_if.ecc.necc_type = NAND_ECC_TYPE_HW; +#else + sc->sc_nand_if.ecc.necc_code_size = 3; + sc->sc_nand_if.ecc.necc_block_size = 256; +#endif /* OMAP2_NAND_HARDWARE_ECC */ + + if (!pmf_device_register1(sc->sc_dev, NULL, NULL, NULL)) + aprint_error_dev(sc->sc_dev, + "couldn't establish power handler\n"); + + sc->sc_nanddev = nand_attach_mi(&sc->sc_nand_if, sc->sc_dev); + if (sc->sc_nanddev == NULL) + return; + + for (child = OF_child(phandle); child; child = OF_peer(child)) { + if (!fdtbus_status_okay(child)) + continue; + + if (fdtbus_get_reg(child, 0, &part_addr, &part_size) != 0) { + aprint_error_dev(self, "couldn't parse partition %s\n", + fdtbus_get_string(child, "name")); + continue; + } + + memset(&flash, 0, sizeof(flash)); + flash.flash_if = &nand_flash_if; + flash.partinfo.part_offset = part_addr; + flash.partinfo.part_size = part_size; + flash.partinfo.part_flags = 0; + flash.partinfo.part_name = fdtbus_get_string(child, "label"); + if (flash.partinfo.part_name == NULL) + flash.partinfo.part_name = fdtbus_get_string(child, "name"); + + config_found_ia(sc->sc_nanddev, "flashbus", &flash, flash_print); + } +} + +static void +omap2_nand_busy(device_t self) +{ + struct omap2_nand_softc *sc = device_private(self); + + while (!(gpmc_register_read(sc, GPMC_STATUS) & WAIT0)) { + DELAY(1); + } +} + +static void +omap2_nand_read_1(device_t self, uint8_t *data) +{ + struct omap2_nand_softc *sc = device_private(self); + + *data = bus_space_read_1(sc->sc_iot, sc->sc_ioh, sc->sc_data_reg); +} + +static void +omap2_nand_write_1(device_t self, uint8_t data) +{ + struct omap2_nand_softc *sc = device_private(self); + + bus_space_write_1(sc->sc_iot, sc->sc_ioh, sc->sc_data_reg, data); +} + +static void +omap2_nand_read_2(device_t self, uint16_t *data) +{ + struct omap2_nand_softc *sc = device_private(self); + + *data = bus_space_read_2(sc->sc_iot, sc->sc_ioh, sc->sc_data_reg); +} + +static void +omap2_nand_write_2(device_t self, uint16_t data) +{ + struct omap2_nand_softc *sc = device_private(self); + + bus_space_write_2(sc->sc_iot, sc->sc_ioh, sc->sc_data_reg, data); +} + +static void +omap2_nand_read_buf_1(device_t self, void *buf, size_t len) +{ + struct omap2_nand_softc *sc = device_private(self); + + KASSERT(buf != NULL); + KASSERT(len >= 1); + + bus_space_read_multi_1(sc->sc_iot, sc->sc_ioh, + sc->sc_data_reg, buf, len); +} + +static void +omap2_nand_read_buf_2(device_t self, void *buf, size_t len) +{ + struct omap2_nand_softc *sc = device_private(self); + + KASSERT(buf != NULL); + KASSERT(len >= 2); + KASSERT(!(len & 0x01)); + + bus_space_read_multi_2(sc->sc_iot, sc->sc_ioh, + sc->sc_data_reg, buf, len / 2); +} + +static void +omap2_nand_write_buf_1(device_t self, const void *buf, size_t len) +{ + struct omap2_nand_softc *sc = device_private(self); + + KASSERT(buf != NULL); + KASSERT(len >= 1); + + bus_space_write_multi_1(sc->sc_iot, sc->sc_ioh, + sc->sc_data_reg, buf, len); +} + +static void +omap2_nand_write_buf_2(device_t self, const void *buf, size_t len) +{ + struct omap2_nand_softc *sc = device_private(self); + + KASSERT(buf != NULL); + KASSERT(len >= 2); + KASSERT(!(len & 0x01)); + + bus_space_write_multi_2(sc->sc_iot, sc->sc_ioh, + sc->sc_data_reg, buf, len / 2); +} + +#ifdef OMAP2_NAND_HARDWARE_ECC +static uint32_t +convert_ecc(const uint8_t *ecc) +{ + return ecc[0] | (ecc[1] << 16) | ((ecc[2] & 0xf0) << 20) | + ((ecc[2] & 0x0f) << 8); +} + +static int +omap2_nand_ecc_init(device_t self) +{ + struct omap2_nand_softc *sc = device_private(self); + uint32_t val; + + val = gpmc_register_read(sc, GPMC_ECC_CONTROL); + /* clear ecc, select ecc register 1 */ + val &= ~ECCPOINTER; + val |= ECCCLEAR | MASKEDINT(ECCPOINTER, 1); + gpmc_register_write(sc, GPMC_ECC_CONTROL, val); + + /* XXX too many MAGIC */ + /* set ecc size to 512, set all regs to eccsize1*/ + val = gpmc_register_read(sc, GPMC_ECC_SIZE_CONFIG); + val &= ~ECCSIZE1; + val |= MASKEDINT(ECCSIZE1, 512) | 0x0f; + gpmc_register_write(sc, GPMC_ECC_CONTROL, val); + + return 0; +} + +static int +omap2_nand_ecc_compute(device_t self, const uint8_t *data, uint8_t *ecc) +{ + struct omap2_nand_softc *sc = device_private(self); + uint32_t val; + + /* read ecc result register */ + val = gpmc_register_read(sc, GPMC_ECC1_RESULT); + + ecc[0] = val & 0xff; + ecc[1] = (val >> 16) & 0xff; + ecc[2] = ((val >> 8) & 0x0f) | ((val >> 20) & 0xf0); + + /* disable ecc engine */ + val = gpmc_register_read(sc, GPMC_ECC_CONFIG); + val &= ~ECCENABLE; + gpmc_register_write(sc, GPMC_ECC_CONFIG, val); + + return 0; +} + +static int +omap2_nand_ecc_prepare(device_t self, int mode) +{ + struct omap2_nand_softc *sc = device_private(self); + uint32_t val; + + /* same for read/write */ + switch (mode) { + case NAND_ECC_READ: + case NAND_ECC_WRITE: + val = gpmc_register_read(sc, GPMC_ECC_CONTROL); + /* clear ecc, select ecc register 1 */ + val &= ~ECCPOINTER; + val |= ECCCLEAR | MASKEDINT(ECCPOINTER, 1); + gpmc_register_write(sc, GPMC_ECC_CONTROL, val); + + val = gpmc_register_read(sc, GPMC_ECC_CONFIG); + val &= ~ECCCS; + val |= ECCENABLE | MASKEDINT(ECCCS, sc->sc_cs); + if (sc->sc_buswidth == 1) + val |= ECC16B; + else + val &= ~ECC16B; + gpmc_register_write(sc, GPMC_ECC_CONFIG, val); + + break; + default: + aprint_error_dev(self, "invalid i/o mode for ecc prepare\n"); + return -1; + } + + return 0; +} + +static int +omap2_nand_ecc_correct(device_t self, uint8_t *data, const uint8_t *oldecc, + const uint8_t *calcecc) +{ + uint32_t oecc, cecc, xor; + uint16_t parity, offset; + uint8_t bit; + + oecc = convert_ecc(oldecc); + cecc = convert_ecc(calcecc); + + /* get the difference */ + xor = oecc ^ cecc; + + /* the data was correct if all bits are zero */ + if (xor == 0x00) + return NAND_ECC_OK; + + switch (popcount32(xor)) { + case 12: + /* single byte error */ + parity = xor >> 16; + bit = (parity & 0x07); + offset = (parity >> 3) & 0x01ff; + /* correct bit */ + data[offset] ^= (0x01 << bit); + return NAND_ECC_CORRECTED; + case 1: + return NAND_ECC_INVALID; + default: + /* erased page! */ + if ((oecc == 0x0fff0fff) && (cecc == 0x00000000)) + return NAND_ECC_OK; + + return NAND_ECC_TWOBIT; + } +} +#endif /* !OMAP2_NAND_HARDWARE_ECC */ Index: src/sys/arch/arm/ti/ti_gpmc.c diff -u /dev/null src/sys/arch/arm/ti/ti_gpmc.c:1.1 --- /dev/null Fri Nov 1 11:53:35 2019 +++ src/sys/arch/arm/ti/ti_gpmc.c Fri Nov 1 11:53:35 2019 @@ -0,0 +1,77 @@ +/* $NetBSD: ti_gpmc.c,v 1.1 2019/11/01 11:53:35 jmcneill Exp $ */ + +/*- + * Copyright (c) 2019 Jared McNeill <jmcne...@invisible.ca> + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include <sys/cdefs.h> +__KERNEL_RCSID(0, "$NetBSD: ti_gpmc.c,v 1.1 2019/11/01 11:53:35 jmcneill Exp $"); + +#include <sys/param.h> +#include <sys/bus.h> +#include <sys/device.h> +#include <sys/intr.h> +#include <sys/systm.h> +#include <sys/kernel.h> +#include <sys/kmem.h> + +#include <dev/fdt/fdtvar.h> + +#include <arm/ti/ti_prcm.h> + +static int ti_gpmc_match(device_t, cfdata_t, void *); +static void ti_gpmc_attach(device_t, device_t, void *); + +CFATTACH_DECL_NEW(ti_gpmc, 0, ti_gpmc_match, ti_gpmc_attach, NULL, NULL); + +static const char * compatible[] = { + "ti,omap3430-gpmc", + NULL +}; + +static int +ti_gpmc_match(device_t parent, cfdata_t cf, void *aux) +{ + struct fdt_attach_args * const faa = aux; + + return of_match_compatible(faa->faa_phandle, compatible); +} + +static void +ti_gpmc_attach(device_t parent, device_t self, void *aux) +{ + struct fdt_attach_args * const faa = aux; + const int phandle = faa->faa_phandle; + + if (ti_prcm_enable_hwmod(phandle, 0) != 0) { + aprint_error(": couldn't enable module\n"); + return; + } + + aprint_naive("\n"); + aprint_normal(": GPMC\n"); + + fdt_add_bus(self, phandle, faa); +}