Module Name: src
Committed By: msaitoh
Date: Mon Sep 27 16:52:15 UTC 2021
Modified Files:
src/sys/arch/x86/include: cacheinfo.h
src/usr.sbin/cpuctl/arch: i386.c
Log Message:
Add Load Only TLB and Store Only TLB.
To generate a diff of this commit:
cvs rdiff -u -r1.28 -r1.29 src/sys/arch/x86/include/cacheinfo.h
cvs rdiff -u -r1.119 -r1.120 src/usr.sbin/cpuctl/arch/i386.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/x86/include/cacheinfo.h
diff -u src/sys/arch/x86/include/cacheinfo.h:1.28 src/sys/arch/x86/include/cacheinfo.h:1.29
--- src/sys/arch/x86/include/cacheinfo.h:1.28 Fri Jul 26 10:03:40 2019
+++ src/sys/arch/x86/include/cacheinfo.h Mon Sep 27 16:52:15 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: cacheinfo.h,v 1.28 2019/07/26 10:03:40 msaitoh Exp $ */
+/* $NetBSD: cacheinfo.h,v 1.29 2021/09/27 16:52:15 msaitoh Exp $ */
#ifndef _X86_CACHEINFO_H_
#define _X86_CACHEINFO_H_
@@ -37,8 +37,10 @@ struct x86_cache_info {
#define CAI_L2_STLB2 17 /* Shared L2 TLB (4K/2M pages) */
#define CAI_L2_STLB3 18 /* Shared L2 TLB (2M/4M pages) */
#define CAI_PREFETCH 19 /* Prefetch */
+#define CAI_L1_LD_TLB 20 /* L1 Load Only TLB */
+#define CAI_L1_ST_TLB 21 /* L1 Store Only TLB */
+#define CAI_COUNT 22
-#define CAI_COUNT 20
/*
* AMD Cache Info:
Index: src/usr.sbin/cpuctl/arch/i386.c
diff -u src/usr.sbin/cpuctl/arch/i386.c:1.119 src/usr.sbin/cpuctl/arch/i386.c:1.120
--- src/usr.sbin/cpuctl/arch/i386.c:1.119 Mon Sep 27 16:47:15 2021
+++ src/usr.sbin/cpuctl/arch/i386.c Mon Sep 27 16:52:15 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: i386.c,v 1.119 2021/09/27 16:47:15 msaitoh Exp $ */
+/* $NetBSD: i386.c,v 1.120 2021/09/27 16:52:15 msaitoh Exp $ */
/*-
* Copyright (c) 1999, 2000, 2001, 2006, 2007, 2008 The NetBSD Foundation, Inc.
@@ -57,7 +57,7 @@
#include <sys/cdefs.h>
#ifndef lint
-__RCSID("$NetBSD: i386.c,v 1.119 2021/09/27 16:47:15 msaitoh Exp $");
+__RCSID("$NetBSD: i386.c,v 1.120 2021/09/27 16:52:15 msaitoh Exp $");
#endif /* not lint */
#include <sys/types.h>
@@ -1132,7 +1132,11 @@ intel_cpu_cacheinfo(struct cpu_info *ci)
caitype = CAI_DTLB;
break;
}
- } else
+ } else if (type == CPUID_DATP_TCTYPE_L)
+ caitype = CAI_L1_LD_TLB;
+ else if (type == CPUID_DATP_TCTYPE_S)
+ caitype = CAI_L1_ST_TLB;
+ else
caitype = -1;
break;
case 2:
@@ -2488,6 +2492,14 @@ x86_print_cache_and_tlb_info(struct cpu_
if (sep != NULL)
aprint_verbose("\n");
+ sep = print_tlb_config(ci, CAI_L1_LD_TLB, "Load only TLB:", NULL);
+ if (sep != NULL)
+ aprint_verbose("\n");
+
+ sep = print_tlb_config(ci, CAI_L1_ST_TLB, "Store only TLB:", NULL);
+ if (sep != NULL)
+ aprint_verbose("\n");
+
sep = print_tlb_config(ci, CAI_L2_ITLB, "L2 ITLB:", NULL);
sep = print_tlb_config(ci, CAI_L2_ITLB2, "L2 ITLB:", sep);
if (sep != NULL)
