Module Name: src Committed By: rin Date: Thu Oct 7 09:57:27 UTC 2021
Modified Files: src/sys/arch/arm/arm: cpufunc_asm_armv5.S Log Message: trailing whitespace/tab To generate a diff of this commit: cvs rdiff -u -r1.7 -r1.8 src/sys/arch/arm/arm/cpufunc_asm_armv5.S Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
Modified files: Index: src/sys/arch/arm/arm/cpufunc_asm_armv5.S diff -u src/sys/arch/arm/arm/cpufunc_asm_armv5.S:1.7 src/sys/arch/arm/arm/cpufunc_asm_armv5.S:1.8 --- src/sys/arch/arm/arm/cpufunc_asm_armv5.S:1.7 Sun Mar 30 01:15:03 2014 +++ src/sys/arch/arm/arm/cpufunc_asm_armv5.S Thu Oct 7 09:57:27 2021 @@ -1,4 +1,4 @@ -/* $NetBSD: cpufunc_asm_armv5.S,v 1.7 2014/03/30 01:15:03 matt Exp $ */ +/* $NetBSD: cpufunc_asm_armv5.S,v 1.8 2021/10/07 09:57:27 rin Exp $ */ /* * Copyright (c) 2002, 2005 ARM Limited @@ -32,7 +32,7 @@ * These routines can be used by any core that supports the set/index * operations. */ - + #include "assym.h" #include <machine/asm.h> #include <arm/locore.h> @@ -130,7 +130,7 @@ ENTRY(armv5_dcache_wb_range) bpl 1b mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */ RET - + ENTRY(armv5_dcache_wbinv_range) ldr ip, .Larmv5_line_size cmp r1, #0x4000 @@ -148,7 +148,7 @@ ENTRY(armv5_dcache_wbinv_range) bpl 1b mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */ RET - + /* * Note, we must not invalidate everything. If the range is too big we * must use wb-inv of the entire cache.