Module Name: src
Committed By: msaitoh
Date: Thu Oct 7 13:04:18 UTC 2021
Modified Files:
src/sys/arch/x86/include: cacheinfo.h cpu.h
src/sys/arch/x86/x86: identcpu.c identcpu_subr.c
src/usr.sbin/cpuctl/arch: cpuctl_i386.h i386.c
Log Message:
Move some common functions into x86/identcpu_subr.c. No functional change.
To generate a diff of this commit:
cvs rdiff -u -r1.29 -r1.30 src/sys/arch/x86/include/cacheinfo.h
cvs rdiff -u -r1.131 -r1.132 src/sys/arch/x86/include/cpu.h
cvs rdiff -u -r1.122 -r1.123 src/sys/arch/x86/x86/identcpu.c
cvs rdiff -u -r1.8 -r1.9 src/sys/arch/x86/x86/identcpu_subr.c
cvs rdiff -u -r1.5 -r1.6 src/usr.sbin/cpuctl/arch/cpuctl_i386.h
cvs rdiff -u -r1.121 -r1.122 src/usr.sbin/cpuctl/arch/i386.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/x86/include/cacheinfo.h
diff -u src/sys/arch/x86/include/cacheinfo.h:1.29 src/sys/arch/x86/include/cacheinfo.h:1.30
--- src/sys/arch/x86/include/cacheinfo.h:1.29 Mon Sep 27 16:52:15 2021
+++ src/sys/arch/x86/include/cacheinfo.h Thu Oct 7 13:04:18 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: cacheinfo.h,v 1.29 2021/09/27 16:52:15 msaitoh Exp $ */
+/* $NetBSD: cacheinfo.h,v 1.30 2021/10/07 13:04:18 msaitoh Exp $ */
#ifndef _X86_CACHEINFO_H_
#define _X86_CACHEINFO_H_
@@ -359,4 +359,7 @@ __CI_TBL(0, 0x0f, 0xff, 0, 0, NULL), \
__CI_TBL(0, 0x00, 0, 0, 0, NULL) \
}
+const struct x86_cache_info *cpu_cacheinfo_lookup(
+ const struct x86_cache_info *, uint8_t);
+
#endif /* _X86_CACHEINFO_H_ */
Index: src/sys/arch/x86/include/cpu.h
diff -u src/sys/arch/x86/include/cpu.h:1.131 src/sys/arch/x86/include/cpu.h:1.132
--- src/sys/arch/x86/include/cpu.h:1.131 Sat Aug 14 17:51:20 2021
+++ src/sys/arch/x86/include/cpu.h Thu Oct 7 13:04:18 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: cpu.h,v 1.131 2021/08/14 17:51:20 ryo Exp $ */
+/* $NetBSD: cpu.h,v 1.132 2021/10/07 13:04:18 msaitoh Exp $ */
/*
* Copyright (c) 1990 The Regents of the University of California.
@@ -496,6 +496,7 @@ void identify_hypervisor(void);
/* identcpu_subr.c */
uint64_t cpu_tsc_freq_cpuid(struct cpu_info *);
+void cpu_dcp_cacheinfo(struct cpu_info *, uint32_t);
typedef enum vm_guest {
VM_GUEST_NO = 0,
Index: src/sys/arch/x86/x86/identcpu.c
diff -u src/sys/arch/x86/x86/identcpu.c:1.122 src/sys/arch/x86/x86/identcpu.c:1.123
--- src/sys/arch/x86/x86/identcpu.c:1.122 Thu Oct 7 12:52:27 2021
+++ src/sys/arch/x86/x86/identcpu.c Thu Oct 7 13:04:18 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: identcpu.c,v 1.122 2021/10/07 12:52:27 msaitoh Exp $ */
+/* $NetBSD: identcpu.c,v 1.123 2021/10/07 13:04:18 msaitoh Exp $ */
/*-
* Copyright (c) 1999, 2000, 2001, 2006, 2007, 2008 The NetBSD Foundation, Inc.
@@ -30,7 +30,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: identcpu.c,v 1.122 2021/10/07 12:52:27 msaitoh Exp $");
+__KERNEL_RCSID(0, "$NetBSD: identcpu.c,v 1.123 2021/10/07 13:04:18 msaitoh Exp $");
#include "opt_xen.h"
@@ -101,79 +101,6 @@ static const char cpu_vendor_names[][10]
"Vortex86"
};
-static const struct x86_cache_info *
-cache_info_lookup(const struct x86_cache_info *cai, uint8_t desc)
-{
- int i;
-
- for (i = 0; cai[i].cai_desc != 0; i++) {
- if (cai[i].cai_desc == desc)
- return (&cai[i]);
- }
-
- return (NULL);
-}
-
-/*
- * Get cache info from one of the following:
- * Intel Deterministic Cache Parameter Leaf (0x04)
- * AMD Cache Topology Information Leaf (0x8000001d)
- */
-static void
-cpu_dcp_cacheinfo(struct cpu_info *ci, uint32_t leaf)
-{
- u_int descs[4];
- int type, level, ways, partitions, linesize, sets, totalsize;
- int caitype = -1;
- int i;
-
- for (i = 0; ; i++) {
- x86_cpuid2(leaf, i, descs);
- type = __SHIFTOUT(descs[0], CPUID_DCP_CACHETYPE);
- if (type == CPUID_DCP_CACHETYPE_N)
- break;
- level = __SHIFTOUT(descs[0], CPUID_DCP_CACHELEVEL);
- switch (level) {
- case 1:
- if (type == CPUID_DCP_CACHETYPE_I)
- caitype = CAI_ICACHE;
- else if (type == CPUID_DCP_CACHETYPE_D)
- caitype = CAI_DCACHE;
- else
- caitype = -1;
- break;
- case 2:
- if (type == CPUID_DCP_CACHETYPE_U)
- caitype = CAI_L2CACHE;
- else
- caitype = -1;
- break;
- case 3:
- if (type == CPUID_DCP_CACHETYPE_U)
- caitype = CAI_L3CACHE;
- else
- caitype = -1;
- break;
- default:
- caitype = -1;
- break;
- }
- if (caitype == -1)
- continue;
-
- ways = __SHIFTOUT(descs[1], CPUID_DCP_WAYS) + 1;
- partitions =__SHIFTOUT(descs[1], CPUID_DCP_PARTITIONS)
- + 1;
- linesize = __SHIFTOUT(descs[1], CPUID_DCP_LINESIZE)
- + 1;
- sets = descs[2] + 1;
- totalsize = ways * partitions * linesize * sets;
- ci->ci_cinfo[caitype].cai_totalsize = totalsize;
- ci->ci_cinfo[caitype].cai_associativity = ways;
- ci->ci_cinfo[caitype].cai_linesize = linesize;
- }
-}
-
static void
cpu_probe_intel_cache(struct cpu_info *ci)
{
@@ -196,7 +123,7 @@ cpu_probe_intel_cache(struct cpu_info *c
desc = (descs[i] >> (j * 8)) & 0xff;
if (desc == 0)
continue;
- cai = cache_info_lookup(
+ cai = cpu_cacheinfo_lookup(
intel_cpuid_cache_info, desc);
if (cai != NULL) {
ci->ci_cinfo[cai->cai_index] =
@@ -313,7 +240,7 @@ cpu_probe_amd_cache(struct cpu_info *ci)
cai->cai_associativity = AMD_L2_ECX_C_ASSOC(descs[2]);
cai->cai_linesize = AMD_L2_ECX_C_LS(descs[2]);
- cp = cache_info_lookup(amd_cpuid_l2l3cache_assoc_info,
+ cp = cpu_cacheinfo_lookup(amd_cpuid_l2l3cache_assoc_info,
cai->cai_associativity);
if (cp != NULL)
cai->cai_associativity = cp->cai_associativity;
@@ -329,7 +256,7 @@ cpu_probe_amd_cache(struct cpu_info *ci)
cai->cai_associativity = AMD_L3_EDX_C_ASSOC(descs[3]);
cai->cai_linesize = AMD_L3_EDX_C_LS(descs[3]);
- cp = cache_info_lookup(amd_cpuid_l2l3cache_assoc_info,
+ cp = cpu_cacheinfo_lookup(amd_cpuid_l2l3cache_assoc_info,
cai->cai_associativity);
if (cp != NULL)
cai->cai_associativity = cp->cai_associativity;
Index: src/sys/arch/x86/x86/identcpu_subr.c
diff -u src/sys/arch/x86/x86/identcpu_subr.c:1.8 src/sys/arch/x86/x86/identcpu_subr.c:1.9
--- src/sys/arch/x86/x86/identcpu_subr.c:1.8 Sat Jan 16 15:26:23 2021
+++ src/sys/arch/x86/x86/identcpu_subr.c Thu Oct 7 13:04:18 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: identcpu_subr.c,v 1.8 2021/01/16 15:26:23 jmcneill Exp $ */
+/* $NetBSD: identcpu_subr.c,v 1.9 2021/10/07 13:04:18 msaitoh Exp $ */
/*-
* Copyright (c) 2020 The NetBSD Foundation, Inc.
@@ -35,7 +35,7 @@
* See src/usr.sbin/cpuctl/{Makefile, arch/i386.c}).
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: identcpu_subr.c,v 1.8 2021/01/16 15:26:23 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: identcpu_subr.c,v 1.9 2021/10/07 13:04:18 msaitoh Exp $");
#ifdef _KERNEL_OPT
#include "lapic.h"
@@ -47,6 +47,7 @@ __KERNEL_RCSID(0, "$NetBSD: identcpu_sub
#include <sys/systm.h>
#include <x86/cpuvar.h>
#include <x86/apicvar.h>
+#include <x86/cacheinfo.h>
#include <machine/cpufunc.h>
#include <machine/cputypes.h>
#include <machine/specialreg.h>
@@ -56,6 +57,7 @@ __KERNEL_RCSID(0, "$NetBSD: identcpu_sub
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
+#include <x86/cacheinfo.h>
#include "cpuctl.h"
#include "cpuctl_i386.h"
#endif
@@ -143,3 +145,76 @@ cpu_tsc_freq_cpuid(struct cpu_info *ci)
return freq;
}
+
+const struct x86_cache_info *
+cpu_cacheinfo_lookup(const struct x86_cache_info *cai, uint8_t desc)
+{
+ int i;
+
+ for (i = 0; cai[i].cai_desc != 0; i++) {
+ if (cai[i].cai_desc == desc)
+ return &cai[i];
+ }
+
+ return NULL;
+}
+
+/*
+ * Get cache info from one of the following:
+ * Intel Deterministic Cache Parameter Leaf (0x04)
+ * AMD Cache Topology Information Leaf (0x8000001d)
+ */
+void
+cpu_dcp_cacheinfo(struct cpu_info *ci, uint32_t leaf)
+{
+ u_int descs[4];
+ int type, level, ways, partitions, linesize, sets, totalsize;
+ int caitype = -1;
+ int i;
+
+ for (i = 0; ; i++) {
+ x86_cpuid2(leaf, i, descs);
+ type = __SHIFTOUT(descs[0], CPUID_DCP_CACHETYPE);
+ if (type == CPUID_DCP_CACHETYPE_N)
+ break;
+ level = __SHIFTOUT(descs[0], CPUID_DCP_CACHELEVEL);
+ switch (level) {
+ case 1:
+ if (type == CPUID_DCP_CACHETYPE_I)
+ caitype = CAI_ICACHE;
+ else if (type == CPUID_DCP_CACHETYPE_D)
+ caitype = CAI_DCACHE;
+ else
+ caitype = -1;
+ break;
+ case 2:
+ if (type == CPUID_DCP_CACHETYPE_U)
+ caitype = CAI_L2CACHE;
+ else
+ caitype = -1;
+ break;
+ case 3:
+ if (type == CPUID_DCP_CACHETYPE_U)
+ caitype = CAI_L3CACHE;
+ else
+ caitype = -1;
+ break;
+ default:
+ caitype = -1;
+ break;
+ }
+ if (caitype == -1)
+ continue;
+
+ ways = __SHIFTOUT(descs[1], CPUID_DCP_WAYS) + 1;
+ partitions =__SHIFTOUT(descs[1], CPUID_DCP_PARTITIONS)
+ + 1;
+ linesize = __SHIFTOUT(descs[1], CPUID_DCP_LINESIZE)
+ + 1;
+ sets = descs[2] + 1;
+ totalsize = ways * partitions * linesize * sets;
+ ci->ci_cinfo[caitype].cai_totalsize = totalsize;
+ ci->ci_cinfo[caitype].cai_associativity = ways;
+ ci->ci_cinfo[caitype].cai_linesize = linesize;
+ }
+}
Index: src/usr.sbin/cpuctl/arch/cpuctl_i386.h
diff -u src/usr.sbin/cpuctl/arch/cpuctl_i386.h:1.5 src/usr.sbin/cpuctl/arch/cpuctl_i386.h:1.6
--- src/usr.sbin/cpuctl/arch/cpuctl_i386.h:1.5 Tue Apr 21 02:56:37 2020
+++ src/usr.sbin/cpuctl/arch/cpuctl_i386.h Thu Oct 7 13:04:18 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: cpuctl_i386.h,v 1.5 2020/04/21 02:56:37 msaitoh Exp $ */
+/* $NetBSD: cpuctl_i386.h,v 1.6 2021/10/07 13:04:18 msaitoh Exp $ */
#include <machine/specialreg.h>
#include <x86/cputypes.h>
@@ -45,6 +45,7 @@ extern int cpu_vendor;
/* For x86/x86/identcpu_subr.c */
uint64_t cpu_tsc_freq_cpuid(struct cpu_info *);
+void cpu_dcp_cacheinfo(struct cpu_info *, uint32_t);
/* Interfaces to code in i386-asm.S */
Index: src/usr.sbin/cpuctl/arch/i386.c
diff -u src/usr.sbin/cpuctl/arch/i386.c:1.121 src/usr.sbin/cpuctl/arch/i386.c:1.122
--- src/usr.sbin/cpuctl/arch/i386.c:1.121 Mon Sep 27 17:05:58 2021
+++ src/usr.sbin/cpuctl/arch/i386.c Thu Oct 7 13:04:18 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: i386.c,v 1.121 2021/09/27 17:05:58 msaitoh Exp $ */
+/* $NetBSD: i386.c,v 1.122 2021/10/07 13:04:18 msaitoh Exp $ */
/*-
* Copyright (c) 1999, 2000, 2001, 2006, 2007, 2008 The NetBSD Foundation, Inc.
@@ -57,7 +57,7 @@
#include <sys/cdefs.h>
#ifndef lint
-__RCSID("$NetBSD: i386.c,v 1.121 2021/09/27 17:05:58 msaitoh Exp $");
+__RCSID("$NetBSD: i386.c,v 1.122 2021/10/07 13:04:18 msaitoh Exp $");
#endif /* not lint */
#include <sys/types.h>
@@ -178,7 +178,6 @@ static void powernow_probe(struct cpu_in
static void intel_family_new_probe(struct cpu_info *);
static void via_cpu_probe(struct cpu_info *);
/* (Cache) Info functions */
-static void cpu_dcp_cacheinfo(struct cpu_info *, uint32_t);
static void intel_cpu_cacheinfo(struct cpu_info *);
static void amd_cpu_cacheinfo(struct cpu_info *);
static void via_cpu_cacheinfo(struct cpu_info *);
@@ -190,8 +189,6 @@ static void cpu_probe_hv_features(struct
static void cpu_probe_features(struct cpu_info *);
static void print_bits(const char *, const char *, const char *, uint32_t);
static void identifycpu_cpuids(struct cpu_info *);
-static const struct x86_cache_info *cache_info_lookup(
- const struct x86_cache_info *, uint8_t);
static const char *print_cache_config(struct cpu_info *, int, const char *,
const char *);
static const char *print_tlb_config(struct cpu_info *, int, const char *,
@@ -956,69 +953,6 @@ amd_family6_probe(struct cpu_info *ci)
}
}
-/*
- * Get cache info from one of the following:
- * Intel Deterministic Cache Parameter Leaf (0x04)
- * AMD Cache Topology Information Leaf (0x8000001d)
- */
-static void
-cpu_dcp_cacheinfo(struct cpu_info *ci, uint32_t leaf)
-{
- u_int descs[4];
- int type, level, ways, partitions, linesize, sets, totalsize;
- int caitype = -1;
- int i;
-
- for (i = 0; ; i++) {
- x86_cpuid2(leaf, i, descs);
- type = __SHIFTOUT(descs[0], CPUID_DCP_CACHETYPE);
- if (type == CPUID_DCP_CACHETYPE_N)
- break;
- level = __SHIFTOUT(descs[0], CPUID_DCP_CACHELEVEL);
- switch (level) {
- case 1:
- if (type == CPUID_DCP_CACHETYPE_I)
- caitype = CAI_ICACHE;
- else if (type == CPUID_DCP_CACHETYPE_D)
- caitype = CAI_DCACHE;
- else
- caitype = -1;
- break;
- case 2:
- if (type == CPUID_DCP_CACHETYPE_U)
- caitype = CAI_L2CACHE;
- else
- caitype = -1;
- break;
- case 3:
- if (type == CPUID_DCP_CACHETYPE_U)
- caitype = CAI_L3CACHE;
- else
- caitype = -1;
- break;
- default:
- caitype = -1;
- break;
- }
- if (caitype == -1) {
- aprint_error_dev(ci->ci_dev,
- "error: unknown cache level&type (%d & %d)\n",
- level, type);
- continue;
- }
- ways = __SHIFTOUT(descs[1], CPUID_DCP_WAYS) + 1;
- partitions =__SHIFTOUT(descs[1], CPUID_DCP_PARTITIONS)
- + 1;
- linesize = __SHIFTOUT(descs[1], CPUID_DCP_LINESIZE)
- + 1;
- sets = descs[2] + 1;
- totalsize = ways * partitions * linesize * sets;
- ci->ci_cinfo[caitype].cai_totalsize = totalsize;
- ci->ci_cinfo[caitype].cai_associativity = ways;
- ci->ci_cinfo[caitype].cai_linesize = linesize;
- }
-}
-
static void
intel_cpu_cacheinfo(struct cpu_info *ci)
{
@@ -1057,8 +991,8 @@ intel_cpu_cacheinfo(struct cpu_info *ci)
desc = (descs[i] >> (j * 8)) & 0xff;
if (desc == 0)
continue;
- cai = cache_info_lookup(intel_cpuid_cache_info,
- desc);
+ cai = cpu_cacheinfo_lookup(
+ intel_cpuid_cache_info, desc);
if (cai != NULL)
ci->ci_cinfo[cai->cai_index] = *cai;
else if ((verbose != 0) && (desc != 0xff)
@@ -1299,7 +1233,7 @@ amd_cpu_cacheinfo(struct cpu_info *ci)
cai->cai_totalsize = AMD_L2_EBX_IUTLB_ENTRIES(descs[1]);
cai->cai_associativity = AMD_L2_EBX_IUTLB_ASSOC(descs[1]);
cai->cai_linesize = (4 * 1024);
- cp = cache_info_lookup(amd_cpuid_l2l3cache_assoc_info,
+ cp = cpu_cacheinfo_lookup(amd_cpuid_l2l3cache_assoc_info,
cai->cai_associativity);
if (cp != NULL)
cai->cai_associativity = cp->cai_associativity;
@@ -1310,7 +1244,7 @@ amd_cpu_cacheinfo(struct cpu_info *ci)
cai->cai_totalsize = AMD_L2_EAX_IUTLB_ENTRIES(descs[0]);
cai->cai_associativity = AMD_L2_EAX_IUTLB_ASSOC(descs[0]);
cai->cai_linesize = largepagesize;
- cp = cache_info_lookup(amd_cpuid_l2l3cache_assoc_info,
+ cp = cpu_cacheinfo_lookup(amd_cpuid_l2l3cache_assoc_info,
cai->cai_associativity);
if (cp != NULL)
cai->cai_associativity = cp->cai_associativity;
@@ -1321,7 +1255,7 @@ amd_cpu_cacheinfo(struct cpu_info *ci)
cai->cai_totalsize = AMD_L2_EBX_DTLB_ENTRIES(descs[1]);
cai->cai_associativity = AMD_L2_EBX_DTLB_ASSOC(descs[1]);
cai->cai_linesize = (4 * 1024);
- cp = cache_info_lookup(amd_cpuid_l2l3cache_assoc_info,
+ cp = cpu_cacheinfo_lookup(amd_cpuid_l2l3cache_assoc_info,
cai->cai_associativity);
if (cp != NULL)
cai->cai_associativity = cp->cai_associativity;
@@ -1332,7 +1266,7 @@ amd_cpu_cacheinfo(struct cpu_info *ci)
cai->cai_totalsize = AMD_L2_EAX_DTLB_ENTRIES(descs[0]);
cai->cai_associativity = AMD_L2_EAX_DTLB_ASSOC(descs[0]);
cai->cai_linesize = largepagesize;
- cp = cache_info_lookup(amd_cpuid_l2l3cache_assoc_info,
+ cp = cpu_cacheinfo_lookup(amd_cpuid_l2l3cache_assoc_info,
cai->cai_associativity);
if (cp != NULL)
cai->cai_associativity = cp->cai_associativity;
@@ -1344,7 +1278,7 @@ amd_cpu_cacheinfo(struct cpu_info *ci)
cai->cai_associativity = AMD_L2_ECX_C_ASSOC(descs[2]);
cai->cai_linesize = AMD_L2_ECX_C_LS(descs[2]);
- cp = cache_info_lookup(amd_cpuid_l2l3cache_assoc_info,
+ cp = cpu_cacheinfo_lookup(amd_cpuid_l2l3cache_assoc_info,
cai->cai_associativity);
if (cp != NULL)
cai->cai_associativity = cp->cai_associativity;
@@ -1358,7 +1292,7 @@ amd_cpu_cacheinfo(struct cpu_info *ci)
cai->cai_associativity = AMD_L3_EDX_C_ASSOC(descs[3]);
cai->cai_linesize = AMD_L3_EDX_C_LS(descs[3]);
- cp = cache_info_lookup(amd_cpuid_l2l3cache_assoc_info,
+ cp = cpu_cacheinfo_lookup(amd_cpuid_l2l3cache_assoc_info,
cai->cai_associativity);
if (cp != NULL)
cai->cai_associativity = cp->cai_associativity;
@@ -1376,7 +1310,7 @@ amd_cpu_cacheinfo(struct cpu_info *ci)
cai->cai_totalsize = AMD_L1_1GB_EAX_IUTLB_ENTRIES(descs[0]);
cai->cai_associativity = AMD_L1_1GB_EAX_IUTLB_ASSOC(descs[0]);
cai->cai_linesize = (1024 * 1024 * 1024);
- cp = cache_info_lookup(amd_cpuid_l2l3cache_assoc_info,
+ cp = cpu_cacheinfo_lookup(amd_cpuid_l2l3cache_assoc_info,
cai->cai_associativity);
if (cp != NULL)
cai->cai_associativity = cp->cai_associativity;
@@ -1387,7 +1321,7 @@ amd_cpu_cacheinfo(struct cpu_info *ci)
cai->cai_totalsize = AMD_L1_1GB_EAX_DTLB_ENTRIES(descs[0]);
cai->cai_associativity = AMD_L1_1GB_EAX_DTLB_ASSOC(descs[0]);
cai->cai_linesize = (1024 * 1024 * 1024);
- cp = cache_info_lookup(amd_cpuid_l2l3cache_assoc_info,
+ cp = cpu_cacheinfo_lookup(amd_cpuid_l2l3cache_assoc_info,
cai->cai_associativity);
if (cp != NULL)
cai->cai_associativity = cp->cai_associativity;
@@ -1398,7 +1332,7 @@ amd_cpu_cacheinfo(struct cpu_info *ci)
cai->cai_totalsize = AMD_L2_1GB_EBX_IUTLB_ENTRIES(descs[1]);
cai->cai_associativity = AMD_L2_1GB_EBX_IUTLB_ASSOC(descs[1]);
cai->cai_linesize = (1024 * 1024 * 1024);
- cp = cache_info_lookup(amd_cpuid_l2l3cache_assoc_info,
+ cp = cpu_cacheinfo_lookup(amd_cpuid_l2l3cache_assoc_info,
cai->cai_associativity);
if (cp != NULL)
cai->cai_associativity = cp->cai_associativity;
@@ -1409,7 +1343,7 @@ amd_cpu_cacheinfo(struct cpu_info *ci)
cai->cai_totalsize = AMD_L2_1GB_EBX_DUTLB_ENTRIES(descs[1]);
cai->cai_associativity = AMD_L2_1GB_EBX_DUTLB_ASSOC(descs[1]);
cai->cai_linesize = (1024 * 1024 * 1024);
- cp = cache_info_lookup(amd_cpuid_l2l3cache_assoc_info,
+ cp = cpu_cacheinfo_lookup(amd_cpuid_l2l3cache_assoc_info,
cai->cai_associativity);
if (cp != NULL)
cai->cai_associativity = cp->cai_associativity;
@@ -2372,19 +2306,6 @@ identifycpu(int fd, const char *cpuname)
ucvers.intel1.ucodeversion, ucvers.intel1.platformid);
}
-static const struct x86_cache_info *
-cache_info_lookup(const struct x86_cache_info *cai, uint8_t desc)
-{
- int i;
-
- for (i = 0; cai[i].cai_desc != 0; i++) {
- if (cai[i].cai_desc == desc)
- return (&cai[i]);
- }
-
- return (NULL);
-}
-
static const char *
print_cache_config(struct cpu_info *ci, int cache_tag, const char *name,
const char *sep)
