Module Name:    src
Committed By:   msaitoh
Date:           Sun Oct 10 07:20:01 UTC 2021

Modified Files:
        src/sys/dev/pci: pci_subr.c pcireg.h

Log Message:
Add Some PCI config information:

 - Lane Margining at the Receiver
 - NVME admin interface
 - UFSHCI
 - InfiniBand
 - Host fabric
 - HDA 1.0 with vendor ext
 - USB4 HCI
 - MIPI I3C
 - Cellular controller/modem (+ Ethernet)


To generate a diff of this commit:
cvs rdiff -u -r1.230 -r1.231 src/sys/dev/pci/pci_subr.c
cvs rdiff -u -r1.159 -r1.160 src/sys/dev/pci/pcireg.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/sys/dev/pci/pci_subr.c
diff -u src/sys/dev/pci/pci_subr.c:1.230 src/sys/dev/pci/pci_subr.c:1.231
--- src/sys/dev/pci/pci_subr.c:1.230	Sat Sep 11 19:56:51 2021
+++ src/sys/dev/pci/pci_subr.c	Sun Oct 10 07:20:01 2021
@@ -1,4 +1,4 @@
-/*	$NetBSD: pci_subr.c,v 1.230 2021/09/11 19:56:51 mrg Exp $	*/
+/*	$NetBSD: pci_subr.c,v 1.231 2021/10/10 07:20:01 msaitoh Exp $	*/
 
 /*
  * Copyright (c) 1997 Zubin D. Dittia.  All rights reserved.
@@ -40,7 +40,7 @@
  */
 
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: pci_subr.c,v 1.230 2021/09/11 19:56:51 mrg Exp $");
+__KERNEL_RCSID(0, "$NetBSD: pci_subr.c,v 1.231 2021/10/10 07:20:01 msaitoh Exp $");
 
 #ifdef _KERNEL_OPT
 #include "opt_pci.h"
@@ -174,7 +174,15 @@ static const struct pci_class pci_interf
 static const struct pci_class pci_interface_nvm[] = {
 	{ "vendor specific",	PCI_INTERFACE_NVM_VND,		NULL,	},
 	{ "NVMHCI 1.0",		PCI_INTERFACE_NVM_NVMHCI10,	NULL,	},
-	{ "NVMe",		PCI_INTERFACE_NVM_NVME,		NULL,	},
+	{ "NVMe I/O",		PCI_INTERFACE_NVM_NVME_IO,	NULL,	},
+	{ "NVMe admin",		PCI_INTERFACE_NVM_NVME_ADMIN,	NULL,	},
+	{ NULL,			0,				NULL,	},
+};
+
+/* UFS programming interface */
+static const struct pci_class pci_interface_ufs[] = {
+	{ "vendor specific",	PCI_INTERFACE_UFS_VND,		NULL,	},
+	{ "UFSHCI",		PCI_INTERFACE_UFS_UFSHCI,	NULL,	},
 	{ NULL,			0,				NULL,	},
 };
 
@@ -192,6 +200,8 @@ static const struct pci_class pci_subcla
 	{ "SAS",		PCI_SUBCLASS_MASS_STORAGE_SAS,	NULL,	},
 	{ "Flash",		PCI_SUBCLASS_MASS_STORAGE_NVM,
 	  pci_interface_nvm,	},
+	{ "UFS",		PCI_SUBCLASS_MASS_STORAGE_UFS,
+	  pci_interface_ufs,	},
 	{ "miscellaneous",	PCI_SUBCLASS_MASS_STORAGE_MISC,	NULL,	},
 	{ NULL,			0,				NULL,	},
 };
@@ -208,6 +218,8 @@ static const struct pci_class pci_subcla
 	{ "ISDN",		PCI_SUBCLASS_NETWORK_ISDN,	NULL,	},
 	{ "WorldFip",		PCI_SUBCLASS_NETWORK_WORLDFIP,	NULL,	},
 	{ "PCMIG Multi Computing", PCI_SUBCLASS_NETWORK_PCIMGMULTICOMP, NULL, },
+	{ "InfiniBand",		PCI_SUBCLASS_NETWORK_INFINIBAND, NULL, },
+	{ "Host fabric",	PCI_SUBCLASS_NETWORK_HFC,	NULL, },
 	{ "miscellaneous",	PCI_SUBCLASS_NETWORK_MISC,	NULL,	},
 	{ NULL,			0,				NULL,	},
 };
@@ -236,11 +248,20 @@ static const struct pci_class pci_subcla
  * Class 0x04.
  * Multimedia device.
  */
+
+/* HD Audio programming interface */
+static const struct pci_class pci_interface_hda[] = {
+	{ "HD Audio 1.0",	PCI_INTERFACE_HDAUDIO,		NULL,	},
+	{ "HD Audio 1.0 + vendor ext",	PCI_INTERFACE_HDAUDIO_VND, NULL, },
+	{ NULL,			0,				NULL,	},
+};
+
 static const struct pci_class pci_subclass_multimedia[] = {
 	{ "video",		PCI_SUBCLASS_MULTIMEDIA_VIDEO,	NULL,	},
 	{ "audio",		PCI_SUBCLASS_MULTIMEDIA_AUDIO,	NULL,	},
 	{ "telephony",		PCI_SUBCLASS_MULTIMEDIA_TELEPHONY, NULL,},
-	{ "mixed mode",		PCI_SUBCLASS_MULTIMEDIA_HDAUDIO, NULL, },
+	{ "mixed mode",		PCI_SUBCLASS_MULTIMEDIA_HDAUDIO,
+	  pci_interface_hda, },
 	{ "miscellaneous",	PCI_SUBCLASS_MULTIMEDIA_MISC,	NULL,	},
 	{ NULL,			0,				NULL,	},
 };
@@ -476,6 +497,7 @@ static const struct pci_class pci_interf
 	{ "OHCI",		PCI_INTERFACE_USB_OHCI,		NULL,	},
 	{ "EHCI",		PCI_INTERFACE_USB_EHCI,		NULL,	},
 	{ "xHCI",		PCI_INTERFACE_USB_XHCI,		NULL,	},
+	{ "USB4 HCI",		PCI_INTERFACE_USB_USB4HCI,	NULL,	},
 	{ "other HC",		PCI_INTERFACE_USB_OTHERHC,	NULL,	},
 	{ "device",		PCI_INTERFACE_USB_DEVICE,	NULL,	},
 	{ NULL,			0,				NULL,	},
@@ -505,6 +527,7 @@ static const struct pci_class pci_subcla
 	  pci_interface_ipmi, },
 	{ "SERCOS",		PCI_SUBCLASS_SERIALBUS_SERCOS,	NULL,	},
 	{ "CANbus",		PCI_SUBCLASS_SERIALBUS_CANBUS,	NULL,	},
+	{ "MIPI I3C",		PCI_SUBCLASS_SERIALBUS_MIPI_I3C, NULL,	},
 	{ "miscellaneous",	PCI_SUBCLASS_SERIALBUS_MISC,	NULL,	},
 	{ NULL,			0,				NULL,	},
 };
@@ -521,6 +544,8 @@ static const struct pci_class pci_subcla
 	{ "broadband",		PCI_SUBCLASS_WIRELESS_BROADBAND, NULL,	},
 	{ "802.11a (5 GHz)",	PCI_SUBCLASS_WIRELESS_802_11A,	NULL,	},
 	{ "802.11b (2.4 GHz)",	PCI_SUBCLASS_WIRELESS_802_11B,	NULL,	},
+	{ "Cellular",		PCI_SUBCLASS_WIRELESS_CELL,	NULL,	},
+	{ "Cellular + Ethernet", PCI_SUBCLASS_WIRELESS_CELL_E,	NULL,	},
 	{ "miscellaneous",	PCI_SUBCLASS_WIRELESS_MISC,	NULL,	},
 	{ NULL,			0,				NULL,	},
 };
@@ -4326,9 +4351,9 @@ static struct {
 	  NULL },
 	{ PCI_EXTCAP_VF_RESIZBAR, "VF Resizable BARs",
 	  NULL },
-	{ PCI_EXTCAP_DLF, "Data link Feature", pci_conf_print_dlf_cap },
+	{ PCI_EXTCAP_DLF,	"Data link Feature", pci_conf_print_dlf_cap },
 	{ PCI_EXTCAP_PYSLAY_16GT, "Physical Layer 16.0 GT/s", NULL },
-	{ 0x27, "unknown", NULL },
+	{ PCI_EXTCAP_LMR,	"Lane Margining at the Receiver", NULL },
 	{ PCI_EXTCAP_HIERARCHYID, "Hierarchy ID",
 	  NULL },
 	{ PCI_EXTCAP_NPEM,	"Native PCIe Enclosure Management",

Index: src/sys/dev/pci/pcireg.h
diff -u src/sys/dev/pci/pcireg.h:1.159 src/sys/dev/pci/pcireg.h:1.160
--- src/sys/dev/pci/pcireg.h:1.159	Sun Oct 10 07:09:20 2021
+++ src/sys/dev/pci/pcireg.h	Sun Oct 10 07:20:01 2021
@@ -1,4 +1,4 @@
-/*	$NetBSD: pcireg.h,v 1.159 2021/10/10 07:09:20 msaitoh Exp $	*/
+/*	$NetBSD: pcireg.h,v 1.160 2021/10/10 07:20:01 msaitoh Exp $	*/
 
 /*
  * Copyright (c) 1995, 1996, 1999, 2000
@@ -203,7 +203,11 @@ typedef u_int8_t pci_revision_t;
 #define	PCI_SUBCLASS_MASS_STORAGE_NVM		0x08
 #define		PCI_INTERFACE_NVM_VND			0x00
 #define		PCI_INTERFACE_NVM_NVMHCI10		0x01
-#define		PCI_INTERFACE_NVM_NVME			0x02
+#define		PCI_INTERFACE_NVM_NVME_IO		0x02
+#define		PCI_INTERFACE_NVM_NVME_ADMIN		0x03
+#define	PCI_SUBCLASS_MASS_STORAGE_UFS		0x09
+#define		PCI_INTERFACE_UFS_VND			0x00
+#define		PCI_INTERFACE_UFS_UFSHCI		0x01
 #define	PCI_SUBCLASS_MASS_STORAGE_MISC		0x80
 
 /* 0x02 network subclasses */
@@ -215,6 +219,7 @@ typedef u_int8_t pci_revision_t;
 #define	PCI_SUBCLASS_NETWORK_WORLDFIP		0x05
 #define	PCI_SUBCLASS_NETWORK_PCIMGMULTICOMP	0x06
 #define	PCI_SUBCLASS_NETWORK_INFINIBAND		0x07
+#define	PCI_SUBCLASS_NETWORK_HFC		0x08
 #define	PCI_SUBCLASS_NETWORK_MISC		0x80
 
 /* 0x03 display subclasses */
@@ -230,6 +235,8 @@ typedef u_int8_t pci_revision_t;
 #define	PCI_SUBCLASS_MULTIMEDIA_AUDIO		0x01
 #define	PCI_SUBCLASS_MULTIMEDIA_TELEPHONY	0x02
 #define	PCI_SUBCLASS_MULTIMEDIA_HDAUDIO		0x03
+#define		PCI_INTERFACE_HDAUDIO			0x00
+#define		PCI_INTERFACE_HDAUDIO_VND		0x80
 #define	PCI_SUBCLASS_MULTIMEDIA_MISC		0x80
 
 /* 0x05 memory subclasses */
@@ -345,6 +352,7 @@ typedef u_int8_t pci_revision_t;
 #define		PCI_INTERFACE_USB_OHCI			0x10
 #define		PCI_INTERFACE_USB_EHCI			0x20
 #define		PCI_INTERFACE_USB_XHCI			0x30
+#define		PCI_INTERFACE_USB_USB4HCI		0x40
 #define		PCI_INTERFACE_USB_OTHERHC		0x80
 #define		PCI_INTERFACE_USB_DEVICE		0xfe
 #define	PCI_SUBCLASS_SERIALBUS_FIBER		0x04	/* XXX _FIBRECHANNEL */
@@ -356,6 +364,7 @@ typedef u_int8_t pci_revision_t;
 #define		PCI_INTERFACE_IPMI_BLOCKXFER		0x02
 #define	PCI_SUBCLASS_SERIALBUS_SERCOS		0x08
 #define	PCI_SUBCLASS_SERIALBUS_CANBUS		0x09
+#define	PCI_SUBCLASS_SERIALBUS_MIPI_I3C		0x0a
 #define	PCI_SUBCLASS_SERIALBUS_MISC		0x80
 
 /* 0x0d wireless subclasses */
@@ -368,6 +377,8 @@ typedef u_int8_t pci_revision_t;
 #define	PCI_SUBCLASS_WIRELESS_BROADBAND		0x12
 #define	PCI_SUBCLASS_WIRELESS_802_11A		0x20
 #define	PCI_SUBCLASS_WIRELESS_802_11B		0x21
+#define	PCI_SUBCLASS_WIRELESS_CELL		0x40
+#define	PCI_SUBCLASS_WIRELESS_CELL_E		0x41
 #define	PCI_SUBCLASS_WIRELESS_MISC		0x80
 
 /* 0x0e I2O (Intelligent I/O) subclasses */
@@ -1557,6 +1568,7 @@ struct pci_rom {
 #define	PCI_EXTCAP_VF_RESIZBAR	0x0024	/* VF Resizable BAR */
 #define	PCI_EXTCAP_DLF		0x0025	/* Data link Feature */
 #define	PCI_EXTCAP_PYSLAY_16GT	0x0026	/* Physical Layer 16.0 GT/s */
+#define	PCI_EXTCAP_LMR		0x0027	/* Lane Margining at the Receiver */
 #define	PCI_EXTCAP_HIERARCHYID	0x0028	/* Hierarchy ID */
 #define	PCI_EXTCAP_NPEM		0x0029	/* Native PCIe Enclosure Management */
 

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