Module Name: src
Committed By: skrll
Date: Mon Nov 1 14:45:24 UTC 2021
Modified Files:
src/sys/arch/arm/include: cpu.h cpufunc.h
Log Message:
Move arm_cache_info from cpufunc.h to cpu.h
To generate a diff of this commit:
cvs rdiff -u -r1.120 -r1.121 src/sys/arch/arm/include/cpu.h
cvs rdiff -u -r1.88 -r1.89 src/sys/arch/arm/include/cpufunc.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/include/cpu.h
diff -u src/sys/arch/arm/include/cpu.h:1.120 src/sys/arch/arm/include/cpu.h:1.121
--- src/sys/arch/arm/include/cpu.h:1.120 Sun Oct 31 16:23:47 2021
+++ src/sys/arch/arm/include/cpu.h Mon Nov 1 14:45:24 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: cpu.h,v 1.120 2021/10/31 16:23:47 skrll Exp $ */
+/* $NetBSD: cpu.h,v 1.121 2021/11/01 14:45:24 skrll Exp $ */
/*
* Copyright (c) 1994-1996 Mark Brinicombe.
@@ -156,9 +156,37 @@ static inline void cpu_dosoftints(void);
#include <sys/device_if.h>
#include <sys/evcnt.h>
-#include <arm/cpufunc.h>
#include <machine/param.h>
+/*
+ * Cache info variables.
+ */
+#define CACHE_TYPE_VIVT 0
+#define CACHE_TYPE_xxPT 1
+#define CACHE_TYPE_VIPT 1
+#define CACHE_TYPE_PIxx 2
+#define CACHE_TYPE_PIPT 3
+
+/* PRIMARY CACHE VARIABLES */
+struct arm_cache_info {
+ u_int icache_size;
+ u_int icache_line_size;
+ u_int icache_ways;
+ u_int icache_way_size;
+ u_int icache_sets;
+
+ u_int dcache_size;
+ u_int dcache_line_size;
+ u_int dcache_ways;
+ u_int dcache_way_size;
+ u_int dcache_sets;
+
+ uint8_t cache_type;
+ bool cache_unified;
+ uint8_t icache_type;
+ uint8_t dcache_type;
+};
+
struct cpu_info {
struct cpu_data ci_data; /* MI per-cpu data */
device_t ci_dev; /* Device corresponding to this CPU */
Index: src/sys/arch/arm/include/cpufunc.h
diff -u src/sys/arch/arm/include/cpufunc.h:1.88 src/sys/arch/arm/include/cpufunc.h:1.89
--- src/sys/arch/arm/include/cpufunc.h:1.88 Mon Mar 1 11:29:14 2021
+++ src/sys/arch/arm/include/cpufunc.h Mon Nov 1 14:45:24 2021
@@ -410,35 +410,6 @@ u_int GetCPSR(void);
void cpu_reset (void) __dead;
-/*
- * Cache info variables.
- */
-#define CACHE_TYPE_VIVT 0
-#define CACHE_TYPE_xxPT 1
-#define CACHE_TYPE_VIPT 1
-#define CACHE_TYPE_PIxx 2
-#define CACHE_TYPE_PIPT 3
-
-/* PRIMARY CACHE VARIABLES */
-struct arm_cache_info {
- u_int icache_size;
- u_int icache_line_size;
- u_int icache_ways;
- u_int icache_way_size;
- u_int icache_sets;
-
- u_int dcache_size;
- u_int dcache_line_size;
- u_int dcache_ways;
- u_int dcache_way_size;
- u_int dcache_sets;
-
- uint8_t cache_type;
- bool cache_unified;
- uint8_t icache_type;
- uint8_t dcache_type;
-};
-
#if (ARM_MMU_V6 + ARM_MMU_V7) != 0
extern u_int arm_cache_prefer_mask;
#endif
