Module Name: src
Committed By: jmcneill
Date: Sat Nov 13 01:48:12 UTC 2021
Modified Files:
src/sys/arch/arm/arm: cpufunc.c
src/sys/arch/arm/include: armreg.h
Log Message:
Set ACTLR.SMP=1 on Cortex-A17
To generate a diff of this commit:
cvs rdiff -u -r1.181 -r1.182 src/sys/arch/arm/arm/cpufunc.c
cvs rdiff -u -r1.132 -r1.133 src/sys/arch/arm/include/armreg.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/arm/cpufunc.c
diff -u src/sys/arch/arm/arm/cpufunc.c:1.181 src/sys/arch/arm/arm/cpufunc.c:1.182
--- src/sys/arch/arm/arm/cpufunc.c:1.181 Fri Jul 2 07:15:35 2021
+++ src/sys/arch/arm/arm/cpufunc.c Sat Nov 13 01:48:12 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: cpufunc.c,v 1.181 2021/07/02 07:15:35 skrll Exp $ */
+/* $NetBSD: cpufunc.c,v 1.182 2021/11/13 01:48:12 jmcneill Exp $ */
/*
* arm7tdmi support code Copyright (c) 2001 John Fremlin
@@ -49,7 +49,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: cpufunc.c,v 1.181 2021/07/02 07:15:35 skrll Exp $");
+__KERNEL_RCSID(0, "$NetBSD: cpufunc.c,v 1.182 2021/11/13 01:48:12 jmcneill Exp $");
#include "opt_arm_start.h"
#include "opt_compat_netbsd.h"
@@ -3005,12 +3005,9 @@ armv7_setup(char *args)
CORTEXA15_ACTLR_SMP |
CORTEXA15_ACTLR_SDEH |
0;
-#if 0
} else if (CPU_ID_CORTEX_A12_P(lcputype) ||
- CPU_ID_CORTEX_A17_P(lcputype)) {
- actlr_set =
- CORTEXA17_ACTLR_SMP;
-#endif
+ CPU_ID_CORTEX_A17_P(lcputype)) {
+ actlr_set = CORTEXA17_ACTLR_SMP;
} else if (CPU_ID_CORTEX_A53_P(lcputype)) {
} else if (CPU_ID_CORTEX_A57_P(lcputype)) {
} else if (CPU_ID_CORTEX_A72_P(lcputype)) {
Index: src/sys/arch/arm/include/armreg.h
diff -u src/sys/arch/arm/include/armreg.h:1.132 src/sys/arch/arm/include/armreg.h:1.133
--- src/sys/arch/arm/include/armreg.h:1.132 Sun Oct 10 08:36:49 2021
+++ src/sys/arch/arm/include/armreg.h Sat Nov 13 01:48:12 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: armreg.h,v 1.132 2021/10/10 08:36:49 skrll Exp $ */
+/* $NetBSD: armreg.h,v 1.133 2021/11/13 01:48:12 jmcneill Exp $ */
/*
* Copyright (c) 1998, 2001 Ben Harris
@@ -312,6 +312,12 @@
#define CORTEXA15_ACTLR_IOBEU __BIT(15) /* In order issue in Branch Exec Unit */
#define CORTEXA15_ACTLR_SDEH __BIT(31) /* snoop-delayed exclusive handling */
+/* Cortex-A17 Auxiliary Control Register (CP15 register 1, opcode 1) */
+#define CORTEXA17_ACTLR_SMP __BIT(6) /* SMP */
+#define CORTEXA17_ACTLR_ASSE __BIT(3) /* ACE STREX Signaling Enable */
+#define CORTEXA17_ACTLR_L2PF __BIT(2) /* Enable L2 prefetch */
+#define CORTEXA17_ACTLR_L1PF __BIT(1) /* Enable L1 prefetch */
+
/* Marvell Feroceon Extra Features Register (CP15 register 1, opcode2 0) */
#define FC_DCACHE_REPL_LOCK 0x80000000 /* Replace DCache Lock */
#define FC_DCACHE_STREAM_EN 0x20000000 /* DCache Streaming Switch */
