Module Name: src Committed By: martin Date: Fri Dec 3 19:40:38 UTC 2021
Modified Files: src/sys/dev/pci [netbsd-9]: nvme_pci.c pci.c pci_subr.c pcireg.h ppb.c Log Message: Pull up the following revisions, requested by msaitoh in ticket #1384: sys/dev/pci/pcireg.h 1.152-1.154, 1.156-1.161 sys/dev/pci/pci_subr.c 1.222, 1.227-1.232 via patch sys/dev/pci/nvme_pci.c 1.31 sys/dev/pci/pci.c 1.158, 1.163 sys/dev/pci/ppb.c 1.74 - When parsing Enhanced Allocation entries, use the correct calculation for finding the next entry. - Add 32.0GT/s to the list of pcie speeds (PCIe 5.x.). - Add Some PCI config information: - Lane Margining at the Receiver - NVME admin interface - UFSHCI - InfiniBand - Host fabric - HDA 1.0 with vendor ext - USB4 HCI - MIPI I3C - Cellular controller/modem (+ Ethernet) - Change PCI_VENDOR_MASK and PCI_PRODUCT_MASK to unsigned values, to prevent sign extension of product ID when shifted up into place in PCI_ID_CODE(). Fixes PR kern/56176. - Add LCAP & LCAP2 definitions. - Use PCI-SIG official acronyms for some macros. - Fix typo in some messages. - Fix typo in comments. - Whitespace fixes. To generate a diff of this commit: cvs rdiff -u -r1.26.4.1 -r1.26.4.2 src/sys/dev/pci/nvme_pci.c cvs rdiff -u -r1.154.4.2 -r1.154.4.3 src/sys/dev/pci/pci.c cvs rdiff -u -r1.215.2.4 -r1.215.2.5 src/sys/dev/pci/pci_subr.c cvs rdiff -u -r1.147.4.2 -r1.147.4.3 src/sys/dev/pci/pcireg.h cvs rdiff -u -r1.69 -r1.69.2.1 src/sys/dev/pci/ppb.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
Modified files: Index: src/sys/dev/pci/nvme_pci.c diff -u src/sys/dev/pci/nvme_pci.c:1.26.4.1 src/sys/dev/pci/nvme_pci.c:1.26.4.2 --- src/sys/dev/pci/nvme_pci.c:1.26.4.1 Mon Jun 21 17:25:48 2021 +++ src/sys/dev/pci/nvme_pci.c Fri Dec 3 19:40:38 2021 @@ -1,4 +1,4 @@ -/* $NetBSD: nvme_pci.c,v 1.26.4.1 2021/06/21 17:25:48 martin Exp $ */ +/* $NetBSD: nvme_pci.c,v 1.26.4.2 2021/12/03 19:40:38 martin Exp $ */ /* $OpenBSD: nvme_pci.c,v 1.3 2016/04/14 11:18:32 dlg Exp $ */ /* @@ -43,7 +43,7 @@ */ #include <sys/cdefs.h> -__KERNEL_RCSID(0, "$NetBSD: nvme_pci.c,v 1.26.4.1 2021/06/21 17:25:48 martin Exp $"); +__KERNEL_RCSID(0, "$NetBSD: nvme_pci.c,v 1.26.4.2 2021/12/03 19:40:38 martin Exp $"); #include <sys/param.h> #include <sys/systm.h> @@ -135,7 +135,7 @@ nvme_pci_match(device_t parent, cfdata_t if (PCI_CLASS(pa->pa_class) == PCI_CLASS_MASS_STORAGE && PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_NVM && - PCI_INTERFACE(pa->pa_class) == PCI_INTERFACE_NVM_NVME) + PCI_INTERFACE(pa->pa_class) == PCI_INTERFACE_NVM_NVME_IO) return 1; return 0; Index: src/sys/dev/pci/pci.c diff -u src/sys/dev/pci/pci.c:1.154.4.2 src/sys/dev/pci/pci.c:1.154.4.3 --- src/sys/dev/pci/pci.c:1.154.4.2 Wed Nov 6 09:52:20 2019 +++ src/sys/dev/pci/pci.c Fri Dec 3 19:40:38 2021 @@ -1,4 +1,4 @@ -/* $NetBSD: pci.c,v 1.154.4.2 2019/11/06 09:52:20 martin Exp $ */ +/* $NetBSD: pci.c,v 1.154.4.3 2021/12/03 19:40:38 martin Exp $ */ /* * Copyright (c) 1995, 1996, 1997, 1998 @@ -36,7 +36,7 @@ */ #include <sys/cdefs.h> -__KERNEL_RCSID(0, "$NetBSD: pci.c,v 1.154.4.2 2019/11/06 09:52:20 martin Exp $"); +__KERNEL_RCSID(0, "$NetBSD: pci.c,v 1.154.4.3 2021/12/03 19:40:38 martin Exp $"); #ifdef _KERNEL_OPT #include "opt_pci.h" @@ -708,7 +708,7 @@ pci_enumerate_bus(struct pci_softc *sc, if (pci_get_capability(ppbpc, ppbtag, PCI_CAP_PCIEXPRESS, &pciecap, &capreg) != 0) { switch (PCIE_XCAP_TYPE(capreg)) { - case PCIE_XCAP_TYPE_ROOT: + case PCIE_XCAP_TYPE_RP: case PCIE_XCAP_TYPE_DOWN: case PCIE_XCAP_TYPE_PCI2PCIE: downstream_port = true; @@ -934,7 +934,7 @@ pci_conf_capture(pci_chipset_tag_t pc, p /* For MSI */ if (pci_get_capability(pc, tag, PCI_CAP_MSI, &off, NULL) != 0) { bool bit64, pvmask; - + pcs->msi_ctl = pci_conf_read(pc, tag, off + PCI_MSI_CTL); bit64 = pcs->msi_ctl & PCI_MSI_CTL_64BIT_ADDR; Index: src/sys/dev/pci/pci_subr.c diff -u src/sys/dev/pci/pci_subr.c:1.215.2.4 src/sys/dev/pci/pci_subr.c:1.215.2.5 --- src/sys/dev/pci/pci_subr.c:1.215.2.4 Sun Jul 26 10:46:14 2020 +++ src/sys/dev/pci/pci_subr.c Fri Dec 3 19:40:38 2021 @@ -1,4 +1,4 @@ -/* $NetBSD: pci_subr.c,v 1.215.2.4 2020/07/26 10:46:14 martin Exp $ */ +/* $NetBSD: pci_subr.c,v 1.215.2.5 2021/12/03 19:40:38 martin Exp $ */ /* * Copyright (c) 1997 Zubin D. Dittia. All rights reserved. @@ -40,7 +40,7 @@ */ #include <sys/cdefs.h> -__KERNEL_RCSID(0, "$NetBSD: pci_subr.c,v 1.215.2.4 2020/07/26 10:46:14 martin Exp $"); +__KERNEL_RCSID(0, "$NetBSD: pci_subr.c,v 1.215.2.5 2021/12/03 19:40:38 martin Exp $"); #ifdef _KERNEL_OPT #include "opt_pci.h" @@ -129,7 +129,15 @@ static const struct pci_class pci_interf static const struct pci_class pci_interface_nvm[] = { { "vendor specific", PCI_INTERFACE_NVM_VND, NULL, }, { "NVMHCI 1.0", PCI_INTERFACE_NVM_NVMHCI10, NULL, }, - { "NVMe", PCI_INTERFACE_NVM_NVME, NULL, }, + { "NVMe I/O", PCI_INTERFACE_NVM_NVME_IO, NULL, }, + { "NVMe admin", PCI_INTERFACE_NVM_NVME_ADMIN, NULL, }, + { NULL, 0, NULL, }, +}; + +/* UFS programming interface */ +static const struct pci_class pci_interface_ufs[] = { + { "vendor specific", PCI_INTERFACE_UFS_VND, NULL, }, + { "UFSHCI", PCI_INTERFACE_UFS_UFSHCI, NULL, }, { NULL, 0, NULL, }, }; @@ -147,6 +155,8 @@ static const struct pci_class pci_subcla { "SAS", PCI_SUBCLASS_MASS_STORAGE_SAS, NULL, }, { "Flash", PCI_SUBCLASS_MASS_STORAGE_NVM, pci_interface_nvm, }, + { "UFS", PCI_SUBCLASS_MASS_STORAGE_UFS, + pci_interface_ufs, }, { "miscellaneous", PCI_SUBCLASS_MASS_STORAGE_MISC, NULL, }, { NULL, 0, NULL, }, }; @@ -163,6 +173,8 @@ static const struct pci_class pci_subcla { "ISDN", PCI_SUBCLASS_NETWORK_ISDN, NULL, }, { "WorldFip", PCI_SUBCLASS_NETWORK_WORLDFIP, NULL, }, { "PCMIG Multi Computing", PCI_SUBCLASS_NETWORK_PCIMGMULTICOMP, NULL, }, + { "InfiniBand", PCI_SUBCLASS_NETWORK_INFINIBAND, NULL, }, + { "Host fabric", PCI_SUBCLASS_NETWORK_HFC, NULL, }, { "miscellaneous", PCI_SUBCLASS_NETWORK_MISC, NULL, }, { NULL, 0, NULL, }, }; @@ -191,11 +203,20 @@ static const struct pci_class pci_subcla * Class 0x04. * Multimedia device. */ + +/* HD Audio programming interface */ +static const struct pci_class pci_interface_hda[] = { + { "HD Audio 1.0", PCI_INTERFACE_HDAUDIO, NULL, }, + { "HD Audio 1.0 + vendor ext", PCI_INTERFACE_HDAUDIO_VND, NULL, }, + { NULL, 0, NULL, }, +}; + static const struct pci_class pci_subclass_multimedia[] = { { "video", PCI_SUBCLASS_MULTIMEDIA_VIDEO, NULL, }, { "audio", PCI_SUBCLASS_MULTIMEDIA_AUDIO, NULL, }, { "telephony", PCI_SUBCLASS_MULTIMEDIA_TELEPHONY, NULL,}, - { "mixed mode", PCI_SUBCLASS_MULTIMEDIA_HDAUDIO, NULL, }, + { "mixed mode", PCI_SUBCLASS_MULTIMEDIA_HDAUDIO, + pci_interface_hda, }, { "miscellaneous", PCI_SUBCLASS_MULTIMEDIA_MISC, NULL, }, { NULL, 0, NULL, }, }; @@ -431,6 +452,7 @@ static const struct pci_class pci_interf { "OHCI", PCI_INTERFACE_USB_OHCI, NULL, }, { "EHCI", PCI_INTERFACE_USB_EHCI, NULL, }, { "xHCI", PCI_INTERFACE_USB_XHCI, NULL, }, + { "USB4 HCI", PCI_INTERFACE_USB_USB4HCI, NULL, }, { "other HC", PCI_INTERFACE_USB_OTHERHC, NULL, }, { "device", PCI_INTERFACE_USB_DEVICE, NULL, }, { NULL, 0, NULL, }, @@ -460,6 +482,7 @@ static const struct pci_class pci_subcla pci_interface_ipmi, }, { "SERCOS", PCI_SUBCLASS_SERIALBUS_SERCOS, NULL, }, { "CANbus", PCI_SUBCLASS_SERIALBUS_CANBUS, NULL, }, + { "MIPI I3C", PCI_SUBCLASS_SERIALBUS_MIPI_I3C, NULL, }, { "miscellaneous", PCI_SUBCLASS_SERIALBUS_MISC, NULL, }, { NULL, 0, NULL, }, }; @@ -476,6 +499,8 @@ static const struct pci_class pci_subcla { "broadband", PCI_SUBCLASS_WIRELESS_BROADBAND, NULL, }, { "802.11a (5 GHz)", PCI_SUBCLASS_WIRELESS_802_11A, NULL, }, { "802.11b (2.4 GHz)", PCI_SUBCLASS_WIRELESS_802_11B, NULL, }, + { "Cellular", PCI_SUBCLASS_WIRELESS_CELL, NULL, }, + { "Cellular + Ethernet", PCI_SUBCLASS_WIRELESS_CELL_E, NULL, }, { "miscellaneous", PCI_SUBCLASS_WIRELESS_MISC, NULL, }, { NULL, 0, NULL, }, }; @@ -843,7 +868,7 @@ pci_conf_print_common( if (pci_conf_find_cap(regs, PCI_CAP_PCIEXPRESS, &pcie_capoff)) { reg = regs[o2i(pcie_capoff + PCIE_XCAP)]; - if (PCIE_XCAP_TYPE(reg) == PCIE_XCAP_TYPE_ROOT_EVNTC) + if (PCIE_XCAP_TYPE(reg) == PCIE_XCAP_TYPE_RC_EVNTC) subclass = PCI_SUBCLASS_SYSTEM_RCEC; } } @@ -1697,7 +1722,9 @@ pci_print_pcie_compl_timeout(uint32_t va } } -static const char * const pcie_linkspeeds[] = {"2.5", "5.0", "8.0", "16.0"}; +static const char * const pcie_linkspeeds[] = { + "2.5", "5.0", "8.0", "16.0", "32.0" +}; /* * Print link speed. This function is used for the following register bits: @@ -1788,7 +1815,7 @@ pci_conf_print_pcie_cap(const pcireg_t * printf("Legacy PCI Express Endpoint device\n"); check_upstreamport = true; break; - case PCIE_XCAP_TYPE_ROOT: /* 0x4 */ + case PCIE_XCAP_TYPE_RP: /* 0x4 */ printf("Root Port of PCI Express Root Complex\n"); check_slot = true; break; @@ -1809,10 +1836,10 @@ pci_conf_print_pcie_cap(const pcireg_t * /* Upstream port is not PCIe */ check_slot = true; break; - case PCIE_XCAP_TYPE_ROOT_INTEP: /* 0x9 */ + case PCIE_XCAP_TYPE_RCIEP: /* 0x9 */ printf("Root Complex Integrated Endpoint\n"); break; - case PCIE_XCAP_TYPE_ROOT_EVNTC: /* 0xa */ + case PCIE_XCAP_TYPE_RC_EVNTC: /* 0xa */ printf("Root Complex Event Collector\n"); break; default: @@ -2575,9 +2602,7 @@ pci_conf_print_ea_cap(const pcireg_t *re printf(" range: 0x%016" PRIx64 "-0x%016" PRIx64 "\n", base, base + offset); - entoff += 4; - entoff += baseis64 ? 8 : 4; - entoff += offsetis64 ? 8 : 4; + entoff += 4 + (4 * entry_size); } } @@ -2692,7 +2717,7 @@ pci_conf_print_caplist( /* * The type was found. Search capability list again and - * print all capabilities that the capabiliy type is + * print all capabilities that the capability type is * the same. This is required because some capabilities * appear multiple times (e.g. HyperTransport capability). */ @@ -2859,8 +2884,8 @@ pci_conf_print_aer_cap(const pcireg_t *r extcapoff + PCI_AER_ROOTERR_CMD); switch (pcie_devtype) { - case PCIE_XCAP_TYPE_ROOT: /* Root Port of PCI Express Root Complex */ - case PCIE_XCAP_TYPE_ROOT_EVNTC: /* Root Complex Event Collector */ + case PCIE_XCAP_TYPE_RP: /* Root Port of PCI Express Root Complex */ + case PCIE_XCAP_TYPE_RC_EVNTC: /* Root Complex Event Collector */ reg = regs[o2i(extcapoff + PCI_AER_ROOTERR_CMD)]; printf(" Root Error Command register: 0x%08x\n", reg); pci_conf_print_aer_cap_rooterr_cmd(reg); @@ -3496,7 +3521,7 @@ pci_conf_print_multicast_cap(const pcire /* Endpoint Only */ n = __SHIFTOUT(reg, PCI_MCAST_CAP_WINSIZEREQ); if (n > 0) - printf(" Windw Size Requested: %d\n", 1 << (n - 1)); + printf(" Window Size Requested: %d\n", 1 << (n - 1)); onoff("ECRC Regeneration Supported", reg, PCI_MCAST_CAP_ECRCREGEN); @@ -3680,7 +3705,7 @@ pci_conf_print_dpa_cap(const pcireg_t *r (unsigned int)__SHIFTOUT(reg, PCI_DPA_CAP_XLCY1)); reg = regs[o2i(extcapoff + PCI_DPA_LATIND)]; - printf(" Latency Indicatior register: 0x%08x\n", reg); + printf(" Latency Indicator register: 0x%08x\n", reg); reg = regs[o2i(extcapoff + PCI_DPA_CS)]; printf(" Status register: 0x%04x\n", reg & 0xffff); @@ -3726,7 +3751,7 @@ pci_conf_print_tph_req_cap(const pcireg_ onoff("No ST Mode Supported", reg, PCI_TPH_REQ_CAP_NOST); onoff("Interrupt Vector Mode Supported", reg, PCI_TPH_REQ_CAP_INTVEC); onoff("Device Specific Mode Supported", reg, PCI_TPH_REQ_CAP_DEVSPEC); - onoff("Extend TPH Reqester Supported", reg, PCI_TPH_REQ_CAP_XTPHREQ); + onoff("Extend TPH Requester Supported", reg, PCI_TPH_REQ_CAP_XTPHREQ); sttbloc = __SHIFTOUT(reg, PCI_TPH_REQ_CAP_STTBLLOC); printf(" ST Table Location: %s\n", pci_conf_print_tph_req_cap_sttabloc(sttbloc)); @@ -4079,7 +4104,7 @@ pci_conf_print_l1pm_cap(const pcireg_t * if (pci_conf_find_cap(regs, PCI_CAP_PCIEXPRESS, &pcie_capoff)) { uint32_t t = regs[o2i(pcie_capoff)]; - if ((t == PCIE_XCAP_TYPE_ROOT) || (t == PCIE_XCAP_TYPE_DOWN)) + if ((t == PCIE_XCAP_TYPE_RP) || (t == PCIE_XCAP_TYPE_DOWN)) onoff("Link Activation Supported", reg, PCI_L1PM_CAP_LA); } @@ -4132,7 +4157,7 @@ pci_conf_print_ptm_cap(const pcireg_t *r pcireg_t reg; uint32_t val; - printf("\n Precision Time Management\n"); + printf("\n Precision Time Measurement\n"); reg = regs[o2i(extcapoff + PCI_PTM_CAP)]; printf(" PTM Capability register: 0x%08x\n", reg); @@ -4269,7 +4294,7 @@ static struct { pci_conf_print_dpc_cap }, { PCI_EXTCAP_L1PM, "L1 PM Substates", pci_conf_print_l1pm_cap }, - { PCI_EXTCAP_PTM, "Precision Time Management", + { PCI_EXTCAP_PTM, "Precision Time Measurement", pci_conf_print_ptm_cap }, { PCI_EXTCAP_MPCIE, "M-PCIe", NULL }, @@ -4281,9 +4306,9 @@ static struct { NULL }, { PCI_EXTCAP_VF_RESIZBAR, "VF Resizable BARs", NULL }, - { PCI_EXTCAP_DLF, "Data link Feature", pci_conf_print_dlf_cap }, + { PCI_EXTCAP_DLF, "Data link Feature", pci_conf_print_dlf_cap }, { PCI_EXTCAP_PYSLAY_16GT, "Physical Layer 16.0 GT/s", NULL }, - { 0x27, "unknown", NULL }, + { PCI_EXTCAP_LMR, "Lane Margining at the Receiver", NULL }, { PCI_EXTCAP_HIERARCHYID, "Hierarchy ID", NULL }, { PCI_EXTCAP_NPEM, "Native PCIe Enclosure Management", @@ -4366,7 +4391,7 @@ pci_conf_print_extcaplist( /* * The type was found. Search capability list again and - * print all capabilities that the capabiliy type is + * print all capabilities that the capability type is * the same. */ if (pci_conf_find_extcap(regs, i, &off) == 0) Index: src/sys/dev/pci/pcireg.h diff -u src/sys/dev/pci/pcireg.h:1.147.4.2 src/sys/dev/pci/pcireg.h:1.147.4.3 --- src/sys/dev/pci/pcireg.h:1.147.4.2 Thu Mar 19 19:05:34 2020 +++ src/sys/dev/pci/pcireg.h Fri Dec 3 19:40:38 2021 @@ -1,4 +1,4 @@ -/* $NetBSD: pcireg.h,v 1.147.4.2 2020/03/19 19:05:34 martin Exp $ */ +/* $NetBSD: pcireg.h,v 1.147.4.3 2021/12/03 19:40:38 martin Exp $ */ /* * Copyright (c) 1995, 1996, 1999, 2000 @@ -54,12 +54,12 @@ typedef u_int16_t pci_vendor_id_t; typedef u_int16_t pci_product_id_t; #define PCI_VENDOR_SHIFT 0 -#define PCI_VENDOR_MASK 0xffff +#define PCI_VENDOR_MASK 0xffffU #define PCI_VENDOR(id) \ (((id) >> PCI_VENDOR_SHIFT) & PCI_VENDOR_MASK) #define PCI_PRODUCT_SHIFT 16 -#define PCI_PRODUCT_MASK 0xffff +#define PCI_PRODUCT_MASK 0xffffU #define PCI_PRODUCT(id) \ (((id) >> PCI_PRODUCT_SHIFT) & PCI_PRODUCT_MASK) @@ -188,7 +188,11 @@ typedef u_int8_t pci_revision_t; #define PCI_SUBCLASS_MASS_STORAGE_NVM 0x08 #define PCI_INTERFACE_NVM_VND 0x00 #define PCI_INTERFACE_NVM_NVMHCI10 0x01 -#define PCI_INTERFACE_NVM_NVME 0x02 +#define PCI_INTERFACE_NVM_NVME_IO 0x02 +#define PCI_INTERFACE_NVM_NVME_ADMIN 0x03 +#define PCI_SUBCLASS_MASS_STORAGE_UFS 0x09 +#define PCI_INTERFACE_UFS_VND 0x00 +#define PCI_INTERFACE_UFS_UFSHCI 0x01 #define PCI_SUBCLASS_MASS_STORAGE_MISC 0x80 /* 0x02 network subclasses */ @@ -200,6 +204,7 @@ typedef u_int8_t pci_revision_t; #define PCI_SUBCLASS_NETWORK_WORLDFIP 0x05 #define PCI_SUBCLASS_NETWORK_PCIMGMULTICOMP 0x06 #define PCI_SUBCLASS_NETWORK_INFINIBAND 0x07 +#define PCI_SUBCLASS_NETWORK_HFC 0x08 #define PCI_SUBCLASS_NETWORK_MISC 0x80 /* 0x03 display subclasses */ @@ -215,6 +220,8 @@ typedef u_int8_t pci_revision_t; #define PCI_SUBCLASS_MULTIMEDIA_AUDIO 0x01 #define PCI_SUBCLASS_MULTIMEDIA_TELEPHONY 0x02 #define PCI_SUBCLASS_MULTIMEDIA_HDAUDIO 0x03 +#define PCI_INTERFACE_HDAUDIO 0x00 +#define PCI_INTERFACE_HDAUDIO_VND 0x80 #define PCI_SUBCLASS_MULTIMEDIA_MISC 0x80 /* 0x05 memory subclasses */ @@ -330,6 +337,7 @@ typedef u_int8_t pci_revision_t; #define PCI_INTERFACE_USB_OHCI 0x10 #define PCI_INTERFACE_USB_EHCI 0x20 #define PCI_INTERFACE_USB_XHCI 0x30 +#define PCI_INTERFACE_USB_USB4HCI 0x40 #define PCI_INTERFACE_USB_OTHERHC 0x80 #define PCI_INTERFACE_USB_DEVICE 0xfe #define PCI_SUBCLASS_SERIALBUS_FIBER 0x04 /* XXX _FIBRECHANNEL */ @@ -341,6 +349,7 @@ typedef u_int8_t pci_revision_t; #define PCI_INTERFACE_IPMI_BLOCKXFER 0x02 #define PCI_SUBCLASS_SERIALBUS_SERCOS 0x08 #define PCI_SUBCLASS_SERIALBUS_CANBUS 0x09 +#define PCI_SUBCLASS_SERIALBUS_MIPI_I3C 0x0a #define PCI_SUBCLASS_SERIALBUS_MISC 0x80 /* 0x0d wireless subclasses */ @@ -353,6 +362,8 @@ typedef u_int8_t pci_revision_t; #define PCI_SUBCLASS_WIRELESS_BROADBAND 0x12 #define PCI_SUBCLASS_WIRELESS_802_11A 0x20 #define PCI_SUBCLASS_WIRELESS_802_11B 0x21 +#define PCI_SUBCLASS_WIRELESS_CELL 0x40 +#define PCI_SUBCLASS_WIRELESS_CELL_E 0x41 #define PCI_SUBCLASS_WIRELESS_MISC 0x80 /* 0x0e I2O (Intelligent I/O) subclasses */ @@ -492,8 +503,8 @@ typedef u_int8_t pci_revision_t; #define PCI_MAPREG_ROM_VSTAT_INPROG 0x1 /* Validation in Progress */ #define PCI_MAPREG_ROM_VSTAT_VPASS 0x2 /* Valid contnt, trust test nperf*/ #define PCI_MAPREG_ROM_VSTAT_VPASSTRUST 0x3 /* Valid and trusted contents */ -#define PCI_MAPREG_ROM_VSTAT_VFAIL 0x4 /* Invaild contents */ -#define PCI_MAPREG_ROM_VSTAT_VFAILUNTRUST 0x5 /* Vaild but untrusted contents*/ +#define PCI_MAPREG_ROM_VSTAT_VFAIL 0x4 /* Invalid contents */ +#define PCI_MAPREG_ROM_VSTAT_VFAILUNTRUST 0x5 /* Valid but untrusted contents */ #define PCI_MAPREG_ROM_VSTAT_WPASS 0x6 /* VPASS + warning */ #define PCI_MAPREG_ROM_VSTAT_WPASSTRUST 0x7 /* VPASSTRUST + warning */ #define PCI_MAPREG_ROM_VALID_DETAIL __BITS(7, 4) /* Validation Details */ @@ -552,7 +563,7 @@ typedef u_int8_t pci_revision_t; #define PCI_CAP_SUBVENDOR 0x0d #define PCI_CAP_AGP8 0x0e #define PCI_CAP_SECURE 0x0f -#define PCI_CAP_PCIEXPRESS 0x10 +#define PCI_CAP_PCIEXPRESS 0x10 #define PCI_CAP_MSIX 0x11 #define PCI_CAP_SATA 0x12 #define PCI_CAP_PCIAF 0x13 @@ -917,7 +928,7 @@ typedef u_int8_t pci_revision_t; /* For IOMMU only */ #define PCI_SECURE_CAP_IOTLBSUP __BIT(24) /* IOTLB */ #define PCI_SECURE_CAP_HTTUNNEL __BIT(25) /* HT tunnel translation */ -#define PCI_SECURE_CAP_NPCACHE __BIT(26) /* Not present table entries cahced*/ +#define PCI_SECURE_CAP_NPCACHE __BIT(26) /* Not present table entries cached */ #define PCI_SECURE_CAP_EFRSUP __BIT(27) /* IOMMU Ext-Feature Reg */ #define PCI_SECURE_CAP_EXT __BIT(28) /* IOMMU Misc Info Reg 1 */ #define PCI_SECURE_IOMMU_BAL 0x04 /* Base Address Low */ @@ -933,14 +944,14 @@ typedef u_int8_t pci_revision_t; #define PCI_SECURE_IOMMU_RANGE_LASTDEV __BITS(31, 24) /* Last device */ #define PCI_SECURE_IOMMU_MISC0 0x10 /* IOMMU Miscellaneous Information 0 */ #define PCI_SECURE_IOMMU_MISC0_MSINUM __BITS(4, 0) /* MSI Message number */ -#define PCI_SECURE_IOMMU_MISC0_GVASIZE __BITS(7, 5) /* Guest Virtual Adr siz */ +#define PCI_SECURE_IOMMU_MISC0_GVASIZE __BITS(7, 5) /* Guest Virtual Adr size */ #define PCI_SECURE_IOMMU_MISC0_GVASIZE_48B 0x2 /* 48bits */ -#define PCI_SECURE_IOMMU_MISC0_PASIZE __BITS(14, 8) /* Physical Address siz */ +#define PCI_SECURE_IOMMU_MISC0_PASIZE __BITS(14, 8) /* Physical Address size */ #define PCI_SECURE_IOMMU_MISC0_VASIZE __BITS(21, 15)/* Virtual Address size */ #define PCI_SECURE_IOMMU_MISC0_ATSRESV __BIT(22) /* ATS resp addr range rsvd */ #define PCI_SECURE_IOMMU_MISC0_MISNPPR __BITS(31, 27)/* Periph Pg Rq MSI Msgn*/ #define PCI_SECURE_IOMMU_MISC1 0x14 /* IOMMU Miscellaneous Information 1 */ -#define PCI_SECURE_IOMMU_MISC1_MSINUM __BITS(4, 0) /* MSI Messsage number(GA)*/ +#define PCI_SECURE_IOMMU_MISC1_MSINUM __BITS(4, 0) /* MSI Message number(GA) */ /* * Capability ID: 0x10 @@ -957,13 +968,13 @@ typedef u_int8_t pci_revision_t; #define PCIE_XCAP_TYPE(x) __SHIFTOUT((x), PCIE_XCAP_TYPE_MASK) #define PCIE_XCAP_TYPE_PCIE_DEV 0x0 #define PCIE_XCAP_TYPE_PCI_DEV 0x1 -#define PCIE_XCAP_TYPE_ROOT 0x4 +#define PCIE_XCAP_TYPE_RP 0x4 #define PCIE_XCAP_TYPE_UP 0x5 #define PCIE_XCAP_TYPE_DOWN 0x6 #define PCIE_XCAP_TYPE_PCIE2PCI 0x7 #define PCIE_XCAP_TYPE_PCI2PCIE 0x8 -#define PCIE_XCAP_TYPE_ROOT_INTEP 0x9 -#define PCIE_XCAP_TYPE_ROOT_EVNTC 0xa +#define PCIE_XCAP_TYPE_RCIEP 0x9 +#define PCIE_XCAP_TYPE_RC_EVNTC 0xa #define PCIE_XCAP_SI __SHIFTIN(__BIT(8), PCIE_XCAP_MASK) /* Slot Implemented */ #define PCIE_XCAP_IRQ __SHIFTIN(__BITS(13, 9), PCIE_XCAP_MASK) #define PCIE_DCAP 0x04 /* Device Capabilities Register */ @@ -1002,6 +1013,12 @@ typedef u_int8_t pci_revision_t; #define PCIE_DCSR_EMGPWRREDD __BIT(6 + 16) /* Emg. Pwr. Reduct. Detected */ #define PCIE_LCAP 0x0c /* Link Capabilities Register */ #define PCIE_LCAP_MAX_SPEED __BITS(3, 0) /* Max Link Speed */ +#define PCIE_LCAP_MAX_SPEED_2 1 /* 2.5GT/s */ +#define PCIE_LCAP_MAX_SPEED_5 2 /* 5GT/s */ +#define PCIE_LCAP_MAX_SPEED_8 3 /* 8GT/s */ +#define PCIE_LCAP_MAX_SPEED_16 4 /* 16GT/s */ +#define PCIE_LCAP_MAX_SPEED_32 5 /* 32GT/s */ +#define PCIE_LCAP_MAX_SPEED_64 6 /* 64GT/s */ #define PCIE_LCAP_MAX_WIDTH __BITS(9, 4) /* Maximum Link Width */ #define PCIE_LCAP_ASPM __BITS(11, 10) /* Active State Link PM Supp. */ #define PCIE_LCAP_L0S_EXIT __BITS(14, 12) /* L0s Exit Latency */ @@ -1015,7 +1032,7 @@ typedef u_int8_t pci_revision_t; #define PCIE_LCSR 0x10 /* Link Control & Status Register */ #define PCIE_LCSR_ASPM_L0S __BIT(0) /* Active State PM Control L0s*/ #define PCIE_LCSR_ASPM_L1 __BIT(1) /* Active State PM Control L1 */ -#define PCIE_LCSR_RCB __BIT(3) /* Read Completion Boundry Ctl*/ +#define PCIE_LCSR_RCB __BIT(3) /* Read Completion Boundary Ctl*/ #define PCIE_LCSR_LINK_DIS __BIT(4) /* Link Disable */ #define PCIE_LCSR_RETRAIN __BIT(5) /* Retrain Link */ #define PCIE_LCSR_COMCLKCFG __BIT(6) /* Common Clock Configuration */ @@ -1029,7 +1046,7 @@ typedef u_int8_t pci_revision_t; #define PCIE_LCSR_NLW __BITS(25, 20) /* Negotiated Link Width */ #define PCIE_LCSR_LINKTRAIN_ERR __BIT(10 + 16) /* Link Training Error */ #define PCIE_LCSR_LINKTRAIN __BIT(11 + 16) /* Link Training */ -#define PCIE_LCSR_SLOTCLKCFG __BIT(12 + 16) /* Slot Clock Configuration */ +#define PCIE_LCSR_SLOTCLKCFG __BIT(12 + 16) /* Slot Clock Configuration */ #define PCIE_LCSR_DLACTIVE __BIT(13 + 16) /* Data Link Layer Link Active*/ #define PCIE_LCSR_LINK_BW_MGMT __BIT(14 + 16) /* Link BW Management Status */ #define PCIE_LCSR_LINK_AUTO_BW __BIT(15 + 16) /* Link Autonomous BW Status */ @@ -1121,6 +1138,12 @@ typedef u_int8_t pci_revision_t; #define PCIE_DCSR2_EETLP __BIT(15) /* End-End TLP Prefix Blcking */ #define PCIE_LCAP2 0x2c /* Link Capabilities 2 Register */ #define PCIE_LCAP2_SUP_LNKSV __BITS(7, 1) /* Supported Link Speeds Vect */ +#define PCIE_LCAP2_SUP_LNKS2 __BIT(1) /* Supported Speed 2.5GT/ */ +#define PCIE_LCAP2_SUP_LNKS5 __BIT(2) /* Supported Speed 5GT/ */ +#define PCIE_LCAP2_SUP_LNKS8 __BIT(3) /* Supported Speed 8GT/ */ +#define PCIE_LCAP2_SUP_LNKS16 __BIT(4) /* Supported Speed 16GT/ */ +#define PCIE_LCAP2_SUP_LNKS32 __BIT(5) /* Supported Speed 32GT/ */ +#define PCIE_LCAP2_SUP_LNKS64 __BIT(6) /* Supported Speed 64GT/ */ #define PCIE_LCAP2_CROSSLNK __BIT(8) /* Crosslink Supported */ #define PCIE_LCAP2_LOWSKPOS_GENSUPPSV __BITS(15, 9) /* Lower SKP OS Generation Supp. Spd. Vect */ @@ -1160,12 +1183,12 @@ typedef u_int8_t pci_revision_t; * Other than Root Complex Integrated Endpoint and Root Complex Event Collector * have link related registers. */ -#define PCIE_HAS_LINKREGS(type) (((type) != PCIE_XCAP_TYPE_ROOT_INTEP) && \ - ((type) != PCIE_XCAP_TYPE_ROOT_EVNTC)) +#define PCIE_HAS_LINKREGS(type) (((type) != PCIE_XCAP_TYPE_RCIEP) && \ + ((type) != PCIE_XCAP_TYPE_RC_EVNTC)) /* Only root port and root complex event collector have PCIE_RCR & PCIE_RSR */ -#define PCIE_HAS_ROOTREGS(type) (((type) == PCIE_XCAP_TYPE_ROOT) || \ - ((type) == PCIE_XCAP_TYPE_ROOT_EVNTC)) +#define PCIE_HAS_ROOTREGS(type) (((type) == PCIE_XCAP_TYPE_RP) || \ + ((type) == PCIE_XCAP_TYPE_RC_EVNTC)) /* @@ -1530,6 +1553,7 @@ struct pci_rom { #define PCI_EXTCAP_VF_RESIZBAR 0x0024 /* VF Resizable BAR */ #define PCI_EXTCAP_DLF 0x0025 /* Data link Feature */ #define PCI_EXTCAP_PYSLAY_16GT 0x0026 /* Physical Layer 16.0 GT/s */ +#define PCI_EXTCAP_LMR 0x0027 /* Lane Margining at the Receiver */ #define PCI_EXTCAP_HIERARCHYID 0x0028 /* Hierarchy ID */ #define PCI_EXTCAP_NPEM 0x0029 /* Native PCIe Enclosure Management */ @@ -1878,38 +1902,36 @@ struct pci_rom { /* Bit definitions for the first DW of each entry */ #define PCI_EA_ES __BITS(2, 0) /* Entry Size */ #define PCI_EA_BEI __BITS(7, 4) /* BAR Equivalent Indicator */ -#define PCI_EA_BEI_BAR0 0 /* BAR0 (10h) */ -#define PCI_EA_BEI_BAR1 1 /* BAR1 (14h) */ -#define PCI_EA_BEI_BAR2 2 /* BAR2 (18h) */ -#define PCI_EA_BEI_BAR3 3 /* BAR3 (1ch) */ -#define PCI_EA_BEI_BAR4 4 /* BAR4 (20h) */ -#define PCI_EA_BEI_BAR5 5 /* BAR5 (24h) */ -#define PCI_EA_BEI_BEHIND 6 /* Behind the function (for type1) */ -#define PCI_EA_BEI_NOTIND 7 /* Not Indicated */ -#define PCI_EA_BEI_EXPROM 8 /* Expansion ROM */ -#define PCI_EA_BEI_VFBAR0 9 /* VF BAR0 */ -#define PCI_EA_BEI_VFBAR1 10 /* VF BAR1 */ -#define PCI_EA_BEI_VFBAR2 11 /* VF BAR2 */ -#define PCI_EA_BEI_VFBAR3 12 /* VF BAR3 */ -#define PCI_EA_BEI_VFBAR4 13 /* VF BAR4 */ -#define PCI_EA_BEI_VFBAR5 14 /* VF BAR5 */ -#define PCI_EA_BEI_RESERVED 15 /* Reserved (treat as Not Indicated) */ - +#define PCI_EA_BEI_BAR0 0 /* BAR0 (10h) */ +#define PCI_EA_BEI_BAR1 1 /* BAR1 (14h) */ +#define PCI_EA_BEI_BAR2 2 /* BAR2 (18h) */ +#define PCI_EA_BEI_BAR3 3 /* BAR3 (1ch) */ +#define PCI_EA_BEI_BAR4 4 /* BAR4 (20h) */ +#define PCI_EA_BEI_BAR5 5 /* BAR5 (24h) */ +#define PCI_EA_BEI_BEHIND 6 /* Behind the function (for type1) */ +#define PCI_EA_BEI_NOTIND 7 /* Not Indicated */ +#define PCI_EA_BEI_EXPROM 8 /* Expansion ROM */ +#define PCI_EA_BEI_VFBAR0 9 /* VF BAR0 */ +#define PCI_EA_BEI_VFBAR1 10 /* VF BAR1 */ +#define PCI_EA_BEI_VFBAR2 11 /* VF BAR2 */ +#define PCI_EA_BEI_VFBAR3 12 /* VF BAR3 */ +#define PCI_EA_BEI_VFBAR4 13 /* VF BAR4 */ +#define PCI_EA_BEI_VFBAR5 14 /* VF BAR5 */ +#define PCI_EA_BEI_RESERVED 15 /* Reserved (treat as Not Indicated) */ #define PCI_EA_PP __BITS(15, 8) /* Primary Properties */ #define PCI_EA_SP __BITS(23, 16) /* Secondary Properties */ /* PP and SP's values */ -#define PCI_EA_PROP_MEM_NONPREF 0x00 /* Memory Space, Non-Prefetchable */ -#define PCI_EA_PROP_MEM_PREF 0x01 /* Memory Space, Prefetchable */ -#define PCI_EA_PROP_IO 0x02 /* I/O Space */ -#define PCI_EA_PROP_VF_MEM_NONPREF 0x03 /* Resorce for VF use. Mem. Non-Pref */ -#define PCI_EA_PROP_VF_MEM_PREF 0x04 /* Resorce for VF use. Mem. Prefetch */ -#define PCI_EA_PROP_BB_MEM_NONPREF 0x05 /* Behind Bridge: MEM. Non-Pref */ -#define PCI_EA_PROP_BB_MEM_PREF 0x06 /* Behind Bridge: MEM. Prefetch */ -#define PCI_EA_PROP_BB_IO 0x07 /* Behind Bridge: I/O Space */ -#define PCI_EA_PROP_MEM_UNAVAIL 0xfd /* Memory Space Unavailable */ -#define PCI_EA_PROP_IO_UNAVAIL 0xfe /* IO Space Unavailable */ -#define PCI_EA_PROP_UNAVAIL 0xff /* Entry Unavailable for use */ - +#define PCI_EA_PROP_MEM_NONPREF 0x00 /* Memory Space, Non-Prefetchable */ +#define PCI_EA_PROP_MEM_PREF 0x01 /* Memory Space, Prefetchable */ +#define PCI_EA_PROP_IO 0x02 /* I/O Space */ +#define PCI_EA_PROP_VF_MEM_NONPREF 0x03 /* Resorce for VF use. Mem. Non-Pref */ +#define PCI_EA_PROP_VF_MEM_PREF 0x04 /* Resorce for VF use. Mem. Prefetch */ +#define PCI_EA_PROP_BB_MEM_NONPREF 0x05 /* Behind Bridge: MEM. Non-Pref */ +#define PCI_EA_PROP_BB_MEM_PREF 0x06 /* Behind Bridge: MEM. Prefetch */ +#define PCI_EA_PROP_BB_IO 0x07 /* Behind Bridge: I/O Space */ +#define PCI_EA_PROP_MEM_UNAVAIL 0xfd /* Memory Space Unavailable */ +#define PCI_EA_PROP_IO_UNAVAIL 0xfe /* IO Space Unavailable */ +#define PCI_EA_PROP_UNAVAIL 0xff /* Entry Unavailable for use */ #define PCI_EA_W __BIT(30) /* Writable */ #define PCI_EA_E __BIT(31) /* Enable for this entry */ @@ -1957,11 +1979,11 @@ struct pci_rom { #define PCI_TPH_REQ_CAP_NOST __BIT(0) /* No ST Mode Supported */ #define PCI_TPH_REQ_CAP_INTVEC __BIT(1) /* Intr Vec Mode Supported */ #define PCI_TPH_REQ_CAP_DEVSPEC __BIT(2) /* Device Specific Mode Supported */ -#define PCI_TPH_REQ_CAP_XTPHREQ __BIT(8) /* Extend TPH Reqester Supported */ +#define PCI_TPH_REQ_CAP_XTPHREQ __BIT(8) /* Extend TPH Requester Supported */ #define PCI_TPH_REQ_CAP_STTBLLOC __BITS(10, 9) /* ST Table Location */ -#define PCI_TPH_REQ_STTBLLOC_NONE 0 /* not present */ -#define PCI_TPH_REQ_STTBLLOC_TPHREQ 1 /* in the TPHREQ cap */ -#define PCI_TPH_REQ_STTBLLOC_MSIX 2 /* in the MSI-X table */ +#define PCI_TPH_REQ_STTBLLOC_NONE 0 /* not present */ +#define PCI_TPH_REQ_STTBLLOC_TPHREQ 1 /* in the TPHREQ cap */ +#define PCI_TPH_REQ_STTBLLOC_MSIX 2 /* in the MSI-X table */ #define PCI_TPH_REQ_CAP_STTBLSIZ __BITS(26, 16) /* ST Table Size */ #define PCI_TPH_REQ_CTL 0x08 /* TPH Requester Control */ #define PCI_TPH_REQ_CTL_STSEL __BITS(2, 0) /* ST Mode Select */ @@ -2073,7 +2095,7 @@ struct pci_rom { #define PCI_DPC_RPPIO_MEMUR_CPL __BIT(16) /* MemReq received UR Complt. */ #define PCI_DPC_RPPIO_MEMCA_CPL __BIT(17) /* MemReq received CA Complt. */ #define PCI_DPC_RPPIO_MEM_CTO __BIT(18) /* MemReq Completion Timeout */ - + #define PCI_DPC_RPPIO_MASK 0x10 /* RP PIO Mask Register */ /* Bits are the same as RP PIO Status Register */ #define PCI_DPC_RPPIO_SEVE 0x14 /* RP PIO Severity Register */ Index: src/sys/dev/pci/ppb.c diff -u src/sys/dev/pci/ppb.c:1.69 src/sys/dev/pci/ppb.c:1.69.2.1 --- src/sys/dev/pci/ppb.c:1.69 Tue Jul 9 12:13:42 2019 +++ src/sys/dev/pci/ppb.c Fri Dec 3 19:40:38 2021 @@ -1,4 +1,4 @@ -/* $NetBSD: ppb.c,v 1.69 2019/07/09 12:13:42 msaitoh Exp $ */ +/* $NetBSD: ppb.c,v 1.69.2.1 2021/12/03 19:40:38 martin Exp $ */ /* * Copyright (c) 1996, 1998 Christopher G. Demetriou. All rights reserved. @@ -31,7 +31,7 @@ */ #include <sys/cdefs.h> -__KERNEL_RCSID(0, "$NetBSD: ppb.c,v 1.69 2019/07/09 12:13:42 msaitoh Exp $"); +__KERNEL_RCSID(0, "$NetBSD: ppb.c,v 1.69.2.1 2021/12/03 19:40:38 martin Exp $"); #ifdef _KERNEL_OPT #include "opt_ppb.h" @@ -150,7 +150,7 @@ ppb_print_pcie(device_t self) case PCIE_XCAP_TYPE_PCI_DEV: aprint_normal("Legacy PCI-E Endpoint device"); break; - case PCIE_XCAP_TYPE_ROOT: + case PCIE_XCAP_TYPE_RP: aprint_normal("Root Port of PCI-E Root Complex"); break; case PCIE_XCAP_TYPE_UP: @@ -171,7 +171,7 @@ ppb_print_pcie(device_t self) } switch (devtype) { - case PCIE_XCAP_TYPE_ROOT: + case PCIE_XCAP_TYPE_RP: case PCIE_XCAP_TYPE_DOWN: case PCIE_XCAP_TYPE_PCI2PCIE: reg = pci_conf_read(sc->sc_pc, sc->sc_tag, off + PCIE_LCAP);