Module Name: src
Committed By: martin
Date: Fri Dec 3 19:45:13 UTC 2021
Modified Files:
src/sys/dev/pci [netbsd-8]: nvme_pci.c pci_subr.c pcireg.h ppb.c
Log Message:
Pull up the following revisions, requested by msaitoh in ticket #1714:
sys/dev/pci/pcireg.h 1.148-1.154, 1.156-1.161
sys/dev/pci/pci_subr.c 1.217-1.222, 1.224, 1.227-1.232
via patch
sys/dev/pci/nvme_pci.c 1.31
sys/dev/pci/pci.c 1.158
sys/dev/pci/ppb.c 1.74
- Print Bridge Config Retry Enable bit and Retimer Presence Detect
Supported bit.
- Add PCIe 4.0 stuff a little:
- 10-bit Tag Requester/Completer.
- Add Data link Feature extended capability.
- Add Physical Layer 16.0 GT/s extended capability. Not decode yet.
- Change pci_conf_print() to allocate memory for the regs dynamically
instead of on-stack.
- Print some DPC register values not with %04x but with %08x because
those are 32bit.
- Fix a bug that the virtual channel extended configuration's
arbitration phase register can't be decoded correctly.
- When parsing Enhanced Allocation entries, use the correct calculation
for finding the next entry.
- Add 32.0GT/s to the list of pcie speeds (PCIe 5.x.).
- Add Some PCI config information:
- Lane Margining at the Receiver
- NVME admin interface
- UFSHCI
- InfiniBand
- Host fabric
- HDA 1.0 with vendor ext
- USB4 HCI
- MIPI I3C
- Cellular controller/modem (+ Ethernet)
- Change PCI_VENDOR_MASK and PCI_PRODUCT_MASK to unsigned values, to
prevent sign extension of product ID when shifted up into place in
PCI_ID_CODE(). Fixes PR kern/56176.
- Add LCAP & LCAP2 definitions.
- Use PCI-SIG official acronyms for some macros.
- Remove unused shift and mask definitions.
- Fix typo in some messages.
- Fix typo in comments.
- Whitespace fixes.
To generate a diff of this commit:
cvs rdiff -u -r1.19.2.2 -r1.19.2.3 src/sys/dev/pci/nvme_pci.c
cvs rdiff -u -r1.183.2.12 -r1.183.2.13 src/sys/dev/pci/pci_subr.c
cvs rdiff -u -r1.130.2.9 -r1.130.2.10 src/sys/dev/pci/pcireg.h
cvs rdiff -u -r1.63.2.2 -r1.63.2.3 src/sys/dev/pci/ppb.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/dev/pci/nvme_pci.c
diff -u src/sys/dev/pci/nvme_pci.c:1.19.2.2 src/sys/dev/pci/nvme_pci.c:1.19.2.3
--- src/sys/dev/pci/nvme_pci.c:1.19.2.2 Sun Jan 27 18:35:19 2019
+++ src/sys/dev/pci/nvme_pci.c Fri Dec 3 19:45:13 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: nvme_pci.c,v 1.19.2.2 2019/01/27 18:35:19 martin Exp $ */
+/* $NetBSD: nvme_pci.c,v 1.19.2.3 2021/12/03 19:45:13 martin Exp $ */
/* $OpenBSD: nvme_pci.c,v 1.3 2016/04/14 11:18:32 dlg Exp $ */
/*
@@ -43,7 +43,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: nvme_pci.c,v 1.19.2.2 2019/01/27 18:35:19 martin Exp $");
+__KERNEL_RCSID(0, "$NetBSD: nvme_pci.c,v 1.19.2.3 2021/12/03 19:45:13 martin Exp $");
#include <sys/param.h>
#include <sys/systm.h>
@@ -133,7 +133,7 @@ nvme_pci_match(device_t parent, cfdata_t
if (PCI_CLASS(pa->pa_class) == PCI_CLASS_MASS_STORAGE &&
PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_NVM &&
- PCI_INTERFACE(pa->pa_class) == PCI_INTERFACE_NVM_NVME)
+ PCI_INTERFACE(pa->pa_class) == PCI_INTERFACE_NVM_NVME_IO)
return 1;
return 0;
Index: src/sys/dev/pci/pci_subr.c
diff -u src/sys/dev/pci/pci_subr.c:1.183.2.12 src/sys/dev/pci/pci_subr.c:1.183.2.13
--- src/sys/dev/pci/pci_subr.c:1.183.2.12 Thu Sep 26 18:14:54 2019
+++ src/sys/dev/pci/pci_subr.c Fri Dec 3 19:45:13 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: pci_subr.c,v 1.183.2.12 2019/09/26 18:14:54 martin Exp $ */
+/* $NetBSD: pci_subr.c,v 1.183.2.13 2021/12/03 19:45:13 martin Exp $ */
/*
* Copyright (c) 1997 Zubin D. Dittia. All rights reserved.
@@ -40,7 +40,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: pci_subr.c,v 1.183.2.12 2019/09/26 18:14:54 martin Exp $");
+__KERNEL_RCSID(0, "$NetBSD: pci_subr.c,v 1.183.2.13 2021/12/03 19:45:13 martin Exp $");
#ifdef _KERNEL_OPT
#include "opt_pci.h"
@@ -52,6 +52,11 @@ __KERNEL_RCSID(0, "$NetBSD: pci_subr.c,v
#include <sys/systm.h>
#include <sys/intr.h>
#include <sys/module.h>
+#include <sys/kmem.h>
+
+#define MALLOC(sz) kmem_alloc(sz, KM_SLEEP)
+#define FREE(p, sz) kmem_free(p, sz)
+
#else
#include <pci.h>
#include <stdarg.h>
@@ -59,6 +64,10 @@ __KERNEL_RCSID(0, "$NetBSD: pci_subr.c,v
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
+
+#define MALLOC(sz) malloc(sz)
+#define FREE(p, sz) free(p)
+
#endif
#include <dev/pci/pcireg.h>
@@ -120,7 +129,15 @@ static const struct pci_class pci_interf
static const struct pci_class pci_interface_nvm[] = {
{ "vendor specific", PCI_INTERFACE_NVM_VND, NULL, },
{ "NVMHCI 1.0", PCI_INTERFACE_NVM_NVMHCI10, NULL, },
- { "NVMe", PCI_INTERFACE_NVM_NVME, NULL, },
+ { "NVMe I/O", PCI_INTERFACE_NVM_NVME_IO, NULL, },
+ { "NVMe admin", PCI_INTERFACE_NVM_NVME_ADMIN, NULL, },
+ { NULL, 0, NULL, },
+};
+
+/* UFS programming interface */
+static const struct pci_class pci_interface_ufs[] = {
+ { "vendor specific", PCI_INTERFACE_UFS_VND, NULL, },
+ { "UFSHCI", PCI_INTERFACE_UFS_UFSHCI, NULL, },
{ NULL, 0, NULL, },
};
@@ -138,6 +155,8 @@ static const struct pci_class pci_subcla
{ "SAS", PCI_SUBCLASS_MASS_STORAGE_SAS, NULL, },
{ "Flash", PCI_SUBCLASS_MASS_STORAGE_NVM,
pci_interface_nvm, },
+ { "UFS", PCI_SUBCLASS_MASS_STORAGE_UFS,
+ pci_interface_ufs, },
{ "miscellaneous", PCI_SUBCLASS_MASS_STORAGE_MISC, NULL, },
{ NULL, 0, NULL, },
};
@@ -154,6 +173,8 @@ static const struct pci_class pci_subcla
{ "ISDN", PCI_SUBCLASS_NETWORK_ISDN, NULL, },
{ "WorldFip", PCI_SUBCLASS_NETWORK_WORLDFIP, NULL, },
{ "PCMIG Multi Computing", PCI_SUBCLASS_NETWORK_PCIMGMULTICOMP, NULL, },
+ { "InfiniBand", PCI_SUBCLASS_NETWORK_INFINIBAND, NULL, },
+ { "Host fabric", PCI_SUBCLASS_NETWORK_HFC, NULL, },
{ "miscellaneous", PCI_SUBCLASS_NETWORK_MISC, NULL, },
{ NULL, 0, NULL, },
};
@@ -182,11 +203,20 @@ static const struct pci_class pci_subcla
* Class 0x04.
* Multimedia device.
*/
+
+/* HD Audio programming interface */
+static const struct pci_class pci_interface_hda[] = {
+ { "HD Audio 1.0", PCI_INTERFACE_HDAUDIO, NULL, },
+ { "HD Audio 1.0 + vendor ext", PCI_INTERFACE_HDAUDIO_VND, NULL, },
+ { NULL, 0, NULL, },
+};
+
static const struct pci_class pci_subclass_multimedia[] = {
{ "video", PCI_SUBCLASS_MULTIMEDIA_VIDEO, NULL, },
{ "audio", PCI_SUBCLASS_MULTIMEDIA_AUDIO, NULL, },
{ "telephony", PCI_SUBCLASS_MULTIMEDIA_TELEPHONY, NULL,},
- { "mixed mode", PCI_SUBCLASS_MULTIMEDIA_HDAUDIO, NULL, },
+ { "mixed mode", PCI_SUBCLASS_MULTIMEDIA_HDAUDIO,
+ pci_interface_hda, },
{ "miscellaneous", PCI_SUBCLASS_MULTIMEDIA_MISC, NULL, },
{ NULL, 0, NULL, },
};
@@ -422,6 +452,7 @@ static const struct pci_class pci_interf
{ "OHCI", PCI_INTERFACE_USB_OHCI, NULL, },
{ "EHCI", PCI_INTERFACE_USB_EHCI, NULL, },
{ "xHCI", PCI_INTERFACE_USB_XHCI, NULL, },
+ { "USB4 HCI", PCI_INTERFACE_USB_USB4HCI, NULL, },
{ "other HC", PCI_INTERFACE_USB_OTHERHC, NULL, },
{ "device", PCI_INTERFACE_USB_DEVICE, NULL, },
{ NULL, 0, NULL, },
@@ -451,6 +482,7 @@ static const struct pci_class pci_subcla
pci_interface_ipmi, },
{ "SERCOS", PCI_SUBCLASS_SERIALBUS_SERCOS, NULL, },
{ "CANbus", PCI_SUBCLASS_SERIALBUS_CANBUS, NULL, },
+ { "MIPI I3C", PCI_SUBCLASS_SERIALBUS_MIPI_I3C, NULL, },
{ "miscellaneous", PCI_SUBCLASS_SERIALBUS_MISC, NULL, },
{ NULL, 0, NULL, },
};
@@ -467,6 +499,8 @@ static const struct pci_class pci_subcla
{ "broadband", PCI_SUBCLASS_WIRELESS_BROADBAND, NULL, },
{ "802.11a (5 GHz)", PCI_SUBCLASS_WIRELESS_802_11A, NULL, },
{ "802.11b (2.4 GHz)", PCI_SUBCLASS_WIRELESS_802_11B, NULL, },
+ { "Cellular", PCI_SUBCLASS_WIRELESS_CELL, NULL, },
+ { "Cellular + Ethernet", PCI_SUBCLASS_WIRELESS_CELL_E, NULL, },
{ "miscellaneous", PCI_SUBCLASS_WIRELESS_MISC, NULL, },
{ NULL, 0, NULL, },
};
@@ -834,7 +868,7 @@ pci_conf_print_common(
if (pci_conf_find_cap(regs, PCI_CAP_PCIEXPRESS, &pcie_capoff)) {
reg = regs[o2i(pcie_capoff + PCIE_XCAP)];
- if (PCIE_XCAP_TYPE(reg) == PCIE_XCAP_TYPE_ROOT_EVNTC)
+ if (PCIE_XCAP_TYPE(reg) == PCIE_XCAP_TYPE_RC_EVNTC)
subclass = PCI_SUBCLASS_SYSTEM_RCEC;
}
}
@@ -1688,7 +1722,9 @@ pci_print_pcie_compl_timeout(uint32_t va
}
}
-static const char * const pcie_linkspeeds[] = {"2.5", "5.0", "8.0", "16.0"};
+static const char * const pcie_linkspeeds[] = {
+ "2.5", "5.0", "8.0", "16.0", "32.0"
+};
/*
* Print link speed. This function is used for the following register bits:
@@ -1779,7 +1815,7 @@ pci_conf_print_pcie_cap(const pcireg_t *
printf("Legacy PCI Express Endpoint device\n");
check_upstreamport = true;
break;
- case PCIE_XCAP_TYPE_ROOT: /* 0x4 */
+ case PCIE_XCAP_TYPE_RP: /* 0x4 */
printf("Root Port of PCI Express Root Complex\n");
check_slot = true;
break;
@@ -1800,10 +1836,10 @@ pci_conf_print_pcie_cap(const pcireg_t *
/* Upstream port is not PCIe */
check_slot = true;
break;
- case PCIE_XCAP_TYPE_ROOT_INTEP: /* 0x9 */
+ case PCIE_XCAP_TYPE_RCIEP: /* 0x9 */
printf("Root Complex Integrated Endpoint\n");
break;
- case PCIE_XCAP_TYPE_ROOT_EVNTC: /* 0xa */
+ case PCIE_XCAP_TYPE_RC_EVNTC: /* 0xa */
printf("Root Complex Event Collector\n");
break;
default:
@@ -1869,6 +1905,9 @@ pci_conf_print_pcie_cap(const pcireg_t *
onoff("Enable No Snoop", reg, PCIE_DCSR_ENA_NO_SNOOP);
printf(" Max Read Request Size: %d byte\n",
128 << __SHIFTOUT(reg, PCIE_DCSR_MAX_READ_REQ));
+ if (pcie_devtype == PCIE_XCAP_TYPE_PCIE2PCI)
+ onoff("Bridge Config Retry Enable", reg,
+ PCIE_DCSR_BRDG_CFG_RETRY);
/* Device Status Register */
reg = regs[o2i(capoff + PCIE_DCSR)];
@@ -2162,6 +2201,8 @@ pci_conf_print_pcie_cap(const pcireg_t *
printf("Reserved\n");
break;
}
+ onoff("10-bit Tag Completer Supported", reg, PCIE_DCAP2_TBT_COMP);
+ onoff("10-bit Tag Requester Supported", reg, PCIE_DCAP2_TBT_REQ);
printf(" OBFF Supported: ");
switch (__SHIFTOUT(reg, PCIE_DCAP2_OBFF)) {
case 0x0:
@@ -2214,6 +2255,7 @@ pci_conf_print_pcie_cap(const pcireg_t *
onoff("LTR Mechanism Enabled", reg, PCIE_DCSR2_LTR_MEC);
onoff("Emergency Power Reduction Request", reg,
PCIE_DCSR2_EMGPWRRED_REQ);
+ onoff("10-bit Tag Requester Enabled", reg, PCIE_DCSR2_TBT_REQ);
printf(" OBFF: ");
switch (__SHIFTOUT(reg, PCIE_DCSR2_OBFF_EN)) {
case 0x0:
@@ -2254,6 +2296,8 @@ pci_conf_print_pcie_cap(const pcireg_t *
pci_print_pcie_linkspeedvector(
__SHIFTOUT(reg, PCIE_LCAP2_LOWSKPOS_RECSUPPSV));
printf("\n");
+ onoff("Retimer Presence Detect Supported", reg,
+ PCIE_LCAP2_RETIMERPD);
onoff("DRS Supported", reg, PCIE_LCAP2_DRS);
drs_supported = (reg & PCIE_LCAP2_DRS) ? true : false;
}
@@ -2273,7 +2317,7 @@ pci_conf_print_pcie_cap(const pcireg_t *
__SHIFTOUT(reg, PCIE_LCSR2_SEL_DEEMP));
printf("\n");
printf(" Transmit Margin: %u\n",
- (unsigned int)(reg & PCIE_LCSR2_TX_MARGIN) >> 7);
+ (unsigned int)__SHIFTOUT(reg, PCIE_LCSR2_TX_MARGIN));
onoff("Enter Modified Compliance", reg, PCIE_LCSR2_EN_MCOMP);
onoff("Compliance SOS", reg, PCIE_LCSR2_COMP_SOS);
printf(" Compliance Present/De-emphasis: ");
@@ -2558,9 +2602,7 @@ pci_conf_print_ea_cap(const pcireg_t *re
printf(" range: 0x%016" PRIx64 "-0x%016" PRIx64
"\n", base, base + offset);
- entoff += 4;
- entoff += baseis64 ? 8 : 4;
- entoff += offsetis64 ? 8 : 4;
+ entoff += 4 + (4 * entry_size);
}
}
@@ -2675,7 +2717,7 @@ pci_conf_print_caplist(
/*
* The type was found. Search capability list again and
- * print all capabilities that the capabiliy type is
+ * print all capabilities that the capability type is
* the same. This is required because some capabilities
* appear multiple times (e.g. HyperTransport capability).
*/
@@ -2842,8 +2884,8 @@ pci_conf_print_aer_cap(const pcireg_t *r
extcapoff + PCI_AER_ROOTERR_CMD);
switch (pcie_devtype) {
- case PCIE_XCAP_TYPE_ROOT: /* Root Port of PCI Express Root Complex */
- case PCIE_XCAP_TYPE_ROOT_EVNTC: /* Root Complex Event Collector */
+ case PCIE_XCAP_TYPE_RP: /* Root Port of PCI Express Root Complex */
+ case PCIE_XCAP_TYPE_RC_EVNTC: /* Root Complex Event Collector */
reg = regs[o2i(extcapoff + PCI_AER_ROOTERR_CMD)];
printf(" Root Error Command register: 0x%08x\n", reg);
pci_conf_print_aer_cap_rooterr_cmd(reg);
@@ -2864,36 +2906,42 @@ pci_conf_print_aer_cap(const pcireg_t *r
}
}
+/*
+ * Helper function to print the arbitration phase register.
+ *
+ * phases: Number of phases in the arbitration tables.
+ * arbsize: Number of bits in each phase.
+ * indent: Add more two spaces if it's true.
+ */
static void
pci_conf_print_vc_cap_arbtab(const pcireg_t *regs, int off, const char *name,
- pcireg_t parbsel, int parbsize)
+ const int phases, int arbsize, bool indent)
{
pcireg_t reg;
- int num = 16 << parbsel;
- int num_per_reg = sizeof(pcireg_t) / parbsize;
+ int num_per_reg = 32 / arbsize;
int i, j;
- /* First, dump the table */
- for (i = 0; i < num; i += num_per_reg) {
- reg = regs[o2i(off + i / num_per_reg)];
- printf(" %s Arbitration Table: 0x%08x\n", name, reg);
- }
- /* And then, decode each entry */
- for (i = 0; i < num; i += num_per_reg) {
- reg = regs[o2i(off + i / num_per_reg)];
- for (j = 0; j < num_per_reg; j++)
- printf(" Phase[%d]: %d\n", j, reg);
+ printf("%s %s Arbitration Table:\n", indent ? " " : "", name);
+ for (i = 0; i < phases; i += num_per_reg) {
+ reg = regs[o2i(off + (sizeof(uint32_t) * (i / num_per_reg)))];
+ for (j = 0; j < num_per_reg; j++) {
+ printf("%s Phase[%d]: 0x%x\n", indent ? " " : "",
+ i + j,
+ (uint32_t)(reg & __BITS(arbsize - 1, 0)));
+ reg >>= arbsize;
+ }
}
}
+/* For VC, bit 4-7 are reserved. For Port, bit 6-7 are reserved */
+static const int arb_phases[8] = {0, 32, 64, 128, 128, 256, 0, 0 };
+
static void
pci_conf_print_vc_cap(const pcireg_t *regs, int extcapoff)
{
pcireg_t reg, n;
- int parbtab, parbsize;
- pcireg_t parbsel;
- int varbtab, varbsize;
- pcireg_t varbsel;
+ int arbtab, parbsize;
+ pcireg_t arbsel;
int i, count;
printf("\n Virtual Channel Register\n");
@@ -2919,19 +2967,23 @@ pci_conf_print_vc_cap(const pcireg_t *re
reg, PCI_VC_CAP2_ARB_CAP_WRR_64);
onoff("WRR arbitration with 128 phases",
reg, PCI_VC_CAP2_ARB_CAP_WRR_128);
- varbtab = __SHIFTOUT(reg, PCI_VC_CAP2_ARB_TABLE_OFFSET);
- printf(" VC Arbitration Table Offset: 0x%x\n", varbtab);
+ arbtab = __SHIFTOUT(reg, PCI_VC_CAP2_ARB_TABLE_OFFSET);
+ printf(" VC Arbitration Table Offset: 0x%x\n", arbtab);
reg = regs[o2i(extcapoff + PCI_VC_CONTROL)] & 0xffff;
printf(" Port VC Control register: 0x%04x\n", reg);
- varbsel = __SHIFTOUT(reg, PCI_VC_CONTROL_VC_ARB_SELECT);
- printf(" VC Arbitration Select: 0x%x\n", varbsel);
+ arbsel = __SHIFTOUT(reg, PCI_VC_CONTROL_VC_ARB_SELECT);
+ printf(" VC Arbitration Select: 0x%x\n", arbsel);
reg = regs[o2i(extcapoff + PCI_VC_STATUS)] >> 16;
printf(" Port VC Status register: 0x%04x\n", reg);
onoff("VC Arbitration Table Status",
reg, PCI_VC_STATUS_LOAD_VC_ARB_TABLE);
+ if ((arbtab != 0) && (arbsel != 0))
+ pci_conf_print_vc_cap_arbtab(regs, extcapoff + (arbtab * 16),
+ "VC", arb_phases[arbsel], 4, false);
+
for (i = 0; i < count + 1; i++) {
reg = regs[o2i(extcapoff + PCI_VC_RESOURCE_CAP(i))];
printf(" VC number %d\n", i);
@@ -2954,9 +3006,10 @@ pci_conf_print_vc_cap(const pcireg_t *re
reg, PCI_VC_RESOURCE_CAP_REJCT_SNOOP_TRANS);
n = __SHIFTOUT(reg, PCI_VC_RESOURCE_CAP_MAX_TIME_SLOTS) + 1;
printf(" Maximum Time Slots: %d\n", n);
- parbtab = reg >> PCI_VC_RESOURCE_CAP_PORT_ARB_TABLE_OFFSET_S;
+ arbtab = __SHIFTOUT(reg,
+ PCI_VC_RESOURCE_CAP_PORT_ARB_TABLE_OFFSET);
printf(" Port Arbitration Table offset: 0x%02x\n",
- parbtab);
+ arbtab);
reg = regs[o2i(extcapoff + PCI_VC_RESOURCE_CTL(i))];
printf(" VC Resource Control Register: 0x%08x\n", reg);
@@ -2967,8 +3020,8 @@ pci_conf_print_vc_cap(const pcireg_t *re
* the Port Arbitration logic and it's always 0 on read, so
* we don't print it.
*/
- parbsel = __SHIFTOUT(reg, PCI_VC_RESOURCE_CTL_PORT_ARB_SELECT);
- printf(" Port Arbitration Select: 0x%x\n", parbsel);
+ arbsel = __SHIFTOUT(reg, PCI_VC_RESOURCE_CTL_PORT_ARB_SELECT);
+ printf(" Port Arbitration Select: 0x%x\n", arbsel);
n = __SHIFTOUT(reg, PCI_VC_RESOURCE_CTL_VC_ID);
printf(" VC ID: %d\n", n);
onoff(" VC Enable", reg, PCI_VC_RESOURCE_CTL_VC_ENABLE);
@@ -2980,15 +3033,11 @@ pci_conf_print_vc_cap(const pcireg_t *re
onoff(" VC Negotiation Pending",
reg, PCI_VC_RESOURCE_STA_VC_NEG_PENDING);
- if ((parbtab != 0) && (parbsel != 0))
- pci_conf_print_vc_cap_arbtab(regs, extcapoff + parbtab,
- "Port", parbsel, parbsize);
+ if ((arbtab != 0) && (arbsel != 0))
+ pci_conf_print_vc_cap_arbtab(regs,
+ extcapoff + (arbtab * 16),
+ "Port", arb_phases[arbsel], parbsize, true);
}
-
- varbsize = 8;
- if ((varbtab != 0) && (varbsel != 0))
- pci_conf_print_vc_cap_arbtab(regs, extcapoff + varbtab,
- " VC", varbsel, varbsize);
}
/*
@@ -3472,7 +3521,7 @@ pci_conf_print_multicast_cap(const pcire
/* Endpoint Only */
n = __SHIFTOUT(reg, PCI_MCAST_CAP_WINSIZEREQ);
if (n > 0)
- printf(" Windw Size Requested: %d\n", 1 << (n - 1));
+ printf(" Window Size Requested: %d\n", 1 << (n - 1));
onoff("ECRC Regeneration Supported", reg, PCI_MCAST_CAP_ECRCREGEN);
@@ -3531,7 +3580,7 @@ pci_conf_print_page_req_cap(const pcireg
ctl = reg & 0xffff;
sta = reg >> 16;
printf(" Control Register: 0x%04x\n", ctl);
- onoff("Enalbe", reg, PCI_PAGE_REQ_CTL_E);
+ onoff("Enable", reg, PCI_PAGE_REQ_CTL_E);
onoff("Reset", reg, PCI_PAGE_REQ_CTL_R);
printf(" Status Register: 0x%04x\n", sta);
@@ -3656,7 +3705,7 @@ pci_conf_print_dpa_cap(const pcireg_t *r
(unsigned int)__SHIFTOUT(reg, PCI_DPA_CAP_XLCY1));
reg = regs[o2i(extcapoff + PCI_DPA_LATIND)];
- printf(" Latency Indicatior register: 0x%08x\n", reg);
+ printf(" Latency Indicator register: 0x%08x\n", reg);
reg = regs[o2i(extcapoff + PCI_DPA_CS)];
printf(" Status register: 0x%04x\n", reg & 0xffff);
@@ -3702,7 +3751,7 @@ pci_conf_print_tph_req_cap(const pcireg_
onoff("No ST Mode Supported", reg, PCI_TPH_REQ_CAP_NOST);
onoff("Interrupt Vector Mode Supported", reg, PCI_TPH_REQ_CAP_INTVEC);
onoff("Device Specific Mode Supported", reg, PCI_TPH_REQ_CAP_DEVSPEC);
- onoff("Extend TPH Reqester Supported", reg, PCI_TPH_REQ_CAP_XTPHREQ);
+ onoff("Extend TPH Requester Supported", reg, PCI_TPH_REQ_CAP_XTPHREQ);
sttbloc = __SHIFTOUT(reg, PCI_TPH_REQ_CAP_STTBLLOC);
printf(" ST Table Location: %s\n",
pci_conf_print_tph_req_cap_sttabloc(sttbloc));
@@ -3990,23 +4039,23 @@ pci_conf_print_dpc_cap(const pcireg_t *r
*/
reg = regs[o2i(extcapoff + PCI_DPC_RPPIO_STAT)];
- printf(" RP PIO Status Register: 0x%04x\n", reg);
+ printf(" RP PIO Status Register: 0x%08x\n", reg);
pci_conf_print_dpc_pio(reg);
reg = regs[o2i(extcapoff + PCI_DPC_RPPIO_MASK)];
- printf(" RP PIO Mask Register: 0x%04x\n", reg);
+ printf(" RP PIO Mask Register: 0x%08x\n", reg);
pci_conf_print_dpc_pio(reg);
reg = regs[o2i(extcapoff + PCI_DPC_RPPIO_SEVE)];
- printf(" RP PIO Severity Register: 0x%04x\n", reg);
+ printf(" RP PIO Severity Register: 0x%08x\n", reg);
pci_conf_print_dpc_pio(reg);
reg = regs[o2i(extcapoff + PCI_DPC_RPPIO_SYSERR)];
- printf(" RP PIO SysError Register: 0x%04x\n", reg);
+ printf(" RP PIO SysError Register: 0x%08x\n", reg);
pci_conf_print_dpc_pio(reg);
reg = regs[o2i(extcapoff + PCI_DPC_RPPIO_EXCPT)];
- printf(" RP PIO Exception Register: 0x%04x\n", reg);
+ printf(" RP PIO Exception Register: 0x%08x\n", reg);
pci_conf_print_dpc_pio(reg);
printf(" RP PIO Header Log Register: start from 0x%03x\n",
@@ -4055,7 +4104,7 @@ pci_conf_print_l1pm_cap(const pcireg_t *
if (pci_conf_find_cap(regs, PCI_CAP_PCIEXPRESS, &pcie_capoff)) {
uint32_t t = regs[o2i(pcie_capoff)];
- if ((t == PCIE_XCAP_TYPE_ROOT) || (t == PCIE_XCAP_TYPE_DOWN))
+ if ((t == PCIE_XCAP_TYPE_RP) || (t == PCIE_XCAP_TYPE_DOWN))
onoff("Link Activation Supported", reg,
PCI_L1PM_CAP_LA);
}
@@ -4108,7 +4157,7 @@ pci_conf_print_ptm_cap(const pcireg_t *r
pcireg_t reg;
uint32_t val;
- printf("\n Precision Time Management\n");
+ printf("\n Precision Time Measurement\n");
reg = regs[o2i(extcapoff + PCI_PTM_CAP)];
printf(" PTM Capability register: 0x%08x\n", reg);
@@ -4153,6 +4202,24 @@ pci_conf_print_ptm_cap(const pcireg_t *r
/* XXX pci_conf_print_rtr_cap */
/* XXX pci_conf_print_desigvndsp_cap */
/* XXX pci_conf_print_vf_resizbar_cap */
+
+static void
+pci_conf_print_dlf_cap(const pcireg_t *regs, int extcapoff)
+{
+ pcireg_t reg;
+
+ printf("\n Data link Feature Register\n");
+ reg = regs[o2i(extcapoff + PCI_DLF_CAP)];
+ printf(" Capability register: 0x%08x\n", reg);
+ onoff("Scaled Flow Control", reg, PCI_DLF_LFEAT_SCLFCTL);
+ onoff("DLF Exchange enable", reg, PCI_DLF_CAP_XCHG);
+
+ reg = regs[o2i(extcapoff + PCI_DLF_STAT)];
+ printf(" Status register: 0x%08x\n", reg);
+ onoff("Scaled Flow Control", reg, PCI_DLF_LFEAT_SCLFCTL);
+ onoff("Remote DLF supported Valid", reg, PCI_DLF_STAT_RMTVALID);
+}
+
/* XXX pci_conf_print_hierarchyid_cap */
/* XXX pci_conf_print_npem_cap */
@@ -4227,7 +4294,7 @@ static struct {
pci_conf_print_dpc_cap },
{ PCI_EXTCAP_L1PM, "L1 PM Substates",
pci_conf_print_l1pm_cap },
- { PCI_EXTCAP_PTM, "Precision Time Management",
+ { PCI_EXTCAP_PTM, "Precision Time Measurement",
pci_conf_print_ptm_cap },
{ PCI_EXTCAP_MPCIE, "M-PCIe",
NULL },
@@ -4239,9 +4306,9 @@ static struct {
NULL },
{ PCI_EXTCAP_VF_RESIZBAR, "VF Resizable BARs",
NULL },
- { 0x25, "unknown", NULL },
- { 0x26, "unknown", NULL },
- { 0x27, "unknown", NULL },
+ { PCI_EXTCAP_DLF, "Data link Feature", pci_conf_print_dlf_cap },
+ { PCI_EXTCAP_PYSLAY_16GT, "Physical Layer 16.0 GT/s", NULL },
+ { PCI_EXTCAP_LMR, "Lane Margining at the Receiver", NULL },
{ PCI_EXTCAP_HIERARCHYID, "Hierarchy ID",
NULL },
{ PCI_EXTCAP_NPEM, "Native PCIe Enclosure Management",
@@ -4324,7 +4391,7 @@ pci_conf_print_extcaplist(
/*
* The type was found. Search capability list again and
- * print all capabilities that the capabiliy type is
+ * print all capabilities that the capability type is
* the same.
*/
if (pci_conf_find_extcap(regs, i, &off) == 0)
@@ -4784,7 +4851,7 @@ pci_conf_print(
#endif
)
{
- pcireg_t regs[o2i(PCI_EXTCONF_SIZE)];
+ pcireg_t *regs;
int off, capoff, endoff, hdrtype;
const char *type_name;
#ifdef _KERNEL
@@ -4793,6 +4860,8 @@ pci_conf_print(
void (*type_printfn)(const pcireg_t *);
#endif
+ regs = MALLOC(PCI_EXTCONF_SIZE);
+
printf("PCI configuration registers:\n");
for (off = 0; off < PCI_EXTCONF_SIZE; off += 4) {
@@ -4889,7 +4958,7 @@ pci_conf_print(
if (regs[o2i(PCI_EXTCAPLIST_BASE)] == 0xffffffff ||
regs[o2i(PCI_EXTCAPLIST_BASE)] == 0)
- return;
+ goto out;
printf("\n");
#ifdef _KERNEL
@@ -4902,4 +4971,7 @@ pci_conf_print(
/* Extended Configuration Space, if present */
printf(" Extended Configuration Space:\n");
pci_conf_print_regs(regs, PCI_EXTCAPLIST_BASE, PCI_EXTCONF_SIZE);
+
+out:
+ FREE(regs, PCI_EXTCONF_SIZE);
}
Index: src/sys/dev/pci/pcireg.h
diff -u src/sys/dev/pci/pcireg.h:1.130.2.9 src/sys/dev/pci/pcireg.h:1.130.2.10
--- src/sys/dev/pci/pcireg.h:1.130.2.9 Thu Sep 26 18:14:54 2019
+++ src/sys/dev/pci/pcireg.h Fri Dec 3 19:45:13 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: pcireg.h,v 1.130.2.9 2019/09/26 18:14:54 martin Exp $ */
+/* $NetBSD: pcireg.h,v 1.130.2.10 2021/12/03 19:45:13 martin Exp $ */
/*
* Copyright (c) 1995, 1996, 1999, 2000
@@ -54,12 +54,12 @@ typedef u_int16_t pci_vendor_id_t;
typedef u_int16_t pci_product_id_t;
#define PCI_VENDOR_SHIFT 0
-#define PCI_VENDOR_MASK 0xffff
+#define PCI_VENDOR_MASK 0xffffU
#define PCI_VENDOR(id) \
(((id) >> PCI_VENDOR_SHIFT) & PCI_VENDOR_MASK)
#define PCI_PRODUCT_SHIFT 16
-#define PCI_PRODUCT_MASK 0xffff
+#define PCI_PRODUCT_MASK 0xffffU
#define PCI_PRODUCT(id) \
(((id) >> PCI_PRODUCT_SHIFT) & PCI_PRODUCT_MASK)
@@ -188,7 +188,11 @@ typedef u_int8_t pci_revision_t;
#define PCI_SUBCLASS_MASS_STORAGE_NVM 0x08
#define PCI_INTERFACE_NVM_VND 0x00
#define PCI_INTERFACE_NVM_NVMHCI10 0x01
-#define PCI_INTERFACE_NVM_NVME 0x02
+#define PCI_INTERFACE_NVM_NVME_IO 0x02
+#define PCI_INTERFACE_NVM_NVME_ADMIN 0x03
+#define PCI_SUBCLASS_MASS_STORAGE_UFS 0x09
+#define PCI_INTERFACE_UFS_VND 0x00
+#define PCI_INTERFACE_UFS_UFSHCI 0x01
#define PCI_SUBCLASS_MASS_STORAGE_MISC 0x80
/* 0x02 network subclasses */
@@ -200,6 +204,7 @@ typedef u_int8_t pci_revision_t;
#define PCI_SUBCLASS_NETWORK_WORLDFIP 0x05
#define PCI_SUBCLASS_NETWORK_PCIMGMULTICOMP 0x06
#define PCI_SUBCLASS_NETWORK_INFINIBAND 0x07
+#define PCI_SUBCLASS_NETWORK_HFC 0x08
#define PCI_SUBCLASS_NETWORK_MISC 0x80
/* 0x03 display subclasses */
@@ -215,6 +220,8 @@ typedef u_int8_t pci_revision_t;
#define PCI_SUBCLASS_MULTIMEDIA_AUDIO 0x01
#define PCI_SUBCLASS_MULTIMEDIA_TELEPHONY 0x02
#define PCI_SUBCLASS_MULTIMEDIA_HDAUDIO 0x03
+#define PCI_INTERFACE_HDAUDIO 0x00
+#define PCI_INTERFACE_HDAUDIO_VND 0x80
#define PCI_SUBCLASS_MULTIMEDIA_MISC 0x80
/* 0x05 memory subclasses */
@@ -330,6 +337,7 @@ typedef u_int8_t pci_revision_t;
#define PCI_INTERFACE_USB_OHCI 0x10
#define PCI_INTERFACE_USB_EHCI 0x20
#define PCI_INTERFACE_USB_XHCI 0x30
+#define PCI_INTERFACE_USB_USB4HCI 0x40
#define PCI_INTERFACE_USB_OTHERHC 0x80
#define PCI_INTERFACE_USB_DEVICE 0xfe
#define PCI_SUBCLASS_SERIALBUS_FIBER 0x04 /* XXX _FIBRECHANNEL */
@@ -341,6 +349,7 @@ typedef u_int8_t pci_revision_t;
#define PCI_INTERFACE_IPMI_BLOCKXFER 0x02
#define PCI_SUBCLASS_SERIALBUS_SERCOS 0x08
#define PCI_SUBCLASS_SERIALBUS_CANBUS 0x09
+#define PCI_SUBCLASS_SERIALBUS_MIPI_I3C 0x0a
#define PCI_SUBCLASS_SERIALBUS_MISC 0x80
/* 0x0d wireless subclasses */
@@ -353,6 +362,8 @@ typedef u_int8_t pci_revision_t;
#define PCI_SUBCLASS_WIRELESS_BROADBAND 0x12
#define PCI_SUBCLASS_WIRELESS_802_11A 0x20
#define PCI_SUBCLASS_WIRELESS_802_11B 0x21
+#define PCI_SUBCLASS_WIRELESS_CELL 0x40
+#define PCI_SUBCLASS_WIRELESS_CELL_E 0x41
#define PCI_SUBCLASS_WIRELESS_MISC 0x80
/* 0x0e I2O (Intelligent I/O) subclasses */
@@ -492,8 +503,8 @@ typedef u_int8_t pci_revision_t;
#define PCI_MAPREG_ROM_VSTAT_INPROG 0x1 /* Validation in Progress */
#define PCI_MAPREG_ROM_VSTAT_VPASS 0x2 /* Valid contnt, trust test nperf*/
#define PCI_MAPREG_ROM_VSTAT_VPASSTRUST 0x3 /* Valid and trusted contents */
-#define PCI_MAPREG_ROM_VSTAT_VFAIL 0x4 /* Invaild contents */
-#define PCI_MAPREG_ROM_VSTAT_VFAILUNTRUST 0x5 /* Vaild but untrusted contents*/
+#define PCI_MAPREG_ROM_VSTAT_VFAIL 0x4 /* Invalid contents */
+#define PCI_MAPREG_ROM_VSTAT_VFAILUNTRUST 0x5 /* Valid but untrusted contents */
#define PCI_MAPREG_ROM_VSTAT_WPASS 0x6 /* VPASS + warning */
#define PCI_MAPREG_ROM_VSTAT_WPASSTRUST 0x7 /* VPASSTRUST + warning */
#define PCI_MAPREG_ROM_VALID_DETAIL __BITS(7, 4) /* Validation Details */
@@ -552,7 +563,7 @@ typedef u_int8_t pci_revision_t;
#define PCI_CAP_SUBVENDOR 0x0d
#define PCI_CAP_AGP8 0x0e
#define PCI_CAP_SECURE 0x0f
-#define PCI_CAP_PCIEXPRESS 0x10
+#define PCI_CAP_PCIEXPRESS 0x10
#define PCI_CAP_MSIX 0x11
#define PCI_CAP_SATA 0x12
#define PCI_CAP_PCIAF 0x13
@@ -603,7 +614,7 @@ typedef u_int8_t pci_revision_t;
#define PCI_PMCSR_PME_EN 0x00000100
#define PCI_PMCSR_DATASEL_MASK 0x00001e00
#define PCI_PMCSR_DATASCL_MASK 0x00006000
-#define PCI_PMCSR_PME_STS 0x00008000
+#define PCI_PMCSR_PME_STS 0x00008000 /* PME Status (R/W1C) */
#define PCI_PMCSR_B2B3_SUPPORT 0x00400000
#define PCI_PMCSR_BPCC_EN 0x00800000
#define PCI_PMCSR_DATA 0xff000000
@@ -917,7 +928,7 @@ typedef u_int8_t pci_revision_t;
/* For IOMMU only */
#define PCI_SECURE_CAP_IOTLBSUP __BIT(24) /* IOTLB */
#define PCI_SECURE_CAP_HTTUNNEL __BIT(25) /* HT tunnel translation */
-#define PCI_SECURE_CAP_NPCACHE __BIT(26) /* Not present table entries cahced*/
+#define PCI_SECURE_CAP_NPCACHE __BIT(26) /* Not present table entries cached */
#define PCI_SECURE_CAP_EFRSUP __BIT(27) /* IOMMU Ext-Feature Reg */
#define PCI_SECURE_CAP_EXT __BIT(28) /* IOMMU Misc Info Reg 1 */
#define PCI_SECURE_IOMMU_BAL 0x04 /* Base Address Low */
@@ -933,14 +944,14 @@ typedef u_int8_t pci_revision_t;
#define PCI_SECURE_IOMMU_RANGE_LASTDEV __BITS(31, 24) /* Last device */
#define PCI_SECURE_IOMMU_MISC0 0x10 /* IOMMU Miscellaneous Information 0 */
#define PCI_SECURE_IOMMU_MISC0_MSINUM __BITS(4, 0) /* MSI Message number */
-#define PCI_SECURE_IOMMU_MISC0_GVASIZE __BITS(7, 5) /* Guest Virtual Adr siz */
+#define PCI_SECURE_IOMMU_MISC0_GVASIZE __BITS(7, 5) /* Guest Virtual Adr size */
#define PCI_SECURE_IOMMU_MISC0_GVASIZE_48B 0x2 /* 48bits */
-#define PCI_SECURE_IOMMU_MISC0_PASIZE __BITS(14, 8) /* Physical Address siz */
+#define PCI_SECURE_IOMMU_MISC0_PASIZE __BITS(14, 8) /* Physical Address size */
#define PCI_SECURE_IOMMU_MISC0_VASIZE __BITS(21, 15)/* Virtual Address size */
#define PCI_SECURE_IOMMU_MISC0_ATSRESV __BIT(22) /* ATS resp addr range rsvd */
#define PCI_SECURE_IOMMU_MISC0_MISNPPR __BITS(31, 27)/* Periph Pg Rq MSI Msgn*/
#define PCI_SECURE_IOMMU_MISC1 0x14 /* IOMMU Miscellaneous Information 1 */
-#define PCI_SECURE_IOMMU_MISC1_MSINUM __BITS(4, 0) /* MSI Messsage number(GA)*/
+#define PCI_SECURE_IOMMU_MISC1_MSINUM __BITS(4, 0) /* MSI Message number(GA) */
/*
* Capability ID: 0x10
@@ -957,13 +968,13 @@ typedef u_int8_t pci_revision_t;
#define PCIE_XCAP_TYPE(x) __SHIFTOUT((x), PCIE_XCAP_TYPE_MASK)
#define PCIE_XCAP_TYPE_PCIE_DEV 0x0
#define PCIE_XCAP_TYPE_PCI_DEV 0x1
-#define PCIE_XCAP_TYPE_ROOT 0x4
+#define PCIE_XCAP_TYPE_RP 0x4
#define PCIE_XCAP_TYPE_UP 0x5
#define PCIE_XCAP_TYPE_DOWN 0x6
#define PCIE_XCAP_TYPE_PCIE2PCI 0x7
#define PCIE_XCAP_TYPE_PCI2PCIE 0x8
-#define PCIE_XCAP_TYPE_ROOT_INTEP 0x9
-#define PCIE_XCAP_TYPE_ROOT_EVNTC 0xa
+#define PCIE_XCAP_TYPE_RCIEP 0x9
+#define PCIE_XCAP_TYPE_RC_EVNTC 0xa
#define PCIE_XCAP_SI __SHIFTIN(__BIT(8), PCIE_XCAP_MASK) /* Slot Implemented */
#define PCIE_XCAP_IRQ __SHIFTIN(__BITS(13, 9), PCIE_XCAP_MASK)
#define PCIE_DCAP 0x04 /* Device Capabilities Register */
@@ -1002,6 +1013,12 @@ typedef u_int8_t pci_revision_t;
#define PCIE_DCSR_EMGPWRREDD __BIT(6 + 16) /* Emg. Pwr. Reduct. Detected */
#define PCIE_LCAP 0x0c /* Link Capabilities Register */
#define PCIE_LCAP_MAX_SPEED __BITS(3, 0) /* Max Link Speed */
+#define PCIE_LCAP_MAX_SPEED_2 1 /* 2.5GT/s */
+#define PCIE_LCAP_MAX_SPEED_5 2 /* 5GT/s */
+#define PCIE_LCAP_MAX_SPEED_8 3 /* 8GT/s */
+#define PCIE_LCAP_MAX_SPEED_16 4 /* 16GT/s */
+#define PCIE_LCAP_MAX_SPEED_32 5 /* 32GT/s */
+#define PCIE_LCAP_MAX_SPEED_64 6 /* 64GT/s */
#define PCIE_LCAP_MAX_WIDTH __BITS(9, 4) /* Maximum Link Width */
#define PCIE_LCAP_ASPM __BITS(11, 10) /* Active State Link PM Supp. */
#define PCIE_LCAP_L0S_EXIT __BITS(14, 12) /* L0s Exit Latency */
@@ -1015,7 +1032,7 @@ typedef u_int8_t pci_revision_t;
#define PCIE_LCSR 0x10 /* Link Control & Status Register */
#define PCIE_LCSR_ASPM_L0S __BIT(0) /* Active State PM Control L0s*/
#define PCIE_LCSR_ASPM_L1 __BIT(1) /* Active State PM Control L1 */
-#define PCIE_LCSR_RCB __BIT(3) /* Read Completion Boundry Ctl*/
+#define PCIE_LCSR_RCB __BIT(3) /* Read Completion Boundary Ctl*/
#define PCIE_LCSR_LINK_DIS __BIT(4) /* Link Disable */
#define PCIE_LCSR_RETRAIN __BIT(5) /* Retrain Link */
#define PCIE_LCSR_COMCLKCFG __BIT(6) /* Common Clock Configuration */
@@ -1029,7 +1046,7 @@ typedef u_int8_t pci_revision_t;
#define PCIE_LCSR_NLW __BITS(25, 20) /* Negotiated Link Width */
#define PCIE_LCSR_LINKTRAIN_ERR __BIT(10 + 16) /* Link Training Error */
#define PCIE_LCSR_LINKTRAIN __BIT(11 + 16) /* Link Training */
-#define PCIE_LCSR_SLOTCLKCFG __BIT(12 + 16) /* Slot Clock Configuration */
+#define PCIE_LCSR_SLOTCLKCFG __BIT(12 + 16) /* Slot Clock Configuration */
#define PCIE_LCSR_DLACTIVE __BIT(13 + 16) /* Data Link Layer Link Active*/
#define PCIE_LCSR_LINK_BW_MGMT __BIT(14 + 16) /* Link BW Management Status */
#define PCIE_LCSR_LINK_AUTO_BW __BIT(15 + 16) /* Link Autonomous BW Status */
@@ -1097,6 +1114,8 @@ typedef u_int8_t pci_revision_t;
#define PCIE_DCAP2_LTR_MEC __BIT(11) /* LTR Mechanism Supported */
#define PCIE_DCAP2_TPH_COMP __BITS(13, 12) /* TPH Completer Supported */
#define PCIE_DCAP2_LNSYSCLS __BITS(15, 14) /* LN System CLS */
+#define PCIE_DCAP2_TBT_COMP __BIT(16) /* 10-bit Tag Completer Supp. */
+#define PCIE_DCAP2_TBT_REQ __BIT(17) /* 10-bit Tag Requester Supp. */
#define PCIE_DCAP2_OBFF __BITS(19, 18) /* Optimized Buffer Flush/Fill*/
#define PCIE_DCAP2_EXTFMT_FLD __BIT(20) /* Extended Fmt Field Support */
#define PCIE_DCAP2_EETLP_PREF __BIT(21) /* End-End TLP Prefix Support */
@@ -1114,10 +1133,17 @@ typedef u_int8_t pci_revision_t;
#define PCIE_DCSR2_IDO_COMP __BIT(9) /* IDO Completion Enable */
#define PCIE_DCSR2_LTR_MEC __BIT(10) /* LTR Mechanism Enable */
#define PCIE_DCSR2_EMGPWRRED_REQ __BIT(11) /* Emergency Power Reduc. Req */
+#define PCIE_DCSR2_TBT_REQ __BIT(12) /* 10-bit Tag Requester Ena. */
#define PCIE_DCSR2_OBFF_EN __BITS(14, 13) /* OBFF Enable */
#define PCIE_DCSR2_EETLP __BIT(15) /* End-End TLP Prefix Blcking */
#define PCIE_LCAP2 0x2c /* Link Capabilities 2 Register */
#define PCIE_LCAP2_SUP_LNKSV __BITS(7, 1) /* Supported Link Speeds Vect */
+#define PCIE_LCAP2_SUP_LNKS2 __BIT(1) /* Supported Speed 2.5GT/ */
+#define PCIE_LCAP2_SUP_LNKS5 __BIT(2) /* Supported Speed 5GT/ */
+#define PCIE_LCAP2_SUP_LNKS8 __BIT(3) /* Supported Speed 8GT/ */
+#define PCIE_LCAP2_SUP_LNKS16 __BIT(4) /* Supported Speed 16GT/ */
+#define PCIE_LCAP2_SUP_LNKS32 __BIT(5) /* Supported Speed 32GT/ */
+#define PCIE_LCAP2_SUP_LNKS64 __BIT(6) /* Supported Speed 64GT/ */
#define PCIE_LCAP2_CROSSLNK __BIT(8) /* Crosslink Supported */
#define PCIE_LCAP2_LOWSKPOS_GENSUPPSV __BITS(15, 9)
/* Lower SKP OS Generation Supp. Spd. Vect */
@@ -1157,12 +1183,12 @@ typedef u_int8_t pci_revision_t;
* Other than Root Complex Integrated Endpoint and Root Complex Event Collector
* have link related registers.
*/
-#define PCIE_HAS_LINKREGS(type) (((type) != PCIE_XCAP_TYPE_ROOT_INTEP) && \
- ((type) != PCIE_XCAP_TYPE_ROOT_EVNTC))
+#define PCIE_HAS_LINKREGS(type) (((type) != PCIE_XCAP_TYPE_RCIEP) && \
+ ((type) != PCIE_XCAP_TYPE_RC_EVNTC))
/* Only root port and root complex event collector have PCIE_RCR & PCIE_RSR */
-#define PCIE_HAS_ROOTREGS(type) (((type) == PCIE_XCAP_TYPE_ROOT) || \
- ((type) == PCIE_XCAP_TYPE_ROOT_EVNTC))
+#define PCIE_HAS_ROOTREGS(type) (((type) == PCIE_XCAP_TYPE_RP) || \
+ ((type) == PCIE_XCAP_TYPE_RC_EVNTC))
/*
@@ -1509,6 +1535,9 @@ struct pci_rom {
#define PCI_EXTCAP_RTR 0x0022 /* Readiness Time Reporting */
#define PCI_EXTCAP_DESIGVNDSP 0x0023 /* Designated Vendor-Specific */
#define PCI_EXTCAP_VF_RESIZBAR 0x0024 /* VF Resizable BAR */
+#define PCI_EXTCAP_DLF 0x0025 /* Data link Feature */
+#define PCI_EXTCAP_PYSLAY_16GT 0x0026 /* Physical Layer 16.0 GT/s */
+#define PCI_EXTCAP_LMR 0x0027 /* Lane Margining at the Receiver */
#define PCI_EXTCAP_HIERARCHYID 0x0028 /* Hierarchy ID */
#define PCI_EXTCAP_NPEM 0x0029 /* Native PCIe Enclosure Management */
@@ -1552,8 +1581,6 @@ struct pci_rom {
/* Shares bits with COR_STATUS */
#define PCI_AER_CAP_CONTROL 0x18 /* AE Capabilities and Control Reg. */
#define PCI_AER_FIRST_ERROR_PTR __BITS(4, 0)
-#define PCI_AER_FIRST_ERROR_PTR_S 0
-#define PCI_AER_FIRST_ERROR_PTR_M 0x1f
#define PCI_AER_ECRC_GEN_CAPABLE __BIT(5)
#define PCI_AER_ECRC_GEN_ENABLE __BIT(6)
#define PCI_AER_ECRC_CHECK_CAPABLE __BIT(7)
@@ -1578,15 +1605,9 @@ struct pci_rom {
#define PCI_AER_ROOTERR_NF_ERR __BIT(5)
#define PCI_AER_ROOTERR_F_ERR __BIT(6)
#define PCI_AER_ROOTERR_INT_MESSAGE __BITS(31, 27)
-#define PCI_AER_ROOTERR_INT_MESSAGE_S 27
-#define PCI_AER_ROOTERR_INT_MESSAGE_M 0x1f
#define PCI_AER_ERRSRC_ID 0x34 /* Error Source Identification Reg. */
#define PCI_AER_ERRSRC_ID_ERR_COR __BITS(15, 0)
-#define PCI_AER_ERRSRC_ID_ERR_COR_S 0
-#define PCI_AER_ERRSRC_ID_ERR_COR_M 0xffff
#define PCI_AER_ERRSRC_ID_ERR_UC __BITS(31, 16)
-#define PCI_AER_ERRSRC_ID_ERR_UC_S 16
-#define PCI_AER_ERRSRC_ID_ERR_UC_M 0xffff
/* Only for root complex ports */
#define PCI_AER_TLP_PREFIX_LOG 0x38 /*TLP Prefix Log Register */
/* Only for TLP prefix functions */
@@ -1597,31 +1618,19 @@ struct pci_rom {
*/
#define PCI_VC_CAP1 0x04 /* Port VC Capability Register 1 */
#define PCI_VC_CAP1_EXT_COUNT __BITS(2, 0)
-#define PCI_VC_CAP1_EXT_COUNT_S 0
-#define PCI_VC_CAP1_EXT_COUNT_M 0x7
#define PCI_VC_CAP1_LOWPRI_EXT_COUNT __BITS(6, 4)
-#define PCI_VC_CAP1_LOWPRI_EXT_COUNT_S 4
-#define PCI_VC_CAP1_LOWPRI_EXT_COUNT_M 0x7
#define PCI_VC_CAP1_REFCLK __BITS(9, 8)
-#define PCI_VC_CAP1_REFCLK_S 8
-#define PCI_VC_CAP1_REFCLK_M 0x3
#define PCI_VC_CAP1_REFCLK_100NS 0x0
#define PCI_VC_CAP1_PORT_ARB_TABLE_SIZE __BITS(11, 10)
-#define PCI_VC_CAP1_PORT_ARB_TABLE_SIZE_S 10
-#define PCI_VC_CAP1_PORT_ARB_TABLE_SIZE_M 0x3
#define PCI_VC_CAP2 0x08 /* Port VC Capability Register 2 */
#define PCI_VC_CAP2_ARB_CAP_HW_FIXED_SCHEME __BIT(0)
#define PCI_VC_CAP2_ARB_CAP_WRR_32 __BIT(1)
#define PCI_VC_CAP2_ARB_CAP_WRR_64 __BIT(2)
#define PCI_VC_CAP2_ARB_CAP_WRR_128 __BIT(3)
#define PCI_VC_CAP2_ARB_TABLE_OFFSET __BITS(31, 24)
-#define PCI_VC_CAP2_ARB_TABLE_OFFSET_S 24
-#define PCI_VC_CAP2_ARB_TABLE_OFFSET_M 0xff
#define PCI_VC_CONTROL 0x0c /* Port VC Control Register (16bit) */
#define PCI_VC_CONTROL_LOAD_VC_ARB_TABLE __BIT(0)
#define PCI_VC_CONTROL_VC_ARB_SELECT __BITS(3, 1)
-#define PCI_VC_CONTROL_VC_ARB_SELECT_S 1
-#define PCI_VC_CONTROL_VC_ARB_SELECT_M 0x7
#define PCI_VC_STATUS 0x0e /* Port VC Status Register (16bit) */
#define PCI_VC_STATUS_LOAD_VC_ARB_TABLE __BIT(0)
#define PCI_VC_RESOURCE_CAP(n) (0x10 + ((n) * 0x0c)) /* VC Resource Capability Register */
@@ -1634,22 +1643,12 @@ struct pci_rom {
#define PCI_VC_RESOURCE_CAP_ADV_PKT_SWITCH __BIT(14)
#define PCI_VC_RESOURCE_CAP_REJCT_SNOOP_TRANS __BIT(15)
#define PCI_VC_RESOURCE_CAP_MAX_TIME_SLOTS __BITS(22, 16)
-#define PCI_VC_RESOURCE_CAP_MAX_TIME_SLOTS_S 16
-#define PCI_VC_RESOURCE_CAP_MAX_TIME_SLOTS_M 0x7f
#define PCI_VC_RESOURCE_CAP_PORT_ARB_TABLE_OFFSET __BITS(31, 24)
-#define PCI_VC_RESOURCE_CAP_PORT_ARB_TABLE_OFFSET_S 24
-#define PCI_VC_RESOURCE_CAP_PORT_ARB_TABLE_OFFSET_M 0xff
#define PCI_VC_RESOURCE_CTL(n) (0x14 + ((n) * 0x0c)) /* VC Resource Control Register */
#define PCI_VC_RESOURCE_CTL_TCVC_MAP __BITS(7, 0)
-#define PCI_VC_RESOURCE_CTL_TCVC_MAP_S 0
-#define PCI_VC_RESOURCE_CTL_TCVC_MAP_M 0xff
#define PCI_VC_RESOURCE_CTL_LOAD_PORT_ARB_TABLE __BIT(16)
#define PCI_VC_RESOURCE_CTL_PORT_ARB_SELECT __BITS(19, 17)
-#define PCI_VC_RESOURCE_CTL_PORT_ARB_SELECT_S 17
-#define PCI_VC_RESOURCE_CTL_PORT_ARB_SELECT_M 0x7
#define PCI_VC_RESOURCE_CTL_VC_ID __BITS(26, 24)
-#define PCI_VC_RESOURCE_CTL_VC_ID_S 24
-#define PCI_VC_RESOURCE_CTL_VC_ID_M 0x7
#define PCI_VC_RESOURCE_CTL_VC_ENABLE __BIT(31)
#define PCI_VC_RESOURCE_STA(n) (0x18 + ((n) * 0x0c)) /* VC Resource Status Register */
#define PCI_VC_RESOURCE_STA_PORT_ARB_TABLE __BIT(0)
@@ -1804,8 +1803,6 @@ struct pci_rom {
#define PCI_SRIOV_CAP_VF_MIGRATION __BIT(0)
#define PCI_SRIOV_CAP_ARI_CAP_HIER_PRESERVED __BIT(1)
#define PCI_SRIOV_CAP_VF_MIGRATION_INTMSG_N __BITS(31, 21)
-#define PCI_SRIOV_CAP_VF_MIGRATION_INTMSG_N_S 21
-#define PCI_SRIOV_CAP_VF_MIGRATION_INTMSG_N_M 0x7ff
#define PCI_SRIOV_CTL 0x08 /* SR-IOV Control (16bit) */
#define PCI_SRIOV_CTL_VF_ENABLE __BIT(0)
#define PCI_SRIOV_CTL_VF_MIGRATION_SUPPORT __BIT(1)
@@ -1828,11 +1825,7 @@ struct pci_rom {
#define PCI_SRIOV_BAR(x) (PCI_SRIOV_BARS + ((x) * 4))
#define PCI_SRIOV_VF_MIG_STA_AR 0x3c /* VF Migration State Array Offset */
#define PCI_SRIOV_VF_MIG_STA_OFFSET __BITS(31, 3)
-#define PCI_SRIOV_VF_MIG_STA_OFFSET_S 3
-#define PCI_SRIOV_VF_MIG_STA_OFFSET_M 0x1fffffff
#define PCI_SRIOV_VF_MIG_STA_BIR __BITS(2, 0)
-#define PCI_SRIOV_VF_MIG_STA_BIR_S 0
-#define PCI_SRIOV_VF_MIG_STA_BIR_M 0x7
/*
* Extended capability ID: 0x0011
@@ -1870,7 +1863,7 @@ struct pci_rom {
* Page Request
*/
#define PCI_PAGE_REQ_CTL 0x04 /* Control Register */
-#define PCI_PAGE_REQ_CTL_E __BIT(0) /* Enalbe */
+#define PCI_PAGE_REQ_CTL_E __BIT(0) /* Enable */
#define PCI_PAGE_REQ_CTL_R __BIT(1) /* Reset */
#define PCI_PAGE_REQ_STA 0x04 /* Status Register */
#define PCI_PAGE_REQ_STA_RF __BIT(0+16) /* Response Failure */
@@ -1893,38 +1886,36 @@ struct pci_rom {
/* Bit definitions for the first DW of each entry */
#define PCI_EA_ES __BITS(2, 0) /* Entry Size */
#define PCI_EA_BEI __BITS(7, 4) /* BAR Equivalent Indicator */
-#define PCI_EA_BEI_BAR0 0 /* BAR0 (10h) */
-#define PCI_EA_BEI_BAR1 1 /* BAR1 (14h) */
-#define PCI_EA_BEI_BAR2 2 /* BAR2 (18h) */
-#define PCI_EA_BEI_BAR3 3 /* BAR3 (1ch) */
-#define PCI_EA_BEI_BAR4 4 /* BAR4 (20h) */
-#define PCI_EA_BEI_BAR5 5 /* BAR5 (24h) */
-#define PCI_EA_BEI_BEHIND 6 /* Behind the function (for type1) */
-#define PCI_EA_BEI_NOTIND 7 /* Not Indicated */
-#define PCI_EA_BEI_EXPROM 8 /* Expansion ROM */
-#define PCI_EA_BEI_VFBAR0 9 /* VF BAR0 */
-#define PCI_EA_BEI_VFBAR1 10 /* VF BAR1 */
-#define PCI_EA_BEI_VFBAR2 11 /* VF BAR2 */
-#define PCI_EA_BEI_VFBAR3 12 /* VF BAR3 */
-#define PCI_EA_BEI_VFBAR4 13 /* VF BAR4 */
-#define PCI_EA_BEI_VFBAR5 14 /* VF BAR5 */
-#define PCI_EA_BEI_RESERVED 15 /* Reserved (treat as Not Indicated) */
-
+#define PCI_EA_BEI_BAR0 0 /* BAR0 (10h) */
+#define PCI_EA_BEI_BAR1 1 /* BAR1 (14h) */
+#define PCI_EA_BEI_BAR2 2 /* BAR2 (18h) */
+#define PCI_EA_BEI_BAR3 3 /* BAR3 (1ch) */
+#define PCI_EA_BEI_BAR4 4 /* BAR4 (20h) */
+#define PCI_EA_BEI_BAR5 5 /* BAR5 (24h) */
+#define PCI_EA_BEI_BEHIND 6 /* Behind the function (for type1) */
+#define PCI_EA_BEI_NOTIND 7 /* Not Indicated */
+#define PCI_EA_BEI_EXPROM 8 /* Expansion ROM */
+#define PCI_EA_BEI_VFBAR0 9 /* VF BAR0 */
+#define PCI_EA_BEI_VFBAR1 10 /* VF BAR1 */
+#define PCI_EA_BEI_VFBAR2 11 /* VF BAR2 */
+#define PCI_EA_BEI_VFBAR3 12 /* VF BAR3 */
+#define PCI_EA_BEI_VFBAR4 13 /* VF BAR4 */
+#define PCI_EA_BEI_VFBAR5 14 /* VF BAR5 */
+#define PCI_EA_BEI_RESERVED 15 /* Reserved (treat as Not Indicated) */
#define PCI_EA_PP __BITS(15, 8) /* Primary Properties */
#define PCI_EA_SP __BITS(23, 16) /* Secondary Properties */
/* PP and SP's values */
-#define PCI_EA_PROP_MEM_NONPREF 0x00 /* Memory Space, Non-Prefetchable */
-#define PCI_EA_PROP_MEM_PREF 0x01 /* Memory Space, Prefetchable */
-#define PCI_EA_PROP_IO 0x02 /* I/O Space */
-#define PCI_EA_PROP_VF_MEM_NONPREF 0x03 /* Resorce for VF use. Mem. Non-Pref */
-#define PCI_EA_PROP_VF_MEM_PREF 0x04 /* Resorce for VF use. Mem. Prefetch */
-#define PCI_EA_PROP_BB_MEM_NONPREF 0x05 /* Behind Bridge: MEM. Non-Pref */
-#define PCI_EA_PROP_BB_MEM_PREF 0x06 /* Behind Bridge: MEM. Prefetch */
-#define PCI_EA_PROP_BB_IO 0x07 /* Behind Bridge: I/O Space */
-#define PCI_EA_PROP_MEM_UNAVAIL 0xfd /* Memory Space Unavailable */
-#define PCI_EA_PROP_IO_UNAVAIL 0xfe /* IO Space Unavailable */
-#define PCI_EA_PROP_UNAVAIL 0xff /* Entry Unavailable for use */
-
+#define PCI_EA_PROP_MEM_NONPREF 0x00 /* Memory Space, Non-Prefetchable */
+#define PCI_EA_PROP_MEM_PREF 0x01 /* Memory Space, Prefetchable */
+#define PCI_EA_PROP_IO 0x02 /* I/O Space */
+#define PCI_EA_PROP_VF_MEM_NONPREF 0x03 /* Resorce for VF use. Mem. Non-Pref */
+#define PCI_EA_PROP_VF_MEM_PREF 0x04 /* Resorce for VF use. Mem. Prefetch */
+#define PCI_EA_PROP_BB_MEM_NONPREF 0x05 /* Behind Bridge: MEM. Non-Pref */
+#define PCI_EA_PROP_BB_MEM_PREF 0x06 /* Behind Bridge: MEM. Prefetch */
+#define PCI_EA_PROP_BB_IO 0x07 /* Behind Bridge: I/O Space */
+#define PCI_EA_PROP_MEM_UNAVAIL 0xfd /* Memory Space Unavailable */
+#define PCI_EA_PROP_IO_UNAVAIL 0xfe /* IO Space Unavailable */
+#define PCI_EA_PROP_UNAVAIL 0xff /* Entry Unavailable for use */
#define PCI_EA_W __BIT(30) /* Writable */
#define PCI_EA_E __BIT(31) /* Enable for this entry */
@@ -1972,11 +1963,11 @@ struct pci_rom {
#define PCI_TPH_REQ_CAP_NOST __BIT(0) /* No ST Mode Supported */
#define PCI_TPH_REQ_CAP_INTVEC __BIT(1) /* Intr Vec Mode Supported */
#define PCI_TPH_REQ_CAP_DEVSPEC __BIT(2) /* Device Specific Mode Supported */
-#define PCI_TPH_REQ_CAP_XTPHREQ __BIT(8) /* Extend TPH Reqester Supported */
+#define PCI_TPH_REQ_CAP_XTPHREQ __BIT(8) /* Extend TPH Requester Supported */
#define PCI_TPH_REQ_CAP_STTBLLOC __BITS(10, 9) /* ST Table Location */
-#define PCI_TPH_REQ_STTBLLOC_NONE 0 /* not present */
-#define PCI_TPH_REQ_STTBLLOC_TPHREQ 1 /* in the TPHREQ cap */
-#define PCI_TPH_REQ_STTBLLOC_MSIX 2 /* in the MSI-X table */
+#define PCI_TPH_REQ_STTBLLOC_NONE 0 /* not present */
+#define PCI_TPH_REQ_STTBLLOC_TPHREQ 1 /* in the TPHREQ cap */
+#define PCI_TPH_REQ_STTBLLOC_MSIX 2 /* in the MSI-X table */
#define PCI_TPH_REQ_CAP_STTBLSIZ __BITS(26, 16) /* ST Table Size */
#define PCI_TPH_REQ_CTL 0x08 /* TPH Requester Control */
#define PCI_TPH_REQ_CTL_STSEL __BITS(2, 0) /* ST Mode Select */
@@ -2088,7 +2079,7 @@ struct pci_rom {
#define PCI_DPC_RPPIO_MEMUR_CPL __BIT(16) /* MemReq received UR Complt. */
#define PCI_DPC_RPPIO_MEMCA_CPL __BIT(17) /* MemReq received CA Complt. */
#define PCI_DPC_RPPIO_MEM_CTO __BIT(18) /* MemReq Completion Timeout */
-
+
#define PCI_DPC_RPPIO_MASK 0x10 /* RP PIO Mask Register */
/* Bits are the same as RP PIO Status Register */
#define PCI_DPC_RPPIO_SEVE 0x14 /* RP PIO Severity Register */
@@ -2171,6 +2162,23 @@ struct pci_rom {
*/
/*
+ * Extended capability ID: 0x0025
+ * Data link Feature
+ */
+#define PCI_DLF_CAP 0x04 /* Capability register */
+#define PCI_DLF_LFEAT __BITS(22, 0) /* Local DLF supported */
+#define PCI_DLF_LFEAT_SCLFCTL __BIT(0) /* Scaled Flow Control */
+#define PCI_DLF_CAP_XCHG __BIT(31) /* DLF Exchange enable */
+#define PCI_DLF_STAT 0x08 /* Status register */
+ /* Bit 22:0 is the same as PCI_DLF_CAP_LINKFEAT */
+#define PCI_DLF_STAT_RMTVALID __BIT(31) /* Remote DLF supported Valid */
+
+/*
+ * Extended capability ID: 0x0026
+ * Physical Layer 16.0 GT/s
+ */
+
+/*
* Extended capability ID: 0x0028
* Hierarchy ID
*/
Index: src/sys/dev/pci/ppb.c
diff -u src/sys/dev/pci/ppb.c:1.63.2.2 src/sys/dev/pci/ppb.c:1.63.2.3
--- src/sys/dev/pci/ppb.c:1.63.2.2 Wed Jul 17 15:55:31 2019
+++ src/sys/dev/pci/ppb.c Fri Dec 3 19:45:13 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: ppb.c,v 1.63.2.2 2019/07/17 15:55:31 martin Exp $ */
+/* $NetBSD: ppb.c,v 1.63.2.3 2021/12/03 19:45:13 martin Exp $ */
/*
* Copyright (c) 1996, 1998 Christopher G. Demetriou. All rights reserved.
@@ -31,7 +31,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: ppb.c,v 1.63.2.2 2019/07/17 15:55:31 martin Exp $");
+__KERNEL_RCSID(0, "$NetBSD: ppb.c,v 1.63.2.3 2021/12/03 19:45:13 martin Exp $");
#include <sys/param.h>
#include <sys/systm.h>
@@ -142,7 +142,7 @@ ppb_print_pcie(device_t self)
case PCIE_XCAP_TYPE_PCI_DEV:
aprint_normal("Legacy PCI-E Endpoint device");
break;
- case PCIE_XCAP_TYPE_ROOT:
+ case PCIE_XCAP_TYPE_RP:
aprint_normal("Root Port of PCI-E Root Complex");
break;
case PCIE_XCAP_TYPE_UP:
@@ -163,7 +163,7 @@ ppb_print_pcie(device_t self)
}
switch (devtype) {
- case PCIE_XCAP_TYPE_ROOT:
+ case PCIE_XCAP_TYPE_RP:
case PCIE_XCAP_TYPE_DOWN:
case PCIE_XCAP_TYPE_PCI2PCIE:
reg = pci_conf_read(sc->sc_pc, sc->sc_tag, off + PCIE_LCAP);
