Module Name: src
Committed By: riastradh
Date: Sun Dec 19 11:39:56 UTC 2021
Modified Files:
src/sys/external/bsd/drm2/dist/drm/i915/gt: intel_ggtt.c intel_gt.c
intel_gtt.h
src/sys/external/bsd/drm2/i915drm: intel_gtt.c
src/sys/external/bsd/drm2/include/asm: smp.h
src/sys/external/bsd/drm2/include/drm: intel-gtt.h
src/sys/external/bsd/drm2/include/linux: io-mapping.h
Log Message:
i915: ggtt
To generate a diff of this commit:
cvs rdiff -u -r1.6 -r1.7 \
src/sys/external/bsd/drm2/dist/drm/i915/gt/intel_ggtt.c
cvs rdiff -u -r1.2 -r1.3 \
src/sys/external/bsd/drm2/dist/drm/i915/gt/intel_gt.c
cvs rdiff -u -r1.11 -r1.12 \
src/sys/external/bsd/drm2/dist/drm/i915/gt/intel_gtt.h
cvs rdiff -u -r1.12 -r1.13 src/sys/external/bsd/drm2/i915drm/intel_gtt.c
cvs rdiff -u -r1.1 -r1.2 src/sys/external/bsd/drm2/include/asm/smp.h
cvs rdiff -u -r1.8 -r1.9 src/sys/external/bsd/drm2/include/drm/intel-gtt.h
cvs rdiff -u -r1.7 -r1.8 src/sys/external/bsd/drm2/include/linux/io-mapping.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/external/bsd/drm2/dist/drm/i915/gt/intel_ggtt.c
diff -u src/sys/external/bsd/drm2/dist/drm/i915/gt/intel_ggtt.c:1.6 src/sys/external/bsd/drm2/dist/drm/i915/gt/intel_ggtt.c:1.7
--- src/sys/external/bsd/drm2/dist/drm/i915/gt/intel_ggtt.c:1.6 Sun Dec 19 10:28:52 2021
+++ src/sys/external/bsd/drm2/dist/drm/i915/gt/intel_ggtt.c Sun Dec 19 11:39:55 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: intel_ggtt.c,v 1.6 2021/12/19 10:28:52 riastradh Exp $ */
+/* $NetBSD: intel_ggtt.c,v 1.7 2021/12/19 11:39:55 riastradh Exp $ */
// SPDX-License-Identifier: MIT
/*
@@ -6,7 +6,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: intel_ggtt.c,v 1.6 2021/12/19 10:28:52 riastradh Exp $");
+__KERNEL_RCSID(0, "$NetBSD: intel_ggtt.c,v 1.7 2021/12/19 11:39:55 riastradh Exp $");
#include <linux/stop_machine.h>
@@ -24,6 +24,8 @@ __KERNEL_RCSID(0, "$NetBSD: intel_ggtt.c
#include "intel_gtt.h"
+#include <linux/nbsd-namespace.h>
+
static int
i915_get_ggtt_vma_pages(struct i915_vma *vma);
@@ -203,23 +205,6 @@ gen8_set_pte(bus_space_tag_t bst, bus_sp
bus_space_write_4(bst, bsh, 8*i + 4, (uint32_t)(pte >> 32));
#endif
}
-static gen8_pte_t
-gen8_get_pte(bus_space_tag_t bst, bus_space_handle_t bsh, unsigned i)
-{
- CTASSERT(_BYTE_ORDER == _LITTLE_ENDIAN); /* x86 */
- CTASSERT(sizeof(gen8_pte_t) == 8);
-#ifdef _LP64 /* XXX How to detect bus_space_read_8? */
- return bus_space_read_8(bst, bsh, 8*i);
-#else
- /*
- * XXX I'm not sure this case can actually happen in practice:
- * 32-bit gen8 chipsets?
- */
- return bus_space_read_4(bst, bsh, 8*i) |
- ((uint64_t)bus_space_read_4(bst, bsh, 8*i + 4) << 32);
-#endif
-}
-
#else
static void gen8_set_pte(void __iomem *addr, gen8_pte_t pte)
{
@@ -234,10 +219,17 @@ static void gen8_ggtt_insert_page(struct
u32 unused)
{
struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm);
+#ifndef __NetBSD__
gen8_pte_t __iomem *pte =
(gen8_pte_t __iomem *)ggtt->gsm + offset / I915_GTT_PAGE_SIZE;
+#endif
+#ifdef __NetBSD__
+ gen8_set_pte(ggtt->gsmt, ggtt->gsmh, offset / I915_GTT_PAGE_SIZE,
+ gen8_pte_encode(addr, level, 0));
+#else
gen8_set_pte(pte, gen8_pte_encode(addr, level, 0));
+#endif
ggtt->invalidate(ggtt);
}
@@ -249,7 +241,7 @@ static void gen8_ggtt_insert_entries(str
{
struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm);
#ifdef __NetBSD__
- bus_dmamap_t map = vma->pages;
+ bus_dmamap_t map = vma->pages->sgl[0].sg_dmamap;
unsigned seg;
unsigned pgno;
#else
@@ -264,10 +256,27 @@ static void gen8_ggtt_insert_entries(str
* not to allow the user to override access to a read only page.
*/
+#ifdef __NetBSD__
+ pgno = vma->node.start / I915_GTT_PAGE_SIZE;
+ for (seg = 0; seg < map->dm_nsegs; seg++) {
+ addr = map->dm_segs[seg].ds_addr;
+ bus_size_t len = map->dm_segs[seg].ds_len;
+ KASSERT((addr % I915_GTT_PAGE_SIZE) == 0);
+ KASSERT((len % I915_GTT_PAGE_SIZE) == 0);
+ for (;
+ len >= I915_GTT_PAGE_SIZE;
+ addr += I915_GTT_PAGE_SIZE, len -= I915_GTT_PAGE_SIZE) {
+ gen8_set_pte(ggtt->gsmt, ggtt->gsmh, pgno++,
+ pte_encode | addr);
+ }
+ KASSERT(len == 0);
+ }
+#else
gtt_entries = (gen8_pte_t __iomem *)ggtt->gsm;
gtt_entries += vma->node.start / I915_GTT_PAGE_SIZE;
for_each_sgt_daddr(addr, sgt_iter, vma->pages)
gen8_set_pte(gtt_entries++, pte_encode | addr);
+#endif
/*
* We want to flush the TLBs only after we're certain all the PTE
@@ -289,7 +298,7 @@ static void gen6_ggtt_insert_page(struct
#endif
#ifdef __NetBSD__
- bus_space_write_4(ggtt->gsmt, ggtt->gsmh, offset >> PAGE_SHIFT,
+ bus_space_write_4(ggtt->gsmt, ggtt->gsmh, offset / I915_GTT_PAGE_SIZE,
vm->pte_encode(addr, level, flags));
#else
iowrite32(vm->pte_encode(addr, level, flags), pte);
@@ -312,24 +321,26 @@ static void gen6_ggtt_insert_entries(str
{
struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm);
#ifdef __NetBSD__
- bus_dmamap_t map = vma->pages;
+ bus_dmamap_t map = vma->pages->sgl[0].sg_dmamap;
unsigned seg;
unsigned pgno;
#else
gen6_pte_t __iomem *entries = (gen6_pte_t __iomem *)ggtt->gsm;
unsigned int i = vma->node.start / I915_GTT_PAGE_SIZE;
struct sgt_iter iter;
- dma_addr_t addr;
#endif
+ dma_addr_t addr;
#ifdef __NetBSD__
pgno = vma->node.start >> PAGE_SHIFT;
for (seg = 0; seg < map->dm_nsegs; seg++) {
addr = map->dm_segs[seg].ds_addr;
bus_size_t len = map->dm_segs[seg].ds_len;
- KASSERT((addr & (PAGE_SIZE - 1)) == 0);
- KASSERT((len & (PAGE_SIZE - 1)) == 0);
- for (; len >= PAGE_SIZE; addr += PAGE_SIZE, len -= PAGE_SIZE) {
+ KASSERT((addr % I915_GTT_PAGE_SIZE) == 0);
+ KASSERT((len % I915_GTT_PAGE_SIZE) == 0);
+ for (;
+ len >= I915_GTT_PAGE_SIZE;
+ addr += I915_GTT_PAGE_SIZE, len -= I915_GTT_PAGE_SIZE) {
/* XXX KASSERT(pgno < ...)? */
CTASSERT(sizeof(gen6_pte_t) == 4);
bus_space_write_4(ggtt->gsmt, ggtt->gsmh,
@@ -1003,16 +1014,12 @@ static int gen8_gmch_probe(struct i915_g
/* TODO: We're not aware of mappable constraints on gen8 yet */
if (!IS_DGFX(i915)) {
-#ifdef __NetBSD__
- ggtt->gmadr.start = pci_resource_start(pdev, 2);
- ggtt->mappable_end = pci_resource_len(pdev, 2);
-#else
ggtt->gmadr = pci_resource(pdev, 2);
ggtt->mappable_end = resource_size(&ggtt->gmadr);
-#endif
}
#ifdef __NetBSD__
+ __USE(err);
ggtt->max_paddr = DMA_BIT_MASK(39);
#else
err = pci_set_dma_mask(pdev, DMA_BIT_MASK(39));
@@ -1159,13 +1166,8 @@ static int gen6_gmch_probe(struct i915_g
u16 snb_gmch_ctl;
int err;
-#ifdef __NetBSD__
- ggtt->gmadr.start = pci_resource_start(pdev, 2);
- ggtt->mappable_end = pci_resource_len(pdev, 2);
-#else
ggtt->gmadr = pci_resource(pdev, 2);
ggtt->mappable_end = resource_size(&ggtt->gmadr);
-#endif
/*
* 64/512MB is the current min/max we actually know of, but this is
@@ -1177,6 +1179,7 @@ static int gen6_gmch_probe(struct i915_g
}
#ifdef __NetBSD__
+ __USE(err);
ggtt->max_paddr = DMA_BIT_MASK(40);
#else
err = pci_set_dma_mask(pdev, DMA_BIT_MASK(40));
@@ -1237,21 +1240,17 @@ static int i915_gmch_probe(struct i915_g
intel_gtt_get(&ggtt->vm.total, &gmadr_base, &ggtt->mappable_end);
+ ggtt->gmadr =
+ (struct resource)DEFINE_RES_MEM(gmadr_base, ggtt->mappable_end);
+
#ifdef __NetBSD__
- ggtt->gmadr.start = gmadr_base;
/* Based on i915_drv.c, i915_driver_hw_probe. */
- if (INTEL_INFO(dev)->gen <= 2)
+ if (IS_GEN(i915, 2))
ggtt->max_paddr = DMA_BIT_MASK(30);
- else if ((INTEL_INFO(dev)->gen <= 3) ||
- IS_BROADWATER(dev) || IS_CRESTLINE(dev))
+ else if (IS_I965G(i915) || IS_I965GM(i915))
ggtt->max_paddr = DMA_BIT_MASK(32);
- else if (INTEL_INFO(dev)->gen <= 5)
- ggtt->max_paddr = DMA_BIT_MASK(36);
else
ggtt->max_paddr = DMA_BIT_MASK(40);
-#else
- ggtt->gmadr =
- (struct resource)DEFINE_RES_MEM(gmadr_base, ggtt->mappable_end);
#endif
ggtt->do_idle_maps = needs_idle_maps(i915);
@@ -1308,7 +1307,7 @@ static int ggtt_probe_hw(struct i915_ggt
if ((ggtt->vm.total - 1) >> 32) {
DRM_ERROR("We never expected a Global GTT with more than 32bits"
- " of address space! Found %lldM!\n",
+ " of address space! Found %"PRId64"M!\n",
ggtt->vm.total >> 20);
ggtt->vm.total = 1ULL << 32;
ggtt->mappable_end =
@@ -1317,15 +1316,15 @@ static int ggtt_probe_hw(struct i915_ggt
if (ggtt->mappable_end > ggtt->vm.total) {
DRM_ERROR("mappable aperture extends past end of GGTT,"
- " aperture=%pa, total=%llx\n",
+ " aperture=%pa, total=%"PRIx64"\n",
&ggtt->mappable_end, ggtt->vm.total);
ggtt->mappable_end = ggtt->vm.total;
}
/* GMADR is the PCI mmio aperture into the global GTT. */
- DRM_DEBUG_DRIVER("GGTT size = %lluM\n", ggtt->vm.total >> 20);
- DRM_DEBUG_DRIVER("GMADR size = %lluM\n", (u64)ggtt->mappable_end >> 20);
- DRM_DEBUG_DRIVER("DSM size = %lluM\n",
+ DRM_DEBUG_DRIVER("GGTT size = %"PRIx64"M\n", ggtt->vm.total >> 20);
+ DRM_DEBUG_DRIVER("GMADR size = %"PRIx64"M\n", (u64)ggtt->mappable_end >> 20);
+ DRM_DEBUG_DRIVER("DSM size = %"PRIx64"M\n",
(u64)resource_size(&intel_graphics_stolen_res) >> 20);
return 0;
@@ -1432,6 +1431,8 @@ void i915_gem_restore_gtt_mappings(struc
setup_private_pat(ggtt->vm.gt->uncore);
}
+#ifndef __NetBSD__
+
static struct scatterlist *
rotate_pages(struct drm_i915_gem_object *obj, unsigned int offset,
unsigned int width, unsigned int height,
@@ -1639,6 +1640,8 @@ err_st_alloc:
return ERR_PTR(ret);
}
+#endif /* __NetBSD__ */
+
static int
i915_get_ggtt_vma_pages(struct i915_vma *vma)
{
@@ -1660,6 +1663,7 @@ i915_get_ggtt_vma_pages(struct i915_vma
vma->pages = vma->obj->mm.pages;
return 0;
+#ifndef __NetBSD__
case I915_GGTT_VIEW_ROTATED:
vma->pages =
intel_rotate_pages(&vma->ggtt_view.rotated, vma->obj);
@@ -1673,6 +1677,7 @@ i915_get_ggtt_vma_pages(struct i915_vma
case I915_GGTT_VIEW_PARTIAL:
vma->pages = intel_partial_pages(&vma->ggtt_view, vma->obj);
break;
+#endif
}
ret = 0;
Index: src/sys/external/bsd/drm2/dist/drm/i915/gt/intel_gt.c
diff -u src/sys/external/bsd/drm2/dist/drm/i915/gt/intel_gt.c:1.2 src/sys/external/bsd/drm2/dist/drm/i915/gt/intel_gt.c:1.3
--- src/sys/external/bsd/drm2/dist/drm/i915/gt/intel_gt.c:1.2 Sat Dec 18 23:45:30 2021
+++ src/sys/external/bsd/drm2/dist/drm/i915/gt/intel_gt.c Sun Dec 19 11:39:55 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: intel_gt.c,v 1.2 2021/12/18 23:45:30 riastradh Exp $ */
+/* $NetBSD: intel_gt.c,v 1.3 2021/12/19 11:39:55 riastradh Exp $ */
// SPDX-License-Identifier: MIT
/*
@@ -6,9 +6,13 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: intel_gt.c,v 1.2 2021/12/18 23:45:30 riastradh Exp $");
+__KERNEL_RCSID(0, "$NetBSD: intel_gt.c,v 1.3 2021/12/19 11:39:55 riastradh Exp $");
+#include <linux/kernel.h>
+
+#if IS_ENABLED(CONFIG_DEBUGFS)
#include "debugfs_gt.h"
+#endif
#include "i915_drv.h"
#include "intel_context.h"
#include "intel_gt.h"
@@ -204,7 +208,7 @@ static void gen6_check_faults(struct int
fault = GEN6_RING_FAULT_REG_READ(engine);
if (fault & RING_FAULT_VALID) {
DRM_DEBUG_DRIVER("Unexpected fault\n"
- "\tAddr: 0x%08lx\n"
+ "\tAddr: 0x%08"PRIx32"\n"
"\tAddress space: %s\n"
"\tSource ID: %d\n"
"\tType: %d\n",
@@ -326,7 +330,9 @@ void intel_gt_driver_register(struct int
{
intel_rps_driver_register(>->rps);
+#if IS_ENABLED(CONFIG_DEBUGFS)
debugfs_gt_register(gt);
+#endif
}
static int intel_gt_init_scratch(struct intel_gt *gt, unsigned int size)
Index: src/sys/external/bsd/drm2/dist/drm/i915/gt/intel_gtt.h
diff -u src/sys/external/bsd/drm2/dist/drm/i915/gt/intel_gtt.h:1.11 src/sys/external/bsd/drm2/dist/drm/i915/gt/intel_gtt.h:1.12
--- src/sys/external/bsd/drm2/dist/drm/i915/gt/intel_gtt.h:1.11 Sun Dec 19 11:33:30 2021
+++ src/sys/external/bsd/drm2/dist/drm/i915/gt/intel_gtt.h Sun Dec 19 11:39:55 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: intel_gtt.h,v 1.11 2021/12/19 11:33:30 riastradh Exp $ */
+/* $NetBSD: intel_gtt.h,v 1.12 2021/12/19 11:39:55 riastradh Exp $ */
/* SPDX-License-Identifier: MIT */
/*
@@ -19,6 +19,7 @@
#define __INTEL_GTT_H__
#include <linux/io-mapping.h>
+#include <linux/ioport.h>
#include <linux/highmem.h>
#include <linux/kref.h>
#include <linux/mm.h>
@@ -346,13 +347,7 @@ struct i915_ggtt {
struct i915_address_space vm;
struct io_mapping iomap; /* Mapping to our CPU mappable region */
-#ifdef __NetBSD__
- struct {
- bus_addr_t start;
- } gmadr;
-#else
struct resource gmadr; /* GMADR resource */
-#endif
resource_size_t mappable_end; /* End offset that we can CPU map */
/** "Graphics Stolen Memory" holds the global PTEs */
Index: src/sys/external/bsd/drm2/i915drm/intel_gtt.c
diff -u src/sys/external/bsd/drm2/i915drm/intel_gtt.c:1.12 src/sys/external/bsd/drm2/i915drm/intel_gtt.c:1.13
--- src/sys/external/bsd/drm2/i915drm/intel_gtt.c:1.12 Sun Dec 19 01:35:10 2021
+++ src/sys/external/bsd/drm2/i915drm/intel_gtt.c Sun Dec 19 11:39:56 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: intel_gtt.c,v 1.12 2021/12/19 01:35:10 riastradh Exp $ */
+/* $NetBSD: intel_gtt.c,v 1.13 2021/12/19 11:39:56 riastradh Exp $ */
/*-
* Copyright (c) 2014 The NetBSD Foundation, Inc.
@@ -32,7 +32,7 @@
/* Intel GTT stubs */
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: intel_gtt.c,v 1.12 2021/12/19 01:35:10 riastradh Exp $");
+__KERNEL_RCSID(0, "$NetBSD: intel_gtt.c,v 1.13 2021/12/19 11:39:56 riastradh Exp $");
#include <sys/types.h>
#include <sys/bus.h>
@@ -185,9 +185,10 @@ intel_gtt_insert_page(bus_addr_t addr, u
}
void
-intel_gtt_insert_sg_entries(bus_dmamap_t dmamap, unsigned va_page,
+intel_gtt_insert_sg_entries(struct sg_table *sg, unsigned va_page,
unsigned flags)
{
+ bus_dmamap_t dmamap = sg->sgl[0].sg_dmamap;
struct agp_i810_softc *const isc = agp_i810_sc->as_chipc;
off_t va = (off_t)va_page << PAGE_SHIFT;
unsigned seg;
Index: src/sys/external/bsd/drm2/include/asm/smp.h
diff -u src/sys/external/bsd/drm2/include/asm/smp.h:1.1 src/sys/external/bsd/drm2/include/asm/smp.h:1.2
--- src/sys/external/bsd/drm2/include/asm/smp.h:1.1 Sun Dec 19 01:53:29 2021
+++ src/sys/external/bsd/drm2/include/asm/smp.h Sun Dec 19 11:39:56 2021
@@ -0,0 +1,53 @@
+/* $NetBSD: smp.h,v 1.2 2021/12/19 11:39:56 riastradh Exp $ */
+
+/*-
+ * Copyright (c) 2021 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _ASM_SMP_H_
+#define _ASM_SMP_H_
+
+#if defined(__i386__) || defined(__amd64__)
+
+#include <sys/null.h>
+#include <sys/xcall.h>
+
+#include <machine/cpufunc.h>
+
+static void
+wbinvd_xc(void *arg0, void *arg1)
+{
+ wbinvd();
+}
+
+static inline void
+wbinvd_on_all_cpus(void)
+{
+ xc_wait(xc_broadcast(0, wbinvd_xc, NULL, NULL));
+}
+
+#endif
+
+#endif /* _ASM_SMP_H_ */
Index: src/sys/external/bsd/drm2/include/drm/intel-gtt.h
diff -u src/sys/external/bsd/drm2/include/drm/intel-gtt.h:1.8 src/sys/external/bsd/drm2/include/drm/intel-gtt.h:1.9
--- src/sys/external/bsd/drm2/include/drm/intel-gtt.h:1.8 Sun Dec 19 01:35:10 2021
+++ src/sys/external/bsd/drm2/include/drm/intel-gtt.h Sun Dec 19 11:39:56 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: intel-gtt.h,v 1.8 2021/12/19 01:35:10 riastradh Exp $ */
+/* $NetBSD: intel-gtt.h,v 1.9 2021/12/19 11:39:56 riastradh Exp $ */
/*-
* Copyright (c) 2013 The NetBSD Foundation, Inc.
@@ -37,8 +37,9 @@
#include <linux/ioport.h>
-struct pci_dev;
struct agp_bridge_data;
+struct pci_dev;
+struct sg_table;
void intel_gtt_get(uint64_t * /* GPU VA size in bytes */,
bus_addr_t * /* aperture base */,
@@ -49,7 +50,7 @@ void intel_gmch_remove(void);
bool intel_enable_gtt(void);
void intel_gtt_chipset_flush(void);
void intel_gtt_insert_page(bus_addr_t, unsigned, unsigned);
-void intel_gtt_insert_sg_entries(bus_dmamap_t, unsigned, unsigned);
+void intel_gtt_insert_sg_entries(struct sg_table *, unsigned, unsigned);
void intel_gtt_clear_range(unsigned, unsigned);
#define AGP_USER_MEMORY 1
Index: src/sys/external/bsd/drm2/include/linux/io-mapping.h
diff -u src/sys/external/bsd/drm2/include/linux/io-mapping.h:1.7 src/sys/external/bsd/drm2/include/linux/io-mapping.h:1.8
--- src/sys/external/bsd/drm2/include/linux/io-mapping.h:1.7 Sun Dec 19 01:34:30 2021
+++ src/sys/external/bsd/drm2/include/linux/io-mapping.h Sun Dec 19 11:39:56 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: io-mapping.h,v 1.7 2021/12/19 01:34:30 riastradh Exp $ */
+/* $NetBSD: io-mapping.h,v 1.8 2021/12/19 11:39:56 riastradh Exp $ */
/*-
* Copyright (c) 2013 The NetBSD Foundation, Inc.
@@ -43,7 +43,7 @@
struct io_mapping {
bus_space_tag_t diom_bst;
bus_addr_t diom_addr;
- bus_size_t diom_size;
+ bus_size_t size; /* Linux API */
vaddr_t diom_va;
bool diom_mapped;
};
@@ -76,7 +76,7 @@ bus_space_io_mapping_init_wc(bus_space_t
/* Initialize the mapping record. */
mapping->diom_bst = bst;
mapping->diom_addr = addr;
- mapping->diom_size = size;
+ mapping->size = size;
mapping->diom_mapped = false;
/* Allocate kva for one page. */
@@ -128,8 +128,8 @@ io_mapping_map_wc(struct io_mapping *map
KASSERT(size == PAGE_SIZE);
KASSERT(0 == (offset & (PAGE_SIZE - 1)));
- KASSERT(PAGE_SIZE <= mapping->diom_size);
- KASSERT(offset <= (mapping->diom_size - PAGE_SIZE));
+ KASSERT(PAGE_SIZE <= mapping->size);
+ KASSERT(offset <= (mapping->size - PAGE_SIZE));
KASSERT(__type_fit(off_t, offset));
KASSERT(!mapping->diom_mapped);
