Module Name: src
Committed By: riastradh
Date: Sun Dec 19 12:02:40 UTC 2021
Modified Files:
src/sys/external/bsd/common/include/linux: printk.h
src/sys/external/bsd/drm2/amdgpu: amdgpu_module.c files.amdgpu
src/sys/external/bsd/drm2/dist/drm/amd/amdgpu: amdgpu.h
amdgpu_bo_list.c amdgpu_cs.c amdgpu_fb.c amdgpu_fence.c
amdgpu_gart.c amdgpu_gart.h amdgpu_gem.c amdgpu_gfx_v10_0.c
amdgpu_gfx_v6_0.c amdgpu_gfx_v7_0.c amdgpu_gfx_v8_0.c
amdgpu_gfx_v9_0.c amdgpu_gmc.c amdgpu_gmc_v10_0.c amdgpu_gmc_v6_0.c
amdgpu_gmc_v7_0.c amdgpu_gmc_v8_0.c amdgpu_gmc_v9_0.c
amdgpu_gtt_mgr.c amdgpu_ids.c amdgpu_ih.c amdgpu_irq.c
amdgpu_jpeg_v1_0.c amdgpu_jpeg_v2_0.c amdgpu_jpeg_v2_5.c
amdgpu_kms.c amdgpu_mes_v10_1.c amdgpu_navi10_reg_init.c
amdgpu_navi12_reg_init.c amdgpu_navi14_reg_init.c amdgpu_nv.c
amdgpu_rlc.h amdgpu_ttm.c amdgpu_ttm.h
src/sys/external/bsd/drm2/dist/drm/amd/display/dc/basics:
amdgpu_fixpt31_32.c
src/sys/external/bsd/drm2/dist/drm/amd/display/dc/gpio: amdgpu_hw_ddc.c
amdgpu_hw_gpio.c amdgpu_hw_hpd.c
src/sys/external/bsd/drm2/dist/drm/amd/display/dc/hdcp:
amdgpu_hdcp_msg.c
src/sys/external/bsd/drm2/dist/drm/amd/display/modules/hdcp:
amdgpu_hdcp1_execution.c amdgpu_hdcp_ddc.c amdgpu_hdcp_log.c hdcp.h
src/sys/external/bsd/drm2/dist/drm/amd/display/modules/inc: mod_hdcp.h
src/sys/external/bsd/drm2/dist/drm/amd/powerplay: amdgpu_navi10_ppt.c
src/sys/external/bsd/drm2/dist/drm/amd/powerplay/smumgr:
amdgpu_fiji_smumgr.c amdgpu_iceland_smumgr.c
src/sys/external/bsd/drm2/include/linux: dma-fence.h hash.h hashtable.h
src/sys/external/bsd/drm2/include/uapi/linux: kfd_ioctl.h
src/sys/external/bsd/drm2/linux: linux_dma_fence.c
Log Message:
amdgpu_fb.c
amdgpu_fence.c
amdgpu_gart.c
amdgpu_fixpt31_32.c
amdgpu_fiji_smumgr.c
amdgpu_gem.c
amdgpu_gfx_v10_0.c
amdgpu_gfx_v6_0.c through amdgpu_gfx_v9_0.c
amdgpu_gmc.c
amdgpu_gmc_v6_0.c through amdgpu_gmc_v10_0.c
amdgpu_gtt_mgr.c
some amdgpu_h* files
some amdgpu_i* files
some amdgpu_j* files
amdgpu_kms.c
some amdgpu_m* and amdgpu_n* files
To generate a diff of this commit:
cvs rdiff -u -r1.11 -r1.12 src/sys/external/bsd/common/include/linux/printk.h
cvs rdiff -u -r1.6 -r1.7 src/sys/external/bsd/drm2/amdgpu/amdgpu_module.c
cvs rdiff -u -r1.20 -r1.21 src/sys/external/bsd/drm2/amdgpu/files.amdgpu
cvs rdiff -u -r1.6 -r1.7 \
src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/amdgpu.h \
src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/amdgpu_cs.c
cvs rdiff -u -r1.8 -r1.9 \
src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/amdgpu_bo_list.c \
src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/amdgpu_gem.c
cvs rdiff -u -r1.9 -r1.10 \
src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/amdgpu_fb.c \
src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/amdgpu_fence.c
cvs rdiff -u -r1.5 -r1.6 \
src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/amdgpu_gart.c \
src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/amdgpu_gfx_v7_0.c \
src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/amdgpu_gfx_v8_0.c \
src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/amdgpu_irq.c \
src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/amdgpu_kms.c
cvs rdiff -u -r1.2 -r1.3 \
src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/amdgpu_gart.h \
src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/amdgpu_gfx_v10_0.c \
src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/amdgpu_gfx_v6_0.c \
src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/amdgpu_gfx_v9_0.c \
src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/amdgpu_gmc.c \
src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/amdgpu_gmc_v10_0.c \
src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/amdgpu_gmc_v6_0.c \
src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/amdgpu_gmc_v9_0.c \
src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/amdgpu_gtt_mgr.c \
src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/amdgpu_ids.c \
src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/amdgpu_jpeg_v1_0.c \
src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/amdgpu_jpeg_v2_0.c \
src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/amdgpu_jpeg_v2_5.c \
src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/amdgpu_mes_v10_1.c \
src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/amdgpu_navi10_reg_init.c \
src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/amdgpu_navi12_reg_init.c \
src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/amdgpu_navi14_reg_init.c \
src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/amdgpu_nv.c \
src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/amdgpu_rlc.h
cvs rdiff -u -r1.4 -r1.5 \
src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/amdgpu_gmc_v7_0.c \
src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/amdgpu_gmc_v8_0.c
cvs rdiff -u -r1.7 -r1.8 \
src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/amdgpu_ih.c \
src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/amdgpu_ttm.c
cvs rdiff -u -r1.3 -r1.4 \
src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/amdgpu_ttm.h
cvs rdiff -u -r1.2 -r1.3 \
src/sys/external/bsd/drm2/dist/drm/amd/display/dc/basics/amdgpu_fixpt31_32.c
cvs rdiff -u -r1.2 -r1.3 \
src/sys/external/bsd/drm2/dist/drm/amd/display/dc/gpio/amdgpu_hw_ddc.c \
src/sys/external/bsd/drm2/dist/drm/amd/display/dc/gpio/amdgpu_hw_gpio.c \
src/sys/external/bsd/drm2/dist/drm/amd/display/dc/gpio/amdgpu_hw_hpd.c
cvs rdiff -u -r1.2 -r1.3 \
src/sys/external/bsd/drm2/dist/drm/amd/display/dc/hdcp/amdgpu_hdcp_msg.c
cvs rdiff -u -r1.2 -r1.3 \
src/sys/external/bsd/drm2/dist/drm/amd/display/modules/hdcp/amdgpu_hdcp1_execution.c
\
src/sys/external/bsd/drm2/dist/drm/amd/display/modules/hdcp/amdgpu_hdcp_ddc.c \
src/sys/external/bsd/drm2/dist/drm/amd/display/modules/hdcp/amdgpu_hdcp_log.c \
src/sys/external/bsd/drm2/dist/drm/amd/display/modules/hdcp/hdcp.h
cvs rdiff -u -r1.2 -r1.3 \
src/sys/external/bsd/drm2/dist/drm/amd/display/modules/inc/mod_hdcp.h
cvs rdiff -u -r1.2 -r1.3 \
src/sys/external/bsd/drm2/dist/drm/amd/powerplay/amdgpu_navi10_ppt.c
cvs rdiff -u -r1.2 -r1.3 \
src/sys/external/bsd/drm2/dist/drm/amd/powerplay/smumgr/amdgpu_fiji_smumgr.c \
src/sys/external/bsd/drm2/dist/drm/amd/powerplay/smumgr/amdgpu_iceland_smumgr.c
cvs rdiff -u -r1.13 -r1.14 \
src/sys/external/bsd/drm2/include/linux/dma-fence.h
cvs rdiff -u -r1.4 -r1.5 src/sys/external/bsd/drm2/include/linux/hash.h
cvs rdiff -u -r1.5 -r1.6 src/sys/external/bsd/drm2/include/linux/hashtable.h
cvs rdiff -u -r1.1 -r1.2 \
src/sys/external/bsd/drm2/include/uapi/linux/kfd_ioctl.h
cvs rdiff -u -r1.18 -r1.19 src/sys/external/bsd/drm2/linux/linux_dma_fence.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/external/bsd/common/include/linux/printk.h
diff -u src/sys/external/bsd/common/include/linux/printk.h:1.11 src/sys/external/bsd/common/include/linux/printk.h:1.12
--- src/sys/external/bsd/common/include/linux/printk.h:1.11 Sun Dec 19 11:38:37 2021
+++ src/sys/external/bsd/common/include/linux/printk.h Sun Dec 19 12:02:38 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: printk.h,v 1.11 2021/12/19 11:38:37 riastradh Exp $ */
+/* $NetBSD: printk.h,v 1.12 2021/12/19 12:02:38 riastradh Exp $ */
/*-
* Copyright (c) 2013 The NetBSD Foundation, Inc.
@@ -58,6 +58,8 @@
#define KERN_DEBUG "kern debug: "
#define KERN_CONT ""
+#define printk_ratelimit() 0 /* XXX */
+
struct va_format {
const char *fmt;
va_list *va;
Index: src/sys/external/bsd/drm2/amdgpu/amdgpu_module.c
diff -u src/sys/external/bsd/drm2/amdgpu/amdgpu_module.c:1.6 src/sys/external/bsd/drm2/amdgpu/amdgpu_module.c:1.7
--- src/sys/external/bsd/drm2/amdgpu/amdgpu_module.c:1.6 Sun Dec 19 12:01:48 2021
+++ src/sys/external/bsd/drm2/amdgpu/amdgpu_module.c Sun Dec 19 12:02:38 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: amdgpu_module.c,v 1.6 2021/12/19 12:01:48 riastradh Exp $ */
+/* $NetBSD: amdgpu_module.c,v 1.7 2021/12/19 12:02:38 riastradh Exp $ */
/*-
* Copyright (c) 2018 The NetBSD Foundation, Inc.
@@ -30,7 +30,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: amdgpu_module.c,v 1.6 2021/12/19 12:01:48 riastradh Exp $");
+__KERNEL_RCSID(0, "$NetBSD: amdgpu_module.c,v 1.7 2021/12/19 12:02:38 riastradh Exp $");
#include <sys/types.h>
#include <sys/module.h>
@@ -43,6 +43,7 @@ __KERNEL_RCSID(0, "$NetBSD: amdgpu_modul
#include <drm/drm_drv.h>
#include <drm/drm_sysctl.h>
+#include <linux/idr.h>
#include <linux/mutex.h>
#include "amdgpu.h"
@@ -59,6 +60,9 @@ MODULE(MODULE_CLASS_DRIVER, amdgpu, "drm
extern struct drm_driver *const amdgpu_drm_driver;
extern struct amdgpu_mgpu_info mgpu_info;
+/* XXX Kludge to replace DEFINE_IDA in amdgpu_ids.c. */
+extern struct ida amdgpu_pasid_ida;
+
struct drm_sysctl_def amdgpu_def = DRM_SYSCTL_INIT();
static int
@@ -74,6 +78,7 @@ amdgpu_init(void)
amdgpu_drm_driver->driver_features |= DRIVER_MODESET;
linux_mutex_init(&mgpu_info.mutex);
+ ida_init(&amdgpu_pasid_ida);
#if notyet /* XXX amdgpu acpi */
amdgpu_register_atpx_handler();
@@ -108,6 +113,7 @@ amdgpu_fini(void)
amdgpu_unregister_atpx_handler();
#endif
+ ida_destroy(&amdgpu_pasid_ida);
linux_mutex_destroy(&mgpu_info.mutex);
}
Index: src/sys/external/bsd/drm2/amdgpu/files.amdgpu
diff -u src/sys/external/bsd/drm2/amdgpu/files.amdgpu:1.20 src/sys/external/bsd/drm2/amdgpu/files.amdgpu:1.21
--- src/sys/external/bsd/drm2/amdgpu/files.amdgpu:1.20 Sun Dec 19 12:01:30 2021
+++ src/sys/external/bsd/drm2/amdgpu/files.amdgpu Sun Dec 19 12:02:38 2021
@@ -1,4 +1,4 @@
-# $NetBSD: files.amdgpu,v 1.20 2021/12/19 12:01:30 riastradh Exp $
+# $NetBSD: files.amdgpu,v 1.21 2021/12/19 12:02:38 riastradh Exp $
version 20180827
@@ -49,6 +49,10 @@ makeoptions amdgpu "CWARNFLAGS.amdgpu_ar
# -Wtype-limits raises warnings about code that is careful to avoid
# overflow in arithmetic, which is the opposite of helpful. &@!#*
makeoptions amdgpu "CWARNFLAGS.amdgpu_bo_list.c"+="-Wno-type-limits"
+makeoptions amdgpu "CWARNFLAGS.amdgpu_hw_ddc.c"+="-Wno-type-limits"
+makeoptions amdgpu "CWARNFLAGS.amdgpu_hw_generic.c"+="-Wno-type-limits"
+makeoptions amdgpu "CWARNFLAGS.amdgpu_hw_hpd.c"+="-Wno-type-limits"
+makeoptions amdgpu "CWARNFLAGS.amdgpu_navi10_ppt.c"+="-Wno-type-limits"
ifdef amd64
makeoptions amdgpu "COPTS.amdgpu_dcn20_resource.c"+="-mhard-float -msse -msse2"
@@ -63,6 +67,8 @@ makeoptions amdgpu "COPTS.amdgpu_display
makeoptions amdgpu "COPTS.amdgpu_display_rq_dlg_calc_20.c"+="-mhard-float -msse -msse2"
makeoptions amdgpu "COPTS.amdgpu_display_rq_dlg_calc_20v2.c"+="-mhard-float -msse -msse2"
makeoptions amdgpu "COPTS.amdgpu_display_rq_dlg_calc_21.c"+="-mhard-float -msse -msse2"
+makeoptions amdgpu "COPTS.amdgpu_dml1_display_rq_dlg_calc.c"+="-mhard-float -msse -msse2"
+makeoptions amdgpu "COPTS.amdgpu_dml_common_defs.c"+="-mhard-float -msse -msse2"
endif
# Local additions.
Index: src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/amdgpu.h
diff -u src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/amdgpu.h:1.6 src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/amdgpu.h:1.7
--- src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/amdgpu.h:1.6 Sun Dec 19 11:35:06 2021
+++ src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/amdgpu.h Sun Dec 19 12:02:39 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: amdgpu.h,v 1.6 2021/12/19 11:35:06 riastradh Exp $ */
+/* $NetBSD: amdgpu.h,v 1.7 2021/12/19 12:02:39 riastradh Exp $ */
/*
* Copyright 2008 Advanced Micro Devices, Inc.
@@ -953,7 +953,7 @@ struct amdgpu_device {
atomic64_t gart_pin_size;
/* soc15 register offset based on ip, instance and segment */
- uint32_t *reg_offset[MAX_HWIP][HWIP_MAX_INSTANCE];
+ const uint32_t *reg_offset[MAX_HWIP][HWIP_MAX_INSTANCE];
/* delayed work_func for deferring clockgating during resume */
struct delayed_work delayed_init_work;
Index: src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/amdgpu_cs.c
diff -u src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/amdgpu_cs.c:1.6 src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/amdgpu_cs.c:1.7
--- src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/amdgpu_cs.c:1.6 Sun Dec 19 10:59:01 2021
+++ src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/amdgpu_cs.c Sun Dec 19 12:02:39 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: amdgpu_cs.c,v 1.6 2021/12/19 10:59:01 riastradh Exp $ */
+/* $NetBSD: amdgpu_cs.c,v 1.7 2021/12/19 12:02:39 riastradh Exp $ */
/*
* Copyright 2008 Jerome Glisse.
@@ -28,7 +28,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: amdgpu_cs.c,v 1.6 2021/12/19 10:59:01 riastradh Exp $");
+__KERNEL_RCSID(0, "$NetBSD: amdgpu_cs.c,v 1.7 2021/12/19 12:02:39 riastradh Exp $");
#include <linux/file.h>
#include <linux/pagemap.h>
@@ -479,16 +479,19 @@ static int amdgpu_cs_list_validate(struc
list_for_each_entry(lobj, validated, tv.head) {
struct amdgpu_bo *bo = ttm_to_amdgpu_bo(lobj->tv.bo);
+#ifdef __NetBSD__
+ struct vmspace *usermm;
+#else
struct mm_struct *usermm;
+#endif
usermm = amdgpu_ttm_tt_get_usermm(bo->tbo.ttm);
-#ifdef __NetBSD__ /* XXX amdgpu userptr */
- if (usermm)
- return -EPERM;
+#ifdef __NetBSD__
+ if (usermm && usermm != curproc->p_vmspace)
#else
if (usermm && usermm != current->mm)
- return -EPERM;
#endif
+ return -EPERM;
if (amdgpu_ttm_tt_is_userptr(bo->tbo.ttm) &&
lobj->user_invalidated && lobj->user_pages) {
Index: src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/amdgpu_bo_list.c
diff -u src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/amdgpu_bo_list.c:1.8 src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/amdgpu_bo_list.c:1.9
--- src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/amdgpu_bo_list.c:1.8 Sun Dec 19 10:59:01 2021
+++ src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/amdgpu_bo_list.c Sun Dec 19 12:02:39 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: amdgpu_bo_list.c,v 1.8 2021/12/19 10:59:01 riastradh Exp $ */
+/* $NetBSD: amdgpu_bo_list.c,v 1.9 2021/12/19 12:02:39 riastradh Exp $ */
/*
* Copyright 2015 Advanced Micro Devices, Inc.
@@ -31,7 +31,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: amdgpu_bo_list.c,v 1.8 2021/12/19 10:59:01 riastradh Exp $");
+__KERNEL_RCSID(0, "$NetBSD: amdgpu_bo_list.c,v 1.9 2021/12/19 12:02:39 riastradh Exp $");
#include <linux/uaccess.h>
@@ -100,7 +100,11 @@ int amdgpu_bo_list_create(struct amdgpu_
struct amdgpu_bo_list_entry *entry;
struct drm_gem_object *gobj;
struct amdgpu_bo *bo;
+#ifdef __NetBSD__
+ struct vmspace *usermm;
+#else
struct mm_struct *usermm;
+#endif
gobj = drm_gem_object_lookup(filp, info[i].bo_handle);
if (!gobj) {
Index: src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/amdgpu_gem.c
diff -u src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/amdgpu_gem.c:1.8 src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/amdgpu_gem.c:1.9
--- src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/amdgpu_gem.c:1.8 Sun Dec 19 09:59:38 2021
+++ src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/amdgpu_gem.c Sun Dec 19 12:02:39 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: amdgpu_gem.c,v 1.8 2021/12/19 09:59:38 riastradh Exp $ */
+/* $NetBSD: amdgpu_gem.c,v 1.9 2021/12/19 12:02:39 riastradh Exp $ */
/*
* Copyright 2008 Advanced Micro Devices, Inc.
@@ -28,7 +28,7 @@
* Jerome Glisse
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: amdgpu_gem.c,v 1.8 2021/12/19 09:59:38 riastradh Exp $");
+__KERNEL_RCSID(0, "$NetBSD: amdgpu_gem.c,v 1.9 2021/12/19 12:02:39 riastradh Exp $");
#include <linux/ktime.h>
#include <linux/module.h>
@@ -133,11 +133,19 @@ int amdgpu_gem_object_open(struct drm_ge
struct amdgpu_fpriv *fpriv = file_priv->driver_priv;
struct amdgpu_vm *vm = &fpriv->vm;
struct amdgpu_bo_va *bo_va;
+#ifdef __NetBSD__
+ struct vmspace *mm;
+#else
struct mm_struct *mm;
+#endif
int r;
mm = amdgpu_ttm_tt_get_usermm(abo->tbo.ttm);
+#ifdef __NetBSD__
+ if (mm && mm != curproc->p_vmspace)
+#else
if (mm && mm != current->mm)
+#endif
return -EPERM;
if (abo->flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID &&
@@ -593,17 +601,17 @@ int amdgpu_gem_va_ioctl(struct drm_devic
if (args->va_address < AMDGPU_VA_RESERVED_SIZE) {
dev_dbg(pci_dev_dev(dev->pdev),
- "va_address 0x%LX is in reserved area 0x%LX\n",
- args->va_address, AMDGPU_VA_RESERVED_SIZE);
+ "va_address 0x%"PRIX64" is in reserved area 0x%"PRIX64"\n",
+ args->va_address, (uint64_t)AMDGPU_VA_RESERVED_SIZE);
return -EINVAL;
}
if (args->va_address >= AMDGPU_GMC_HOLE_START &&
args->va_address < AMDGPU_GMC_HOLE_END) {
dev_dbg(pci_dev_dev(dev->pdev),
- "va_address 0x%LX is in VA hole 0x%LX-0x%LX\n",
- args->va_address, AMDGPU_GMC_HOLE_START,
- AMDGPU_GMC_HOLE_END);
+ "va_address 0x%"PRIX64" is in VA hole 0x%"PRIX64"-0x%"PRIX64"\n",
+ args->va_address, (uint64_t)AMDGPU_GMC_HOLE_START,
+ (uint64_t)AMDGPU_GMC_HOLE_END);
return -EINVAL;
}
Index: src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/amdgpu_fb.c
diff -u src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/amdgpu_fb.c:1.9 src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/amdgpu_fb.c:1.10
--- src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/amdgpu_fb.c:1.9 Sun Dec 19 10:46:43 2021
+++ src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/amdgpu_fb.c Sun Dec 19 12:02:39 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: amdgpu_fb.c,v 1.9 2021/12/19 10:46:43 riastradh Exp $ */
+/* $NetBSD: amdgpu_fb.c,v 1.10 2021/12/19 12:02:39 riastradh Exp $ */
/*
* Copyright © 2007 David Airlie
@@ -27,7 +27,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: amdgpu_fb.c,v 1.9 2021/12/19 10:46:43 riastradh Exp $");
+__KERNEL_RCSID(0, "$NetBSD: amdgpu_fb.c,v 1.10 2021/12/19 12:02:39 riastradh Exp $");
#include <linux/module.h>
#include <linux/pm_runtime.h>
@@ -57,6 +57,8 @@ __KERNEL_RCSID(0, "$NetBSD: amdgpu_fb.c,
the helper contains a pointer to amdgpu framebuffer baseclass.
*/
+#ifndef __NetBSD__
+
static int
amdgpufb_open(struct fb_info *info, int user)
{
@@ -80,7 +82,6 @@ amdgpufb_release(struct fb_info *info, i
return 0;
}
-#ifndef __NetBSD__
static const struct fb_ops amdgpufb_ops = {
.owner = THIS_MODULE,
DRM_FB_HELPER_DEFAULT_OPS,
@@ -90,6 +91,7 @@ static const struct fb_ops amdgpufb_ops
.fb_copyarea = drm_fb_helper_cfb_copyarea,
.fb_imageblit = drm_fb_helper_cfb_imageblit,
};
+
#endif
@@ -213,17 +215,13 @@ static int amdgpufb_create(struct drm_fb
{
struct amdgpu_fbdev *rfbdev = (struct amdgpu_fbdev *)helper;
struct amdgpu_device *adev = rfbdev->adev;
-#ifndef __NetBSD__
struct fb_info *info;
-#endif
struct drm_framebuffer *fb = NULL;
struct drm_mode_fb_cmd2 mode_cmd;
struct drm_gem_object *gobj = NULL;
struct amdgpu_bo *abo = NULL;
int ret;
-#ifndef __NetBSD__
unsigned long tmp;
-#endif
mode_cmd.width = sizes->surface_width;
mode_cmd.height = sizes->surface_height;
@@ -242,53 +240,48 @@ static int amdgpufb_create(struct drm_fb
abo = gem_to_amdgpu_bo(gobj);
-#ifdef __NetBSD__
- ret = amdgpu_framebuffer_init(adev->ddev, &rfbdev->rfb, &mode_cmd, gobj);
+#ifndef __NetBSD__
+ /* okay we have an object now allocate the framebuffer */
+ info = drm_fb_helper_alloc_fbi(helper);
+ if (IS_ERR(info)) {
+ ret = PTR_ERR(info);
+ goto out;
+ }
+#endif
+
+ ret = amdgpu_display_framebuffer_init(adev->ddev, &rfbdev->rfb,
+ &mode_cmd, gobj);
if (ret) {
DRM_ERROR("failed to initialize framebuffer %d\n", ret);
- goto out_unref;
+ goto out;
}
- (void)memset(rbo->kptr, 0, amdgpu_bo_size(rbo));
+ fb = &rfbdev->rfb.base;
+
+ /* setup helper */
+ rfbdev->helper.fb = fb;
+#ifdef __NetBSD__
{
static const struct amdgpufb_attach_args zero_afa;
struct amdgpufb_attach_args afa = zero_afa;
+ __USE(tmp);
+ __USE(info);
+
afa.afa_fb_helper = helper;
afa.afa_fb_sizes = *sizes;
- afa.afa_fb_ptr = rbo->kptr;
+ afa.afa_fb_ptr = amdgpu_bo_kptr(abo);
afa.afa_fb_linebytes = mode_cmd.pitches[0];
helper->fbdev = config_found(adev->ddev->dev, &afa, NULL,
CFARGS(.iattr = "amdgpufbbus"));
if (helper->fbdev == NULL) {
DRM_ERROR("failed to attach amdgpufb\n");
- goto out_unref;
+ goto out;
}
}
- fb = &rfbdev->rfb.base;
- rfbdev->helper.fb = fb;
#else /* __NetBSD__ */
- /* okay we have an object now allocate the framebuffer */
- info = drm_fb_helper_alloc_fbi(helper);
- if (IS_ERR(info)) {
- ret = PTR_ERR(info);
- goto out;
- }
-
- ret = amdgpu_display_framebuffer_init(adev->ddev, &rfbdev->rfb,
- &mode_cmd, gobj);
- if (ret) {
- DRM_ERROR("failed to initialize framebuffer %d\n", ret);
- goto out;
- }
-
- fb = &rfbdev->rfb.base;
-
- /* setup helper */
- rfbdev->helper.fb = fb;
-
info->fbops = &amdgpufb_ops;
tmp = amdgpu_bo_gpu_offset(abo) - adev->gmc.vram_start;
Index: src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/amdgpu_fence.c
diff -u src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/amdgpu_fence.c:1.9 src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/amdgpu_fence.c:1.10
--- src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/amdgpu_fence.c:1.9 Sun Dec 19 11:55:47 2021
+++ src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/amdgpu_fence.c Sun Dec 19 12:02:39 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: amdgpu_fence.c,v 1.9 2021/12/19 11:55:47 riastradh Exp $ */
+/* $NetBSD: amdgpu_fence.c,v 1.10 2021/12/19 12:02:39 riastradh Exp $ */
/*
* Copyright 2009 Jerome Glisse.
@@ -31,7 +31,7 @@
* Dave Airlie
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: amdgpu_fence.c,v 1.9 2021/12/19 11:55:47 riastradh Exp $");
+__KERNEL_RCSID(0, "$NetBSD: amdgpu_fence.c,v 1.10 2021/12/19 12:02:39 riastradh Exp $");
#include <linux/seq_file.h>
#include <linux/atomic.h>
@@ -422,7 +422,7 @@ int amdgpu_fence_driver_start_ring(struc
ring->fence_drv.initialized = true;
DRM_DEV_DEBUG(adev->dev, "fence driver on ring %s use gpu addr "
- "0x%016"RPIx64", cpu addr 0x%p\n", ring->name,
+ "0x%016"PRIx64", cpu addr 0x%p\n", ring->name,
ring->fence_drv.gpu_addr, ring->fence_drv.cpu_addr);
return 0;
}
@@ -668,6 +668,7 @@ static void amdgpu_fence_free(struct rcu
{
struct dma_fence *f = container_of(rcu, struct dma_fence, rcu);
struct amdgpu_fence *fence = to_amdgpu_fence(f);
+ dma_fence_destroy(f);
kmem_cache_free(amdgpu_fence_slab, fence);
}
Index: src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/amdgpu_gart.c
diff -u src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/amdgpu_gart.c:1.5 src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/amdgpu_gart.c:1.6
--- src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/amdgpu_gart.c:1.5 Sat Dec 18 23:44:58 2021
+++ src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/amdgpu_gart.c Sun Dec 19 12:02:39 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: amdgpu_gart.c,v 1.5 2021/12/18 23:44:58 riastradh Exp $ */
+/* $NetBSD: amdgpu_gart.c,v 1.6 2021/12/19 12:02:39 riastradh Exp $ */
/*
* Copyright 2008 Advanced Micro Devices, Inc.
@@ -29,7 +29,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: amdgpu_gart.c,v 1.5 2021/12/18 23:44:58 riastradh Exp $");
+__KERNEL_RCSID(0, "$NetBSD: amdgpu_gart.c,v 1.6 2021/12/19 12:02:39 riastradh Exp $");
#include <linux/pci.h>
#include <linux/vmalloc.h>
@@ -273,6 +273,7 @@ static void
amdgpu_gart_post_update(struct amdgpu_device *adev, unsigned gpu_pgstart,
unsigned gpu_npages)
{
+ unsigned i;
if (adev->gart.ag_table_map != NULL) {
const unsigned entsize =
@@ -282,8 +283,10 @@ amdgpu_gart_post_update(struct amdgpu_de
gpu_pgstart*entsize, gpu_npages*entsize,
BUS_DMASYNC_PREWRITE);
}
- mb();
- amdgpu_gart_flush_gpu_tlb(adev, 0);
+ mb(); /* XXX why is bus_dmamap_sync not enough? */
+ amdgpu_asic_flush_hdp(adev, NULL);
+ for (i = 0; i < adev->num_vmhubs; i++)
+ amdgpu_gmc_flush_gpu_tlb(adev, 0, i, 0);
}
#endif
@@ -295,7 +298,7 @@ void
amdgpu_gart_unbind(struct amdgpu_device *adev, uint64_t gpu_start,
unsigned npages)
{
- const unsigned gpu_per_cpu = (PAGE_SIZE / AMDGPU_GPU_PAGE_SIZE);
+ const unsigned gpu_per_cpu = AMDGPU_GPU_PAGES_IN_CPU_PAGE;
const unsigned gpu_npages = (npages * gpu_per_cpu);
const uint64_t gpu_pgstart = (gpu_start / AMDGPU_GPU_PAGE_SIZE);
const uint64_t pgstart = (gpu_pgstart / gpu_per_cpu);
@@ -313,17 +316,16 @@ amdgpu_gart_unbind(struct amdgpu_device
amdgpu_gart_pre_update(adev, gpu_pgstart, gpu_npages);
for (pgno = 0; pgno < npages; pgno++) {
- if (adev->gart.pages[pgstart + pgno] == NULL)
- continue;
+#ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS
adev->gart.pages[pgstart + pgno] = NULL;
- adev->gart.pages_addr[pgstart + pgno] = adev->dummy_page.addr;
+#endif
if (adev->gart.ptr == NULL)
continue;
for (gpu_pgno = 0; gpu_pgno < gpu_per_cpu; gpu_pgno++) {
- amdgpu_gart_set_pte_pde(adev, adev->gart.ptr,
+ amdgpu_gmc_set_pte_pde(adev, adev->gart.ptr,
gpu_pgstart + gpu_per_cpu*pgno + gpu_pgno,
- adev->dummy_page.addr, flags);
+ adev->dummy_page_addr, flags);
}
}
amdgpu_gart_post_update(adev, gpu_pgstart, gpu_npages);
@@ -422,7 +424,7 @@ int
amdgpu_gart_bind(struct amdgpu_device *adev, uint64_t gpu_start,
unsigned npages, struct page **pages, bus_dmamap_t dmamap, uint32_t flags)
{
- const unsigned gpu_per_cpu = (PAGE_SIZE / AMDGPU_GPU_PAGE_SIZE);
+ const unsigned gpu_per_cpu = AMDGPU_GPU_PAGES_IN_CPU_PAGE;
const unsigned gpu_npages = (npages * gpu_per_cpu);
const uint64_t gpu_pgstart = (gpu_start / AMDGPU_GPU_PAGE_SIZE);
const uint64_t pgstart = (gpu_pgstart / gpu_per_cpu);
@@ -443,14 +445,15 @@ amdgpu_gart_bind(struct amdgpu_device *a
const bus_addr_t addr = dmamap->dm_segs[pgno].ds_addr;
KASSERT(dmamap->dm_segs[pgno].ds_len == PAGE_SIZE);
- adev->gart.pages[pgstart + pgno] = pages[pgno];
- adev->gart.pages_addr[pgstart + pgno] = addr;
+#ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS
+ adev->gart.pages[pgstart + pgno] = NULL;
+#endif
if (adev->gart.ptr == NULL)
continue;
for (gpu_pgno = 0; gpu_pgno < gpu_per_cpu; gpu_pgno++) {
- amdgpu_gart_set_pte_pde(adev, adev->gart.ptr,
+ amdgpu_gmc_set_pte_pde(adev, adev->gart.ptr,
gpu_pgstart + gpu_per_cpu*pgno + gpu_pgno,
addr + gpu_pgno*AMDGPU_GPU_PAGE_SIZE, flags);
}
Index: src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/amdgpu_gfx_v7_0.c
diff -u src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/amdgpu_gfx_v7_0.c:1.5 src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/amdgpu_gfx_v7_0.c:1.6
--- src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/amdgpu_gfx_v7_0.c:1.5 Sun Dec 19 09:59:46 2021
+++ src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/amdgpu_gfx_v7_0.c Sun Dec 19 12:02:39 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: amdgpu_gfx_v7_0.c,v 1.5 2021/12/19 09:59:46 riastradh Exp $ */
+/* $NetBSD: amdgpu_gfx_v7_0.c,v 1.6 2021/12/19 12:02:39 riastradh Exp $ */
/*
* Copyright 2014 Advanced Micro Devices, Inc.
@@ -24,7 +24,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: amdgpu_gfx_v7_0.c,v 1.5 2021/12/19 09:59:46 riastradh Exp $");
+__KERNEL_RCSID(0, "$NetBSD: amdgpu_gfx_v7_0.c,v 1.6 2021/12/19 12:02:39 riastradh Exp $");
#include <linux/firmware.h>
#include <linux/module.h>
@@ -56,6 +56,8 @@ __KERNEL_RCSID(0, "$NetBSD: amdgpu_gfx_v
#include "oss/oss_2_0_d.h"
#include "oss/oss_2_0_sh_mask.h"
+#include <linux/nbsd-namespace.h>
+
#define NUM_SIMD_PER_CU 0x4 /* missing from the gfx_7 IP headers */
#define GFX7_NUM_GFX_RINGS 1
@@ -4541,11 +4543,11 @@ static int gfx_v7_0_sw_fini(void *handle
gfx_v7_0_mec_fini(adev);
amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj,
&adev->gfx.rlc.clear_state_gpu_addr,
- (void **)&adev->gfx.rlc.cs_ptr);
+ (void **)__UNVOLATILE(&adev->gfx.rlc.cs_ptr));
if (adev->gfx.rlc.cp_table_size) {
amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj,
&adev->gfx.rlc.cp_table_gpu_addr,
- (void **)&adev->gfx.rlc.cp_table_ptr);
+ (void **)__UNVOLATILE(&adev->gfx.rlc.cp_table_ptr));
}
gfx_v7_0_free_microcode(adev);
Index: src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/amdgpu_gfx_v8_0.c
diff -u src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/amdgpu_gfx_v8_0.c:1.5 src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/amdgpu_gfx_v8_0.c:1.6
--- src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/amdgpu_gfx_v8_0.c:1.5 Sat Dec 18 23:44:58 2021
+++ src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/amdgpu_gfx_v8_0.c Sun Dec 19 12:02:39 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: amdgpu_gfx_v8_0.c,v 1.5 2021/12/18 23:44:58 riastradh Exp $ */
+/* $NetBSD: amdgpu_gfx_v8_0.c,v 1.6 2021/12/19 12:02:39 riastradh Exp $ */
/*
* Copyright 2014 Advanced Micro Devices, Inc.
@@ -24,7 +24,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: amdgpu_gfx_v8_0.c,v 1.5 2021/12/18 23:44:58 riastradh Exp $");
+__KERNEL_RCSID(0, "$NetBSD: amdgpu_gfx_v8_0.c,v 1.6 2021/12/19 12:02:39 riastradh Exp $");
#include <linux/delay.h>
#include <linux/kernel.h>
@@ -2084,12 +2084,12 @@ static int gfx_v8_0_sw_fini(void *handle
amdgpu_gfx_rlc_fini(adev);
amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj,
&adev->gfx.rlc.clear_state_gpu_addr,
- (void **)&adev->gfx.rlc.cs_ptr);
+ (void **)__UNVOLATILE(&adev->gfx.rlc.cs_ptr));
if ((adev->asic_type == CHIP_CARRIZO) ||
(adev->asic_type == CHIP_STONEY)) {
amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj,
&adev->gfx.rlc.cp_table_gpu_addr,
- (void **)&adev->gfx.rlc.cp_table_ptr);
+ (void **)__UNVOLATILE(&adev->gfx.rlc.cp_table_ptr));
}
gfx_v8_0_free_microcode(adev);
Index: src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/amdgpu_irq.c
diff -u src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/amdgpu_irq.c:1.5 src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/amdgpu_irq.c:1.6
--- src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/amdgpu_irq.c:1.5 Sat Dec 18 23:44:58 2021
+++ src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/amdgpu_irq.c Sun Dec 19 12:02:39 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: amdgpu_irq.c,v 1.5 2021/12/18 23:44:58 riastradh Exp $ */
+/* $NetBSD: amdgpu_irq.c,v 1.6 2021/12/19 12:02:39 riastradh Exp $ */
/*
* Copyright 2008 Advanced Micro Devices, Inc.
@@ -45,7 +45,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: amdgpu_irq.c,v 1.5 2021/12/18 23:44:58 riastradh Exp $");
+__KERNEL_RCSID(0, "$NetBSD: amdgpu_irq.c,v 1.6 2021/12/19 12:02:39 riastradh Exp $");
#include <linux/irq.h>
#include <linux/pci.h>
@@ -253,6 +253,7 @@ int amdgpu_irq_init(struct amdgpu_device
adev->irq.msi_enabled = false;
if (amdgpu_msi_ok(adev)) {
+#ifndef __NetBSD__ /* XXX amdgpu msix */
int nvec = pci_msix_vec_count(adev->pdev);
unsigned int flags;
@@ -267,6 +268,7 @@ int amdgpu_irq_init(struct amdgpu_device
adev->irq.msi_enabled = true;
dev_dbg(adev->dev, "amdgpu: using MSI/MSI-X.\n");
}
+#endif
}
if (!amdgpu_device_has_dc_support(adev)) {
@@ -322,8 +324,10 @@ void amdgpu_irq_fini(struct amdgpu_devic
if (adev->irq.installed) {
drm_irq_uninstall(adev->ddev);
adev->irq.installed = false;
+#ifndef __NetBSD__ /* XXX amdgpu msix */
if (adev->irq.msi_enabled)
pci_free_irq_vectors(adev->pdev);
+#endif
if (!amdgpu_device_has_dc_support(adev))
flush_work(&adev->hotplug_work);
}
@@ -422,7 +426,7 @@ void amdgpu_irq_dispatch(struct amdgpu_d
bool handled = false;
int r;
- entry.iv_entry = (const uint32_t *)&ih->ring[ring_index];
+ entry.iv_entry = (const uint32_t *)__UNVOLATILE(&ih->ring[ring_index]);
amdgpu_ih_decode_iv(adev, &entry);
trace_amdgpu_iv(ih - &adev->irq.ih, &entry);
@@ -436,8 +440,10 @@ void amdgpu_irq_dispatch(struct amdgpu_d
} else if (src_id >= AMDGPU_MAX_IRQ_SRC_ID) {
DRM_DEBUG("Invalid src_id in IV: %d\n", src_id);
+#ifndef __NetBSD__ /* XXX amdgpu irq */
} else if (adev->irq.virq[src_id]) {
generic_handle_irq(irq_find_mapping(adev->irq.domain, src_id));
+#endif
} else if (!adev->irq.client[client_id].sources) {
DRM_DEBUG("Unregistered interrupt client_id: %d src_id: %d\n",
@@ -604,6 +610,8 @@ bool amdgpu_irq_enabled(struct amdgpu_de
return !!atomic_read(&src->enabled_types[type]);
}
+#ifndef __NetBSD__ /* XXX amdgpu irq */
+
/* XXX: Generic IRQ handling */
static void amdgpu_irq_mask(struct irq_data *irqd)
{
@@ -709,3 +717,5 @@ unsigned amdgpu_irq_create_mapping(struc
return adev->irq.virq[src_id];
}
+
+#endif
Index: src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/amdgpu_kms.c
diff -u src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/amdgpu_kms.c:1.5 src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/amdgpu_kms.c:1.6
--- src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/amdgpu_kms.c:1.5 Sat Dec 18 23:44:58 2021
+++ src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/amdgpu_kms.c Sun Dec 19 12:02:39 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: amdgpu_kms.c,v 1.5 2021/12/18 23:44:58 riastradh Exp $ */
+/* $NetBSD: amdgpu_kms.c,v 1.6 2021/12/19 12:02:39 riastradh Exp $ */
/*
* Copyright 2008 Advanced Micro Devices, Inc.
@@ -29,7 +29,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: amdgpu_kms.c,v 1.5 2021/12/18 23:44:58 riastradh Exp $");
+__KERNEL_RCSID(0, "$NetBSD: amdgpu_kms.c,v 1.6 2021/12/19 12:02:39 riastradh Exp $");
#include "amdgpu.h"
#include <drm/drm_debugfs.h>
@@ -205,7 +205,7 @@ int amdgpu_driver_load_kms(struct drm_de
out:
if (r) {
/* balance pm_runtime_get_sync in amdgpu_driver_unload_kms */
- if (adev->rmmio && adev->runpm)
+ if (adev->rmmio_size && adev->runpm)
pm_runtime_put_noidle(dev->dev);
amdgpu_driver_unload_kms(dev);
}
Index: src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/amdgpu_gart.h
diff -u src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/amdgpu_gart.h:1.2 src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/amdgpu_gart.h:1.3
--- src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/amdgpu_gart.h:1.2 Sat Dec 18 23:44:58 2021
+++ src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/amdgpu_gart.h Sun Dec 19 12:02:39 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: amdgpu_gart.h,v 1.2 2021/12/18 23:44:58 riastradh Exp $ */
+/* $NetBSD: amdgpu_gart.h,v 1.3 2021/12/19 12:02:39 riastradh Exp $ */
/*
* Copyright 2017 Advanced Micro Devices, Inc.
@@ -42,6 +42,10 @@ struct amdgpu_bo;
#define AMDGPU_GPU_PAGES_IN_CPU_PAGE (PAGE_SIZE / AMDGPU_GPU_PAGE_SIZE)
struct amdgpu_gart {
+#ifdef __NetBSD__
+ bus_dma_segment_t ag_table_seg;
+ bus_dmamap_t ag_table_map;
+#endif
struct amdgpu_bo *bo;
/* CPU kmapped address of gart table */
void *ptr;
Index: src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/amdgpu_gfx_v10_0.c
diff -u src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/amdgpu_gfx_v10_0.c:1.2 src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/amdgpu_gfx_v10_0.c:1.3
--- src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/amdgpu_gfx_v10_0.c:1.2 Sat Dec 18 23:44:58 2021
+++ src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/amdgpu_gfx_v10_0.c Sun Dec 19 12:02:39 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: amdgpu_gfx_v10_0.c,v 1.2 2021/12/18 23:44:58 riastradh Exp $ */
+/* $NetBSD: amdgpu_gfx_v10_0.c,v 1.3 2021/12/19 12:02:39 riastradh Exp $ */
/*
* Copyright 2019 Advanced Micro Devices, Inc.
@@ -24,7 +24,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: amdgpu_gfx_v10_0.c,v 1.2 2021/12/18 23:44:58 riastradh Exp $");
+__KERNEL_RCSID(0, "$NetBSD: amdgpu_gfx_v10_0.c,v 1.3 2021/12/19 12:02:39 riastradh Exp $");
#include <linux/delay.h>
#include <linux/kernel.h>
@@ -52,6 +52,8 @@ __KERNEL_RCSID(0, "$NetBSD: amdgpu_gfx_v
#include "gfx_v10_0.h"
#include "nbio_v2_3.h"
+#include <linux/nbsd-namespace.h>
+
/**
* Navi10 has two graphic rings to share each graphic pipe.
* 1. Primary ring
@@ -608,15 +610,15 @@ static void gfx_v10_0_init_rlc_ext_micro
adev->gfx.rlc_srlc_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_cntl_ucode_ver);
adev->gfx.rlc_srlc_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_cntl_feature_ver);
adev->gfx.rlc.save_restore_list_cntl_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_cntl_size_bytes);
- adev->gfx.rlc.save_restore_list_cntl = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_cntl_offset_bytes);
+ adev->gfx.rlc.save_restore_list_cntl = (const u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_cntl_offset_bytes);
adev->gfx.rlc_srlg_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_gpm_ucode_ver);
adev->gfx.rlc_srlg_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_gpm_feature_ver);
adev->gfx.rlc.save_restore_list_gpm_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_gpm_size_bytes);
- adev->gfx.rlc.save_restore_list_gpm = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_gpm_offset_bytes);
+ adev->gfx.rlc.save_restore_list_gpm = (const u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_gpm_offset_bytes);
adev->gfx.rlc_srls_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_srm_ucode_ver);
adev->gfx.rlc_srls_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_srm_feature_ver);
adev->gfx.rlc.save_restore_list_srm_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_srm_size_bytes);
- adev->gfx.rlc.save_restore_list_srm = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_srm_offset_bytes);
+ adev->gfx.rlc.save_restore_list_srm = (const u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_srm_offset_bytes);
adev->gfx.rlc.reg_list_format_direct_reg_list_length =
le32_to_cpu(rlc_hdr->reg_list_format_direct_reg_list_length);
}
@@ -997,12 +999,12 @@ static void gfx_v10_0_rlc_fini(struct am
/* clear state block */
amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj,
&adev->gfx.rlc.clear_state_gpu_addr,
- (void **)&adev->gfx.rlc.cs_ptr);
+ (void **)__UNVOLATILE(&adev->gfx.rlc.cs_ptr));
/* jump table block */
amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj,
&adev->gfx.rlc.cp_table_gpu_addr,
- (void **)&adev->gfx.rlc.cp_table_ptr);
+ (void **)__UNVOLATILE(&adev->gfx.rlc.cp_table_ptr));
}
static int gfx_v10_0_rlc_init(struct amdgpu_device *adev)
@@ -1254,7 +1256,7 @@ static int gfx_v10_0_gfx_ring_init(struc
ring->doorbell_index = adev->doorbell_index.gfx_ring0 << 1;
else
ring->doorbell_index = adev->doorbell_index.gfx_ring1 << 1;
- sprintf(ring->name, "gfx_%d.%d.%d", ring->me, ring->pipe, ring->queue);
+ snprintf(ring->name, sizeof(ring->name), "gfx_%d.%d.%d", ring->me, ring->pipe, ring->queue);
irq_type = AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP + ring->pipe;
r = amdgpu_ring_init(adev, ring, 1024,
@@ -1283,7 +1285,7 @@ static int gfx_v10_0_compute_ring_init(s
ring->doorbell_index = (adev->doorbell_index.mec_ring0 + ring_id) << 1;
ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr
+ (ring_id * GFX10_MEC_HPD_SIZE);
- sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue);
+ snprintf(ring->name, sizeof(ring->name), "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue);
irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP
+ ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec)
@@ -2149,7 +2151,7 @@ static void gfx_v10_0_rlc_backdoor_autol
FIRMWARE_ID_SDMA0_UCODE, fw_data, fw_size);
gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
FIRMWARE_ID_SDMA0_JT,
- (uint32_t *)fw_data +
+ (const uint32_t *)fw_data +
sdma_hdr->jt_offset,
sdma_hdr->jt_size * 4);
} else if (i == 1) {
@@ -2157,7 +2159,7 @@ static void gfx_v10_0_rlc_backdoor_autol
FIRMWARE_ID_SDMA1_UCODE, fw_data, fw_size);
gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
FIRMWARE_ID_SDMA1_JT,
- (uint32_t *)fw_data +
+ (const uint32_t *)fw_data +
sdma_hdr->jt_offset,
sdma_hdr->jt_size * 4);
}
@@ -4321,7 +4323,7 @@ static u64 gfx_v10_0_ring_get_wptr_gfx(s
/* XXX check if swapping is necessary on BE */
if (ring->use_doorbell) {
- wptr = atomic64_read((atomic64_t *)&adev->wb.wb[ring->wptr_offs]);
+ wptr = atomic_load_relaxed(&adev->wb.wb[ring->wptr_offs]);
} else {
wptr = RREG32_SOC15(GC, 0, mmCP_RB0_WPTR);
wptr += (u64)RREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI) << 32;
@@ -4336,7 +4338,7 @@ static void gfx_v10_0_ring_set_wptr_gfx(
if (ring->use_doorbell) {
/* XXX check if swapping is necessary on BE */
- atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], ring->wptr);
+ atomic_store_relaxed(&adev->wb.wb[ring->wptr_offs], ring->wptr);
WDOORBELL64(ring->doorbell_index, ring->wptr);
} else {
WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr));
@@ -4355,7 +4357,7 @@ static u64 gfx_v10_0_ring_get_wptr_compu
/* XXX check if swapping is necessary on BE */
if (ring->use_doorbell)
- wptr = atomic64_read((atomic64_t *)&ring->adev->wb.wb[ring->wptr_offs]);
+ wptr = atomic_load_relaxed(&ring->adev->wb.wb[ring->wptr_offs]);
else
BUG();
return wptr;
@@ -4367,7 +4369,7 @@ static void gfx_v10_0_ring_set_wptr_comp
/* XXX check if swapping is necessary on BE */
if (ring->use_doorbell) {
- atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], ring->wptr);
+ atomic_store_relaxed(&adev->wb.wb[ring->wptr_offs], ring->wptr);
WDOORBELL64(ring->doorbell_index, ring->wptr);
} else {
BUG(); /* only DOORBELL method supported on gfx10 now */
Index: src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/amdgpu_gfx_v6_0.c
diff -u src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/amdgpu_gfx_v6_0.c:1.2 src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/amdgpu_gfx_v6_0.c:1.3
--- src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/amdgpu_gfx_v6_0.c:1.2 Sat Dec 18 23:44:58 2021
+++ src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/amdgpu_gfx_v6_0.c Sun Dec 19 12:02:39 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: amdgpu_gfx_v6_0.c,v 1.2 2021/12/18 23:44:58 riastradh Exp $ */
+/* $NetBSD: amdgpu_gfx_v6_0.c,v 1.3 2021/12/19 12:02:39 riastradh Exp $ */
/*
* Copyright 2015 Advanced Micro Devices, Inc.
@@ -23,7 +23,7 @@
*
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: amdgpu_gfx_v6_0.c,v 1.2 2021/12/18 23:44:58 riastradh Exp $");
+__KERNEL_RCSID(0, "$NetBSD: amdgpu_gfx_v6_0.c,v 1.3 2021/12/19 12:02:39 riastradh Exp $");
#include <linux/firmware.h>
#include <linux/module.h>
@@ -2410,7 +2410,7 @@ static int gfx_v6_0_rlc_init(struct amdg
AMDGPU_GEM_DOMAIN_VRAM,
&adev->gfx.rlc.clear_state_obj,
&adev->gfx.rlc.clear_state_gpu_addr,
- (void **)&adev->gfx.rlc.cs_ptr);
+ (void **)__UNVOLATILE(&adev->gfx.rlc.cs_ptr));
if (r) {
dev_warn(adev->dev, "(%d) create RLC c bo failed\n", r);
amdgpu_gfx_rlc_fini(adev);
@@ -3117,7 +3117,7 @@ static int gfx_v6_0_sw_init(void *handle
for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
ring = &adev->gfx.gfx_ring[i];
ring->ring_obj = NULL;
- sprintf(ring->name, "gfx");
+ snprintf(ring->name, sizeof(ring->name), "gfx");
r = amdgpu_ring_init(adev, ring, 1024,
&adev->gfx.eop_irq, AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP);
if (r)
@@ -3138,7 +3138,7 @@ static int gfx_v6_0_sw_init(void *handle
ring->me = 1;
ring->pipe = i;
ring->queue = i;
- sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue);
+ snprintf(ring->name, sizeof(ring->name), "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue);
irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP + ring->pipe;
r = amdgpu_ring_init(adev, ring, 1024,
&adev->gfx.eop_irq, irq_type);
Index: src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/amdgpu_gfx_v9_0.c
diff -u src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/amdgpu_gfx_v9_0.c:1.2 src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/amdgpu_gfx_v9_0.c:1.3
--- src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/amdgpu_gfx_v9_0.c:1.2 Sat Dec 18 23:44:58 2021
+++ src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/amdgpu_gfx_v9_0.c Sun Dec 19 12:02:39 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: amdgpu_gfx_v9_0.c,v 1.2 2021/12/18 23:44:58 riastradh Exp $ */
+/* $NetBSD: amdgpu_gfx_v9_0.c,v 1.3 2021/12/19 12:02:39 riastradh Exp $ */
/*
* Copyright 2016 Advanced Micro Devices, Inc.
@@ -24,7 +24,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: amdgpu_gfx_v9_0.c,v 1.2 2021/12/18 23:44:58 riastradh Exp $");
+__KERNEL_RCSID(0, "$NetBSD: amdgpu_gfx_v9_0.c,v 1.3 2021/12/19 12:02:39 riastradh Exp $");
#include <linux/delay.h>
#include <linux/kernel.h>
@@ -55,6 +55,8 @@ __KERNEL_RCSID(0, "$NetBSD: amdgpu_gfx_v
#include "gfx_v9_4.h"
+#include <linux/nbsd-namespace.h>
+
#define GFX9_NUM_GFX_RINGS 1
#define GFX9_MEC_HPD_SIZE 4096
#define RLCG_UCODE_LOADING_START_ADDRESS 0x00002000L
@@ -341,7 +343,7 @@ enum ta_ras_gfx_subblock {
};
struct ras_gfx_subblock {
- unsigned char *name;
+ const unsigned char *name;
int ta_subblock;
int hw_supported_error_type;
int sw_supported_error_type;
@@ -1093,15 +1095,15 @@ static void gfx_v9_0_init_rlc_ext_microc
adev->gfx.rlc_srlc_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_cntl_ucode_ver);
adev->gfx.rlc_srlc_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_cntl_feature_ver);
adev->gfx.rlc.save_restore_list_cntl_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_cntl_size_bytes);
- adev->gfx.rlc.save_restore_list_cntl = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_cntl_offset_bytes);
+ adev->gfx.rlc.save_restore_list_cntl = (const u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_cntl_offset_bytes);
adev->gfx.rlc_srlg_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_gpm_ucode_ver);
adev->gfx.rlc_srlg_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_gpm_feature_ver);
adev->gfx.rlc.save_restore_list_gpm_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_gpm_size_bytes);
- adev->gfx.rlc.save_restore_list_gpm = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_gpm_offset_bytes);
+ adev->gfx.rlc.save_restore_list_gpm = (const u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_gpm_offset_bytes);
adev->gfx.rlc_srls_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_srm_ucode_ver);
adev->gfx.rlc_srls_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_srm_feature_ver);
adev->gfx.rlc.save_restore_list_srm_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_srm_size_bytes);
- adev->gfx.rlc.save_restore_list_srm = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_srm_offset_bytes);
+ adev->gfx.rlc.save_restore_list_srm = (const u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_srm_offset_bytes);
adev->gfx.rlc.reg_list_format_direct_reg_list_length =
le32_to_cpu(rlc_hdr->reg_list_format_direct_reg_list_length);
}
@@ -2146,7 +2148,7 @@ static int gfx_v9_0_compute_ring_init(st
ring->doorbell_index = (adev->doorbell_index.mec_ring0 + ring_id) << 1;
ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr
+ (ring_id * GFX9_MEC_HPD_SIZE);
- sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue);
+ snprintf(ring->name, sizeof(ring->name), "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue);
irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP
+ ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec)
@@ -2242,9 +2244,9 @@ static int gfx_v9_0_sw_init(void *handle
ring = &adev->gfx.gfx_ring[i];
ring->ring_obj = NULL;
if (!i)
- sprintf(ring->name, "gfx");
+ snprintf(ring->name, sizeof(ring->name), "gfx");
else
- sprintf(ring->name, "gfx_%d", i);
+ snprintf(ring->name, sizeof(ring->name), "gfx_%d", i);
ring->use_doorbell = true;
ring->doorbell_index = adev->doorbell_index.gfx_ring0 << 1;
r = amdgpu_ring_init(adev, ring, 1024,
@@ -2319,7 +2321,7 @@ static int gfx_v9_0_sw_fini(void *handle
if (adev->asic_type == CHIP_RAVEN || adev->asic_type == CHIP_RENOIR) {
amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj,
&adev->gfx.rlc.cp_table_gpu_addr,
- (void **)&adev->gfx.rlc.cp_table_ptr);
+ (void **)__UNVOLATILE(&adev->gfx.rlc.cp_table_ptr));
}
gfx_v9_0_free_microcode(adev);
@@ -4853,7 +4855,7 @@ static u64 gfx_v9_0_ring_get_wptr_gfx(st
/* XXX check if swapping is necessary on BE */
if (ring->use_doorbell) {
- wptr = atomic64_read((atomic64_t *)&adev->wb.wb[ring->wptr_offs]);
+ wptr = atomic_load_relaxed(&adev->wb.wb[ring->wptr_offs]);
} else {
wptr = RREG32_SOC15(GC, 0, mmCP_RB0_WPTR);
wptr += (u64)RREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI) << 32;
@@ -4868,7 +4870,7 @@ static void gfx_v9_0_ring_set_wptr_gfx(s
if (ring->use_doorbell) {
/* XXX check if swapping is necessary on BE */
- atomic64_set((atomic64_t*)&adev->wb.wb[ring->wptr_offs], ring->wptr);
+ atomic_store_relaxed(&adev->wb.wb[ring->wptr_offs], ring->wptr);
WDOORBELL64(ring->doorbell_index, ring->wptr);
} else {
WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr));
@@ -5042,7 +5044,7 @@ static u64 gfx_v9_0_ring_get_wptr_comput
/* XXX check if swapping is necessary on BE */
if (ring->use_doorbell)
- wptr = atomic64_read((atomic64_t *)&ring->adev->wb.wb[ring->wptr_offs]);
+ wptr = atomic_load_relaxed(&ring->adev->wb.wb[ring->wptr_offs]);
else
BUG();
return wptr;
@@ -5153,7 +5155,7 @@ static void gfx_v9_0_ring_set_wptr_compu
/* XXX check if swapping is necessary on BE */
if (ring->use_doorbell) {
- atomic64_set((atomic64_t*)&adev->wb.wb[ring->wptr_offs], ring->wptr);
+ atomic_store_relaxed(&adev->wb.wb[ring->wptr_offs], ring->wptr);
WDOORBELL64(ring->doorbell_index, ring->wptr);
} else{
BUG(); /* only DOORBELL method supported on gfx9 now */
Index: src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/amdgpu_gmc.c
diff -u src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/amdgpu_gmc.c:1.2 src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/amdgpu_gmc.c:1.3
--- src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/amdgpu_gmc.c:1.2 Sat Dec 18 23:44:58 2021
+++ src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/amdgpu_gmc.c Sun Dec 19 12:02:39 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: amdgpu_gmc.c,v 1.2 2021/12/18 23:44:58 riastradh Exp $ */
+/* $NetBSD: amdgpu_gmc.c,v 1.3 2021/12/19 12:02:39 riastradh Exp $ */
/*
* Copyright 2018 Advanced Micro Devices, Inc.
@@ -27,7 +27,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: amdgpu_gmc.c,v 1.2 2021/12/18 23:44:58 riastradh Exp $");
+__KERNEL_RCSID(0, "$NetBSD: amdgpu_gmc.c,v 1.3 2021/12/19 12:02:39 riastradh Exp $");
#include <linux/io-64-nonatomic-lo-hi.h>
@@ -35,6 +35,8 @@ __KERNEL_RCSID(0, "$NetBSD: amdgpu_gmc.c
#include "amdgpu_ras.h"
#include "amdgpu_xgmi.h"
+#include <linux/nbsd-namespace.h>
+
/**
* amdgpu_gmc_get_pde_for_bo - get the PDE for a BO
*
@@ -54,7 +56,11 @@ void amdgpu_gmc_get_pde_for_bo(struct am
switch (bo->tbo.mem.mem_type) {
case TTM_PL_TT:
ttm = container_of(bo->tbo.ttm, struct ttm_dma_tt, ttm);
+#ifdef __NetBSD__
+ *addr = ttm->dma_address->dm_segs[0].ds_addr;
+#else
*addr = ttm->dma_address[0];
+#endif
break;
case TTM_PL_VRAM:
*addr = amdgpu_bo_gpu_offset(bo);
@@ -103,7 +109,9 @@ int amdgpu_gmc_set_pte_pde(struct amdgpu
uint32_t gpu_page_idx, uint64_t addr,
uint64_t flags)
{
+#ifndef __NetBSD__
void __iomem *ptr = (void *)cpu_pt_addr;
+#endif
uint64_t value;
/*
@@ -111,7 +119,12 @@ int amdgpu_gmc_set_pte_pde(struct amdgpu
*/
value = addr & 0x0000FFFFFFFFF000ULL;
value |= flags;
+#ifdef __NetBSD__
+ /* Caller must issue appropriate bus_dmamap_sync before use. */
+ ((uint64_t *)cpu_pt_addr)[gpu_page_idx] = value;
+#else
writeq(value, ptr + (gpu_page_idx * 8));
+#endif
return 0;
}
@@ -127,15 +140,21 @@ uint64_t amdgpu_gmc_agp_addr(struct ttm_
{
struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
struct ttm_dma_tt *ttm;
+ resource_size_t addr;
if (bo->num_pages != 1 || bo->ttm->caching_state == tt_cached)
return AMDGPU_BO_INVALID_OFFSET;
ttm = container_of(bo->ttm, struct ttm_dma_tt, ttm);
- if (ttm->dma_address[0] + PAGE_SIZE >= adev->gmc.agp_size)
+#ifdef __NetBSD__
+ addr = ttm->dma_address->dm_segs[0].ds_addr;
+#else
+ addr = ttm->dma_address[0];
+#endif
+ if (addr + PAGE_SIZE >= adev->gmc.agp_size)
return AMDGPU_BO_INVALID_OFFSET;
- return adev->gmc.agp_start + ttm->dma_address[0];
+ return adev->gmc.agp_start + addr;
}
/**
@@ -162,7 +181,7 @@ void amdgpu_gmc_vram_location(struct amd
mc->fb_start = mc->vram_start;
mc->fb_end = mc->vram_end;
}
- dev_info(adev->dev, "VRAM: %lluM 0x%016llX - 0x%016llX (%lluM used)\n",
+ dev_info(adev->dev, "VRAM: %"PRIu64"M 0x%016"PRIX64" - 0x%016"PRIX64" (%"PRIu64"M used)\n",
mc->mc_vram_size >> 20, mc->vram_start,
mc->vram_end, mc->real_vram_size >> 20);
}
@@ -206,7 +225,7 @@ void amdgpu_gmc_gart_location(struct amd
mc->gart_start &= ~(four_gb - 1);
mc->gart_end = mc->gart_start + mc->gart_size - 1;
- dev_info(adev->dev, "GART: %lluM 0x%016llX - 0x%016llX\n",
+ dev_info(adev->dev, "GART: %"PRIu64"M 0x%016"PRIX64" - 0x%016"PRIX64"\n",
mc->gart_size >> 20, mc->gart_start, mc->gart_end);
}
@@ -254,7 +273,7 @@ void amdgpu_gmc_agp_location(struct amdg
}
mc->agp_end = mc->agp_start + mc->agp_size - 1;
- dev_info(adev->dev, "AGP: %lluM 0x%016llX - 0x%016llX\n",
+ dev_info(adev->dev, "AGP: %"PRIu64"M 0x%016"PRIX64" - 0x%016"PRIX64"\n",
mc->agp_size >> 20, mc->agp_start, mc->agp_end);
}
Index: src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/amdgpu_gmc_v10_0.c
diff -u src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/amdgpu_gmc_v10_0.c:1.2 src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/amdgpu_gmc_v10_0.c:1.3
--- src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/amdgpu_gmc_v10_0.c:1.2 Sat Dec 18 23:44:58 2021
+++ src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/amdgpu_gmc_v10_0.c Sun Dec 19 12:02:39 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: amdgpu_gmc_v10_0.c,v 1.2 2021/12/18 23:44:58 riastradh Exp $ */
+/* $NetBSD: amdgpu_gmc_v10_0.c,v 1.3 2021/12/19 12:02:39 riastradh Exp $ */
/*
* Copyright 2019 Advanced Micro Devices, Inc.
@@ -23,7 +23,7 @@
*
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: amdgpu_gmc_v10_0.c,v 1.2 2021/12/18 23:44:58 riastradh Exp $");
+__KERNEL_RCSID(0, "$NetBSD: amdgpu_gmc_v10_0.c,v 1.3 2021/12/19 12:02:39 riastradh Exp $");
#include <linux/firmware.h>
#include <linux/pci.h>
@@ -169,7 +169,7 @@ static int gmc_v10_0_process_interrupt(s
entry->src_id, entry->ring_id, entry->vmid,
entry->pasid, task_info.process_name, task_info.tgid,
task_info.task_name, task_info.pid);
- dev_err(adev->dev, " in page starting at address 0x%016llx from client %d\n",
+ dev_err(adev->dev, " in page starting at address 0x%016"PRIx64" from client %d\n",
addr, entry->client_id);
if (!amdgpu_sriov_vf(adev)) {
dev_err(adev->dev,
@@ -819,7 +819,11 @@ static int gmc_v10_0_sw_init(void *handl
*/
adev->gmc.mc_mask = 0xffffffffffffULL; /* 48 bit MC */
+#ifdef __NetBSD__
+ r = drm_limit_dma_space(adev->ddev, 0, DMA_BIT_MASK(44));
+#else
r = dma_set_mask_and_coherent(adev->dev, DMA_BIT_MASK(44));
+#endif
if (r) {
printk(KERN_WARNING "amdgpu: No suitable DMA available.\n");
return r;
Index: src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/amdgpu_gmc_v6_0.c
diff -u src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/amdgpu_gmc_v6_0.c:1.2 src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/amdgpu_gmc_v6_0.c:1.3
--- src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/amdgpu_gmc_v6_0.c:1.2 Sat Dec 18 23:44:58 2021
+++ src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/amdgpu_gmc_v6_0.c Sun Dec 19 12:02:39 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: amdgpu_gmc_v6_0.c,v 1.2 2021/12/18 23:44:58 riastradh Exp $ */
+/* $NetBSD: amdgpu_gmc_v6_0.c,v 1.3 2021/12/19 12:02:39 riastradh Exp $ */
/*
* Copyright 2014 Advanced Micro Devices, Inc.
@@ -24,7 +24,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: amdgpu_gmc_v6_0.c,v 1.2 2021/12/18 23:44:58 riastradh Exp $");
+__KERNEL_RCSID(0, "$NetBSD: amdgpu_gmc_v6_0.c,v 1.3 2021/12/19 12:02:39 riastradh Exp $");
#include <linux/firmware.h>
#include <linux/module.h>
@@ -67,7 +67,7 @@ MODULE_FIRMWARE("amdgpu/si58_mc.bin");
#define MC_SEQ_MISC0__MT__DDR3 0xB0000000
-static const u32 crtc_offsets[6] =
+static const u32 crtc_offsets[6] __unused =
{
SI_CRTC0_REGISTER_OFFSET,
SI_CRTC1_REGISTER_OFFSET,
@@ -861,7 +861,11 @@ static int gmc_v6_0_sw_init(void *handle
adev->gmc.mc_mask = 0xffffffffffULL;
+#ifdef __NetBSD__
+ r = drm_limit_dma_space(adev->ddev, 0, DMA_BIT_MASK(44));
+#else
r = dma_set_mask_and_coherent(adev->dev, DMA_BIT_MASK(44));
+#endif
if (r) {
dev_warn(adev->dev, "amdgpu: No suitable DMA available.\n");
return r;
Index: src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/amdgpu_gmc_v9_0.c
diff -u src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/amdgpu_gmc_v9_0.c:1.2 src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/amdgpu_gmc_v9_0.c:1.3
--- src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/amdgpu_gmc_v9_0.c:1.2 Sat Dec 18 23:44:58 2021
+++ src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/amdgpu_gmc_v9_0.c Sun Dec 19 12:02:39 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: amdgpu_gmc_v9_0.c,v 1.2 2021/12/18 23:44:58 riastradh Exp $ */
+/* $NetBSD: amdgpu_gmc_v9_0.c,v 1.3 2021/12/19 12:02:39 riastradh Exp $ */
/*
* Copyright 2016 Advanced Micro Devices, Inc.
@@ -24,7 +24,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: amdgpu_gmc_v9_0.c,v 1.2 2021/12/18 23:44:58 riastradh Exp $");
+__KERNEL_RCSID(0, "$NetBSD: amdgpu_gmc_v9_0.c,v 1.3 2021/12/19 12:02:39 riastradh Exp $");
#include <linux/firmware.h>
#include <linux/pci.h>
@@ -172,7 +172,7 @@ static const uint32_t ecc_umc_mcumc_ctrl
(0x001d43e0 + 0x00001800),
};
-static const uint32_t ecc_umc_mcumc_status_addrs[] = {
+static const uint32_t ecc_umc_mcumc_status_addrs[] __unused = {
(0x000143c2 + 0x00000000),
(0x000143c2 + 0x00000800),
(0x000143c2 + 0x00001000),
@@ -361,7 +361,7 @@ static int gmc_v9_0_process_interrupt(st
entry->src_id, entry->ring_id, entry->vmid,
entry->pasid, task_info.process_name, task_info.tgid,
task_info.task_name, task_info.pid);
- dev_err(adev->dev, " in page starting at address 0x%016llx from client %d\n",
+ dev_err(adev->dev, " in page starting at address 0x%016"PRIx64" from client %d\n",
addr, entry->client_id);
if (!amdgpu_sriov_vf(adev)) {
dev_err(adev->dev,
@@ -1185,7 +1185,11 @@ static int gmc_v9_0_sw_init(void *handle
*/
adev->gmc.mc_mask = 0xffffffffffffULL; /* 48 bit MC */
+#ifdef __NetBSD__
+ r = drm_limit_dma_space(adev->ddev, 0, DMA_BIT_MASK(44));
+#else
r = dma_set_mask_and_coherent(adev->dev, DMA_BIT_MASK(44));
+#endif
if (r) {
printk(KERN_WARNING "amdgpu: No suitable DMA available.\n");
return r;
Index: src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/amdgpu_gtt_mgr.c
diff -u src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/amdgpu_gtt_mgr.c:1.2 src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/amdgpu_gtt_mgr.c:1.3
--- src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/amdgpu_gtt_mgr.c:1.2 Sat Dec 18 23:44:58 2021
+++ src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/amdgpu_gtt_mgr.c Sun Dec 19 12:02:39 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: amdgpu_gtt_mgr.c,v 1.2 2021/12/18 23:44:58 riastradh Exp $ */
+/* $NetBSD: amdgpu_gtt_mgr.c,v 1.3 2021/12/19 12:02:39 riastradh Exp $ */
/*
* Copyright 2016 Advanced Micro Devices, Inc.
@@ -25,7 +25,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: amdgpu_gtt_mgr.c,v 1.2 2021/12/18 23:44:58 riastradh Exp $");
+__KERNEL_RCSID(0, "$NetBSD: amdgpu_gtt_mgr.c,v 1.3 2021/12/19 12:02:39 riastradh Exp $");
#include "amdgpu.h"
@@ -40,6 +40,8 @@ struct amdgpu_gtt_node {
struct ttm_buffer_object *tbo;
};
+#ifndef __NetBSD__ /* XXX amdgpu sysfs */
+
/**
* DOC: mem_info_gtt_total
*
@@ -81,6 +83,8 @@ static DEVICE_ATTR(mem_info_gtt_total, S
static DEVICE_ATTR(mem_info_gtt_used, S_IRUGO,
amdgpu_mem_info_gtt_used_show, NULL);
+#endif
+
/**
* amdgpu_gtt_mgr_init - init GTT manager and DRM MM
*
@@ -108,6 +112,9 @@ static int amdgpu_gtt_mgr_init(struct tt
atomic64_set(&mgr->available, p_size);
man->priv = mgr;
+#ifdef __NetBSD__ /* XXX amdgpu sysfs */
+ __USE(ret);
+#else
ret = device_create_file(adev->dev, &dev_attr_mem_info_gtt_total);
if (ret) {
DRM_ERROR("Failed to create device file mem_info_gtt_total\n");
@@ -118,6 +125,7 @@ static int amdgpu_gtt_mgr_init(struct tt
DRM_ERROR("Failed to create device file mem_info_gtt_used\n");
return ret;
}
+#endif
return 0;
}
@@ -137,11 +145,16 @@ static int amdgpu_gtt_mgr_fini(struct tt
spin_lock(&mgr->lock);
drm_mm_takedown(&mgr->mm);
spin_unlock(&mgr->lock);
+ spin_lock_destroy(&mgr->lock);
kfree(mgr);
man->priv = NULL;
+#ifdef __NetBSD__ /* XXX amdgpu sysfs */
+ __USE(adev);
+#else
device_remove_file(adev->dev, &dev_attr_mem_info_gtt_total);
device_remove_file(adev->dev, &dev_attr_mem_info_gtt_used);
+#endif
return 0;
}
@@ -349,7 +362,7 @@ static void amdgpu_gtt_mgr_debug(struct
drm_mm_print(&mgr->mm, printer);
spin_unlock(&mgr->lock);
- drm_printf(printer, "man size:%llu pages, gtt available:%lld pages, usage:%lluMB\n",
+ drm_printf(printer, "man size:%"PRIu64" pages, gtt available:%"PRId64" pages, usage:%"PRIu64"MB\n",
man->size, (u64)atomic64_read(&mgr->available),
amdgpu_gtt_mgr_usage(man) >> 20);
}
Index: src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/amdgpu_ids.c
diff -u src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/amdgpu_ids.c:1.2 src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/amdgpu_ids.c:1.3
--- src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/amdgpu_ids.c:1.2 Sat Dec 18 23:44:58 2021
+++ src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/amdgpu_ids.c Sun Dec 19 12:02:39 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: amdgpu_ids.c,v 1.2 2021/12/18 23:44:58 riastradh Exp $ */
+/* $NetBSD: amdgpu_ids.c,v 1.3 2021/12/19 12:02:39 riastradh Exp $ */
/*
* Copyright 2017 Advanced Micro Devices, Inc.
@@ -23,7 +23,7 @@
*
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: amdgpu_ids.c,v 1.2 2021/12/18 23:44:58 riastradh Exp $");
+__KERNEL_RCSID(0, "$NetBSD: amdgpu_ids.c,v 1.3 2021/12/19 12:02:39 riastradh Exp $");
#include "amdgpu_ids.h"
@@ -34,6 +34,8 @@ __KERNEL_RCSID(0, "$NetBSD: amdgpu_ids.c
#include "amdgpu.h"
#include "amdgpu_trace.h"
+#include <linux/nbsd-namespace.h>
+
/*
* PASID manager
*
@@ -43,7 +45,11 @@ __KERNEL_RCSID(0, "$NetBSD: amdgpu_ids.c
* space. Therefore PASIDs are allocated using a global IDA. VMs are
* looked up from the PASID per amdgpu_device.
*/
+#ifdef __NetBSD__ /* XXX */
+struct ida amdgpu_pasid_ida;
+#else
static DEFINE_IDA(amdgpu_pasid_ida);
+#endif
/* Helper to free pasid from a fence callback */
struct amdgpu_pasid_cb {
Index: src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/amdgpu_jpeg_v1_0.c
diff -u src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/amdgpu_jpeg_v1_0.c:1.2 src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/amdgpu_jpeg_v1_0.c:1.3
--- src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/amdgpu_jpeg_v1_0.c:1.2 Sat Dec 18 23:44:58 2021
+++ src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/amdgpu_jpeg_v1_0.c Sun Dec 19 12:02:39 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: amdgpu_jpeg_v1_0.c,v 1.2 2021/12/18 23:44:58 riastradh Exp $ */
+/* $NetBSD: amdgpu_jpeg_v1_0.c,v 1.3 2021/12/19 12:02:39 riastradh Exp $ */
/*
* Copyright 2019 Advanced Micro Devices, Inc.
@@ -24,7 +24,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: amdgpu_jpeg_v1_0.c,v 1.2 2021/12/18 23:44:58 riastradh Exp $");
+__KERNEL_RCSID(0, "$NetBSD: amdgpu_jpeg_v1_0.c,v 1.3 2021/12/19 12:02:39 riastradh Exp $");
#include "amdgpu.h"
#include "amdgpu_jpeg.h"
@@ -484,7 +484,7 @@ int jpeg_v1_0_sw_init(void *handle)
return r;
ring = &adev->jpeg.inst->ring_dec;
- sprintf(ring->name, "jpeg_dec");
+ snprintf(ring->name, sizeof(ring->name), "jpeg_dec");
r = amdgpu_ring_init(adev, ring, 512, &adev->jpeg.inst->irq, 0);
if (r)
return r;
Index: src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/amdgpu_jpeg_v2_0.c
diff -u src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/amdgpu_jpeg_v2_0.c:1.2 src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/amdgpu_jpeg_v2_0.c:1.3
--- src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/amdgpu_jpeg_v2_0.c:1.2 Sat Dec 18 23:44:58 2021
+++ src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/amdgpu_jpeg_v2_0.c Sun Dec 19 12:02:39 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: amdgpu_jpeg_v2_0.c,v 1.2 2021/12/18 23:44:58 riastradh Exp $ */
+/* $NetBSD: amdgpu_jpeg_v2_0.c,v 1.3 2021/12/19 12:02:39 riastradh Exp $ */
/*
* Copyright 2019 Advanced Micro Devices, Inc.
@@ -24,7 +24,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: amdgpu_jpeg_v2_0.c,v 1.2 2021/12/18 23:44:58 riastradh Exp $");
+__KERNEL_RCSID(0, "$NetBSD: amdgpu_jpeg_v2_0.c,v 1.3 2021/12/19 12:02:39 riastradh Exp $");
#include "amdgpu.h"
#include "amdgpu_jpeg.h"
@@ -110,7 +110,7 @@ static int jpeg_v2_0_sw_init(void *handl
ring = &adev->jpeg.inst->ring_dec;
ring->use_doorbell = true;
ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 1;
- sprintf(ring->name, "jpeg_dec");
+ snprintf(ring->name, sizeof(ring->name), "jpeg_dec");
r = amdgpu_ring_init(adev, ring, 512, &adev->jpeg.inst->irq, 0);
if (r)
return r;
Index: src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/amdgpu_jpeg_v2_5.c
diff -u src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/amdgpu_jpeg_v2_5.c:1.2 src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/amdgpu_jpeg_v2_5.c:1.3
--- src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/amdgpu_jpeg_v2_5.c:1.2 Sat Dec 18 23:44:58 2021
+++ src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/amdgpu_jpeg_v2_5.c Sun Dec 19 12:02:39 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: amdgpu_jpeg_v2_5.c,v 1.2 2021/12/18 23:44:58 riastradh Exp $ */
+/* $NetBSD: amdgpu_jpeg_v2_5.c,v 1.3 2021/12/19 12:02:39 riastradh Exp $ */
/*
* Copyright 2019 Advanced Micro Devices, Inc.
@@ -24,7 +24,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: amdgpu_jpeg_v2_5.c,v 1.2 2021/12/18 23:44:58 riastradh Exp $");
+__KERNEL_RCSID(0, "$NetBSD: amdgpu_jpeg_v2_5.c,v 1.3 2021/12/19 12:02:39 riastradh Exp $");
#include "amdgpu.h"
#include "amdgpu_jpeg.h"
@@ -122,7 +122,7 @@ static int jpeg_v2_5_sw_init(void *handl
ring = &adev->jpeg.inst[i].ring_dec;
ring->use_doorbell = true;
ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 1 + 8 * i;
- sprintf(ring->name, "jpeg_dec_%d", i);
+ snprintf(ring->name, sizeof(ring->name), "jpeg_dec_%d", i);
r = amdgpu_ring_init(adev, ring, 512, &adev->jpeg.inst[i].irq, 0);
if (r)
return r;
Index: src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/amdgpu_mes_v10_1.c
diff -u src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/amdgpu_mes_v10_1.c:1.2 src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/amdgpu_mes_v10_1.c:1.3
--- src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/amdgpu_mes_v10_1.c:1.2 Sat Dec 18 23:44:58 2021
+++ src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/amdgpu_mes_v10_1.c Sun Dec 19 12:02:39 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: amdgpu_mes_v10_1.c,v 1.2 2021/12/18 23:44:58 riastradh Exp $ */
+/* $NetBSD: amdgpu_mes_v10_1.c,v 1.3 2021/12/19 12:02:39 riastradh Exp $ */
/*
* Copyright 2019 Advanced Micro Devices, Inc.
@@ -24,7 +24,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: amdgpu_mes_v10_1.c,v 1.2 2021/12/18 23:44:58 riastradh Exp $");
+__KERNEL_RCSID(0, "$NetBSD: amdgpu_mes_v10_1.c,v 1.3 2021/12/19 12:02:39 riastradh Exp $");
#include <linux/firmware.h>
#include <linux/module.h>
@@ -60,7 +60,7 @@ static int mes_v10_1_resume_gang(struct
return 0;
}
-static const struct amdgpu_mes_funcs mes_v10_1_funcs = {
+static const struct amdgpu_mes_funcs mes_v10_1_funcs __unused = {
.add_hw_queue = mes_v10_1_add_hw_queue,
.remove_hw_queue = mes_v10_1_remove_hw_queue,
.suspend_gang = mes_v10_1_suspend_gang,
Index: src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/amdgpu_navi10_reg_init.c
diff -u src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/amdgpu_navi10_reg_init.c:1.2 src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/amdgpu_navi10_reg_init.c:1.3
--- src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/amdgpu_navi10_reg_init.c:1.2 Sat Dec 18 23:44:58 2021
+++ src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/amdgpu_navi10_reg_init.c Sun Dec 19 12:02:39 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: amdgpu_navi10_reg_init.c,v 1.2 2021/12/18 23:44:58 riastradh Exp $ */
+/* $NetBSD: amdgpu_navi10_reg_init.c,v 1.3 2021/12/19 12:02:39 riastradh Exp $ */
/*
* Copyright 2018 Advanced Micro Devices, Inc.
@@ -23,7 +23,7 @@
*
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: amdgpu_navi10_reg_init.c,v 1.2 2021/12/18 23:44:58 riastradh Exp $");
+__KERNEL_RCSID(0, "$NetBSD: amdgpu_navi10_reg_init.c,v 1.3 2021/12/19 12:02:39 riastradh Exp $");
#include "amdgpu.h"
#include "nv.h"
@@ -36,22 +36,22 @@ int navi10_reg_base_init(struct amdgpu_d
int i;
for (i = 0 ; i < MAX_INSTANCE ; ++i) {
- adev->reg_offset[GC_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i]));
- adev->reg_offset[HDP_HWIP][i] = (uint32_t *)(&(HDP_BASE.instance[i]));
- adev->reg_offset[MMHUB_HWIP][i] = (uint32_t *)(&(MMHUB_BASE.instance[i]));
- adev->reg_offset[ATHUB_HWIP][i] = (uint32_t *)(&(ATHUB_BASE.instance[i]));
- adev->reg_offset[NBIO_HWIP][i] = (uint32_t *)(&(NBIO_BASE.instance[i]));
- adev->reg_offset[MP0_HWIP][i] = (uint32_t *)(&(MP0_BASE.instance[i]));
- adev->reg_offset[MP1_HWIP][i] = (uint32_t *)(&(MP1_BASE.instance[i]));
- adev->reg_offset[VCN_HWIP][i] = (uint32_t *)(&(VCN_BASE.instance[i]));
- adev->reg_offset[DF_HWIP][i] = (uint32_t *)(&(DF_BASE.instance[i]));
- adev->reg_offset[DCE_HWIP][i] = (uint32_t *)(&(DCN_BASE.instance[i]));
- adev->reg_offset[OSSSYS_HWIP][i] = (uint32_t *)(&(OSSSYS_BASE.instance[i]));
- adev->reg_offset[SDMA0_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i]));
- adev->reg_offset[SDMA1_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i]));
- adev->reg_offset[SMUIO_HWIP][i] = (uint32_t *)(&(SMUIO_BASE.instance[i]));
- adev->reg_offset[THM_HWIP][i] = (uint32_t *)(&(THM_BASE.instance[i]));
- adev->reg_offset[CLK_HWIP][i] = (uint32_t *)(&(CLK_BASE.instance[i]));
+ adev->reg_offset[GC_HWIP][i] = (const uint32_t *)(&(GC_BASE.instance[i]));
+ adev->reg_offset[HDP_HWIP][i] = (const uint32_t *)(&(HDP_BASE.instance[i]));
+ adev->reg_offset[MMHUB_HWIP][i] = (const uint32_t *)(&(MMHUB_BASE.instance[i]));
+ adev->reg_offset[ATHUB_HWIP][i] = (const uint32_t *)(&(ATHUB_BASE.instance[i]));
+ adev->reg_offset[NBIO_HWIP][i] = (const uint32_t *)(&(NBIO_BASE.instance[i]));
+ adev->reg_offset[MP0_HWIP][i] = (const uint32_t *)(&(MP0_BASE.instance[i]));
+ adev->reg_offset[MP1_HWIP][i] = (const uint32_t *)(&(MP1_BASE.instance[i]));
+ adev->reg_offset[VCN_HWIP][i] = (const uint32_t *)(&(VCN_BASE.instance[i]));
+ adev->reg_offset[DF_HWIP][i] = (const uint32_t *)(&(DF_BASE.instance[i]));
+ adev->reg_offset[DCE_HWIP][i] = (const uint32_t *)(&(DCN_BASE.instance[i]));
+ adev->reg_offset[OSSSYS_HWIP][i] = (const uint32_t *)(&(OSSSYS_BASE.instance[i]));
+ adev->reg_offset[SDMA0_HWIP][i] = (const uint32_t *)(&(GC_BASE.instance[i]));
+ adev->reg_offset[SDMA1_HWIP][i] = (const uint32_t *)(&(GC_BASE.instance[i]));
+ adev->reg_offset[SMUIO_HWIP][i] = (const uint32_t *)(&(SMUIO_BASE.instance[i]));
+ adev->reg_offset[THM_HWIP][i] = (const uint32_t *)(&(THM_BASE.instance[i]));
+ adev->reg_offset[CLK_HWIP][i] = (const uint32_t *)(&(CLK_BASE.instance[i]));
}
return 0;
Index: src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/amdgpu_navi12_reg_init.c
diff -u src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/amdgpu_navi12_reg_init.c:1.2 src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/amdgpu_navi12_reg_init.c:1.3
--- src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/amdgpu_navi12_reg_init.c:1.2 Sat Dec 18 23:44:58 2021
+++ src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/amdgpu_navi12_reg_init.c Sun Dec 19 12:02:39 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: amdgpu_navi12_reg_init.c,v 1.2 2021/12/18 23:44:58 riastradh Exp $ */
+/* $NetBSD: amdgpu_navi12_reg_init.c,v 1.3 2021/12/19 12:02:39 riastradh Exp $ */
/*
* Copyright 2018 Advanced Micro Devices, Inc.
@@ -23,7 +23,7 @@
*
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: amdgpu_navi12_reg_init.c,v 1.2 2021/12/18 23:44:58 riastradh Exp $");
+__KERNEL_RCSID(0, "$NetBSD: amdgpu_navi12_reg_init.c,v 1.3 2021/12/19 12:02:39 riastradh Exp $");
#include "amdgpu.h"
#include "nv.h"
@@ -36,22 +36,22 @@ int navi12_reg_base_init(struct amdgpu_d
/* HW has more IP blocks, only initialized the blocks needed by driver */
uint32_t i;
for (i = 0 ; i < MAX_INSTANCE ; ++i) {
- adev->reg_offset[GC_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i]));
- adev->reg_offset[HDP_HWIP][i] = (uint32_t *)(&(HDP_BASE.instance[i]));
- adev->reg_offset[MMHUB_HWIP][i] = (uint32_t *)(&(MMHUB_BASE.instance[i]));
- adev->reg_offset[ATHUB_HWIP][i] = (uint32_t *)(&(ATHUB_BASE.instance[i]));
- adev->reg_offset[NBIO_HWIP][i] = (uint32_t *)(&(NBIF0_BASE.instance[i]));
- adev->reg_offset[MP0_HWIP][i] = (uint32_t *)(&(MP0_BASE.instance[i]));
- adev->reg_offset[MP1_HWIP][i] = (uint32_t *)(&(MP1_BASE.instance[i]));
- adev->reg_offset[VCN_HWIP][i] = (uint32_t *)(&(UVD0_BASE.instance[i]));
- adev->reg_offset[DF_HWIP][i] = (uint32_t *)(&(DF_BASE.instance[i]));
- adev->reg_offset[DCE_HWIP][i] = (uint32_t *)(&(DMU_BASE.instance[i]));
- adev->reg_offset[OSSSYS_HWIP][i] = (uint32_t *)(&(OSSSYS_BASE.instance[i]));
- adev->reg_offset[SDMA0_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i]));
- adev->reg_offset[SDMA1_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i]));
- adev->reg_offset[SMUIO_HWIP][i] = (uint32_t *)(&(SMUIO_BASE.instance[i]));
- adev->reg_offset[THM_HWIP][i] = (uint32_t *)(&(THM_BASE.instance[i]));
- adev->reg_offset[CLK_HWIP][i] = (uint32_t *)(&(CLK_BASE.instance[i]));
+ adev->reg_offset[GC_HWIP][i] = (const uint32_t *)(&(GC_BASE.instance[i]));
+ adev->reg_offset[HDP_HWIP][i] = (const uint32_t *)(&(HDP_BASE.instance[i]));
+ adev->reg_offset[MMHUB_HWIP][i] = (const uint32_t *)(&(MMHUB_BASE.instance[i]));
+ adev->reg_offset[ATHUB_HWIP][i] = (const uint32_t *)(&(ATHUB_BASE.instance[i]));
+ adev->reg_offset[NBIO_HWIP][i] = (const uint32_t *)(&(NBIF0_BASE.instance[i]));
+ adev->reg_offset[MP0_HWIP][i] = (const uint32_t *)(&(MP0_BASE.instance[i]));
+ adev->reg_offset[MP1_HWIP][i] = (const uint32_t *)(&(MP1_BASE.instance[i]));
+ adev->reg_offset[VCN_HWIP][i] = (const uint32_t *)(&(UVD0_BASE.instance[i]));
+ adev->reg_offset[DF_HWIP][i] = (const uint32_t *)(&(DF_BASE.instance[i]));
+ adev->reg_offset[DCE_HWIP][i] = (const uint32_t *)(&(DMU_BASE.instance[i]));
+ adev->reg_offset[OSSSYS_HWIP][i] = (const uint32_t *)(&(OSSSYS_BASE.instance[i]));
+ adev->reg_offset[SDMA0_HWIP][i] = (const uint32_t *)(&(GC_BASE.instance[i]));
+ adev->reg_offset[SDMA1_HWIP][i] = (const uint32_t *)(&(GC_BASE.instance[i]));
+ adev->reg_offset[SMUIO_HWIP][i] = (const uint32_t *)(&(SMUIO_BASE.instance[i]));
+ adev->reg_offset[THM_HWIP][i] = (const uint32_t *)(&(THM_BASE.instance[i]));
+ adev->reg_offset[CLK_HWIP][i] = (const uint32_t *)(&(CLK_BASE.instance[i]));
}
return 0;
}
Index: src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/amdgpu_navi14_reg_init.c
diff -u src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/amdgpu_navi14_reg_init.c:1.2 src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/amdgpu_navi14_reg_init.c:1.3
--- src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/amdgpu_navi14_reg_init.c:1.2 Sat Dec 18 23:44:58 2021
+++ src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/amdgpu_navi14_reg_init.c Sun Dec 19 12:02:39 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: amdgpu_navi14_reg_init.c,v 1.2 2021/12/18 23:44:58 riastradh Exp $ */
+/* $NetBSD: amdgpu_navi14_reg_init.c,v 1.3 2021/12/19 12:02:39 riastradh Exp $ */
/*
* Copyright 2018 Advanced Micro Devices, Inc.
@@ -23,7 +23,7 @@
*
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: amdgpu_navi14_reg_init.c,v 1.2 2021/12/18 23:44:58 riastradh Exp $");
+__KERNEL_RCSID(0, "$NetBSD: amdgpu_navi14_reg_init.c,v 1.3 2021/12/19 12:02:39 riastradh Exp $");
#include "amdgpu.h"
#include "nv.h"
@@ -36,22 +36,22 @@ int navi14_reg_base_init(struct amdgpu_d
int i;
for (i = 0 ; i < MAX_INSTANCE ; ++i) {
- adev->reg_offset[GC_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i]));
- adev->reg_offset[HDP_HWIP][i] = (uint32_t *)(&(HDP_BASE.instance[i]));
- adev->reg_offset[MMHUB_HWIP][i] = (uint32_t *)(&(MMHUB_BASE.instance[i]));
- adev->reg_offset[ATHUB_HWIP][i] = (uint32_t *)(&(ATHUB_BASE.instance[i]));
- adev->reg_offset[NBIO_HWIP][i] = (uint32_t *)(&(NBIF0_BASE.instance[i]));
- adev->reg_offset[MP0_HWIP][i] = (uint32_t *)(&(MP0_BASE.instance[i]));
- adev->reg_offset[MP1_HWIP][i] = (uint32_t *)(&(MP1_BASE.instance[i]));
- adev->reg_offset[VCN_HWIP][i] = (uint32_t *)(&(UVD0_BASE.instance[i]));
- adev->reg_offset[DF_HWIP][i] = (uint32_t *)(&(DF_BASE.instance[i]));
- adev->reg_offset[DCE_HWIP][i] = (uint32_t *)(&(DMU_BASE.instance[i]));
- adev->reg_offset[OSSSYS_HWIP][i] = (uint32_t *)(&(OSSSYS_BASE.instance[i]));
- adev->reg_offset[SDMA0_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i]));
- adev->reg_offset[SDMA1_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i]));
- adev->reg_offset[SMUIO_HWIP][i] = (uint32_t *)(&(SMUIO_BASE.instance[i]));
- adev->reg_offset[THM_HWIP][i] = (uint32_t *)(&(THM_BASE.instance[i]));
- adev->reg_offset[CLK_HWIP][i] = (uint32_t *)(&(CLK_BASE.instance[i]));
+ adev->reg_offset[GC_HWIP][i] = (const uint32_t *)(&(GC_BASE.instance[i]));
+ adev->reg_offset[HDP_HWIP][i] = (const uint32_t *)(&(HDP_BASE.instance[i]));
+ adev->reg_offset[MMHUB_HWIP][i] = (const uint32_t *)(&(MMHUB_BASE.instance[i]));
+ adev->reg_offset[ATHUB_HWIP][i] = (const uint32_t *)(&(ATHUB_BASE.instance[i]));
+ adev->reg_offset[NBIO_HWIP][i] = (const uint32_t *)(&(NBIF0_BASE.instance[i]));
+ adev->reg_offset[MP0_HWIP][i] = (const uint32_t *)(&(MP0_BASE.instance[i]));
+ adev->reg_offset[MP1_HWIP][i] = (const uint32_t *)(&(MP1_BASE.instance[i]));
+ adev->reg_offset[VCN_HWIP][i] = (const uint32_t *)(&(UVD0_BASE.instance[i]));
+ adev->reg_offset[DF_HWIP][i] = (const uint32_t *)(&(DF_BASE.instance[i]));
+ adev->reg_offset[DCE_HWIP][i] = (const uint32_t *)(&(DMU_BASE.instance[i]));
+ adev->reg_offset[OSSSYS_HWIP][i] = (const uint32_t *)(&(OSSSYS_BASE.instance[i]));
+ adev->reg_offset[SDMA0_HWIP][i] = (const uint32_t *)(&(GC_BASE.instance[i]));
+ adev->reg_offset[SDMA1_HWIP][i] = (const uint32_t *)(&(GC_BASE.instance[i]));
+ adev->reg_offset[SMUIO_HWIP][i] = (const uint32_t *)(&(SMUIO_BASE.instance[i]));
+ adev->reg_offset[THM_HWIP][i] = (const uint32_t *)(&(THM_BASE.instance[i]));
+ adev->reg_offset[CLK_HWIP][i] = (const uint32_t *)(&(CLK_BASE.instance[i]));
}
return 0;
Index: src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/amdgpu_nv.c
diff -u src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/amdgpu_nv.c:1.2 src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/amdgpu_nv.c:1.3
--- src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/amdgpu_nv.c:1.2 Sat Dec 18 23:44:58 2021
+++ src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/amdgpu_nv.c Sun Dec 19 12:02:39 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: amdgpu_nv.c,v 1.2 2021/12/18 23:44:58 riastradh Exp $ */
+/* $NetBSD: amdgpu_nv.c,v 1.3 2021/12/19 12:02:39 riastradh Exp $ */
/*
* Copyright 2019 Advanced Micro Devices, Inc.
@@ -23,7 +23,7 @@
*
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: amdgpu_nv.c,v 1.2 2021/12/18 23:44:58 riastradh Exp $");
+__KERNEL_RCSID(0, "$NetBSD: amdgpu_nv.c,v 1.3 2021/12/19 12:02:39 riastradh Exp $");
#include <linux/firmware.h>
#include <linux/slab.h>
@@ -63,6 +63,8 @@ __KERNEL_RCSID(0, "$NetBSD: amdgpu_nv.c,
#include "mes_v10_1.h"
#include "mxgpu_nv.h"
+#include <linux/nbsd-namespace.h>
+
static const struct amd_ip_funcs nv_common_ip_funcs;
/*
Index: src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/amdgpu_rlc.h
diff -u src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/amdgpu_rlc.h:1.2 src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/amdgpu_rlc.h:1.3
--- src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/amdgpu_rlc.h:1.2 Sat Dec 18 23:44:58 2021
+++ src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/amdgpu_rlc.h Sun Dec 19 12:02:39 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: amdgpu_rlc.h,v 1.2 2021/12/18 23:44:58 riastradh Exp $ */
+/* $NetBSD: amdgpu_rlc.h,v 1.3 2021/12/19 12:02:39 riastradh Exp $ */
/*
* Copyright 2014 Advanced Micro Devices, Inc.
@@ -170,9 +170,9 @@ struct amdgpu_rlc {
u32 *register_list_format;
u32 *register_restore;
- u8 *save_restore_list_cntl;
- u8 *save_restore_list_gpm;
- u8 *save_restore_list_srm;
+ const u8 *save_restore_list_cntl;
+ const u8 *save_restore_list_gpm;
+ const u8 *save_restore_list_srm;
bool is_rlc_v2_1;
Index: src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/amdgpu_gmc_v7_0.c
diff -u src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/amdgpu_gmc_v7_0.c:1.4 src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/amdgpu_gmc_v7_0.c:1.5
--- src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/amdgpu_gmc_v7_0.c:1.4 Sat Dec 18 23:44:58 2021
+++ src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/amdgpu_gmc_v7_0.c Sun Dec 19 12:02:39 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: amdgpu_gmc_v7_0.c,v 1.4 2021/12/18 23:44:58 riastradh Exp $ */
+/* $NetBSD: amdgpu_gmc_v7_0.c,v 1.5 2021/12/19 12:02:39 riastradh Exp $ */
/*
* Copyright 2014 Advanced Micro Devices, Inc.
@@ -24,7 +24,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: amdgpu_gmc_v7_0.c,v 1.4 2021/12/18 23:44:58 riastradh Exp $");
+__KERNEL_RCSID(0, "$NetBSD: amdgpu_gmc_v7_0.c,v 1.5 2021/12/19 12:02:39 riastradh Exp $");
#include <linux/firmware.h>
#include <linux/module.h>
@@ -1027,20 +1027,15 @@ static int gmc_v7_0_sw_init(void *handle
*/
adev->gmc.mc_mask = 0xffffffffffULL; /* 40 bit MC */
-#ifdef __NetBSD__ /* XXX post-merge audit - switch to DMA_BIT_MASK */
- adev->need_dma32 = false;
- dma_bits = adev->need_dma32 ? 32 : 40;
-
- r = drm_limit_dma_space(adev->ddev, 0, __BITS(dma_bits - 1, 0));
- if (r)
- DRM_ERROR("No suitable DMA available.\n");
+#ifdef __NetBSD__
+ r = drm_limit_dma_space(adev->ddev, 0, DMA_BIT_MASK(40));
#else
r = dma_set_mask_and_coherent(adev->dev, DMA_BIT_MASK(40));
+#endif
if (r) {
pr_warn("amdgpu: No suitable DMA available\n");
return r;
}
-#endif /* __NetBSD__ */
adev->need_swiotlb = drm_need_swiotlb(40);
r = gmc_v7_0_init_microcode(adev);
Index: src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/amdgpu_gmc_v8_0.c
diff -u src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/amdgpu_gmc_v8_0.c:1.4 src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/amdgpu_gmc_v8_0.c:1.5
--- src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/amdgpu_gmc_v8_0.c:1.4 Sat Dec 18 23:44:58 2021
+++ src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/amdgpu_gmc_v8_0.c Sun Dec 19 12:02:39 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: amdgpu_gmc_v8_0.c,v 1.4 2021/12/18 23:44:58 riastradh Exp $ */
+/* $NetBSD: amdgpu_gmc_v8_0.c,v 1.5 2021/12/19 12:02:39 riastradh Exp $ */
/*
* Copyright 2014 Advanced Micro Devices, Inc.
@@ -24,7 +24,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: amdgpu_gmc_v8_0.c,v 1.4 2021/12/18 23:44:58 riastradh Exp $");
+__KERNEL_RCSID(0, "$NetBSD: amdgpu_gmc_v8_0.c,v 1.5 2021/12/19 12:02:39 riastradh Exp $");
#include <linux/firmware.h>
#include <linux/module.h>
@@ -1148,7 +1148,7 @@ static int gmc_v8_0_sw_init(void *handle
adev->gmc.mc_mask = 0xffffffffffULL; /* 40 bit MC */
#ifdef __NetBSD__
- r = drm_limit_dma_space(adev->ddev, 0, __BITS(39,0));
+ r = drm_limit_dma_space(adev->ddev, 0, DMA_BIT_MASK(40));
#else
r = dma_set_mask_and_coherent(adev->dev, DMA_BIT_MASK(40));
#endif
Index: src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/amdgpu_ih.c
diff -u src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/amdgpu_ih.c:1.7 src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/amdgpu_ih.c:1.8
--- src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/amdgpu_ih.c:1.7 Sun Dec 19 11:26:25 2021
+++ src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/amdgpu_ih.c Sun Dec 19 12:02:39 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: amdgpu_ih.c,v 1.7 2021/12/19 11:26:25 riastradh Exp $ */
+/* $NetBSD: amdgpu_ih.c,v 1.8 2021/12/19 12:02:39 riastradh Exp $ */
/*
* Copyright 2014 Advanced Micro Devices, Inc.
@@ -24,7 +24,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: amdgpu_ih.c,v 1.7 2021/12/19 11:26:25 riastradh Exp $");
+__KERNEL_RCSID(0, "$NetBSD: amdgpu_ih.c,v 1.8 2021/12/19 12:02:39 riastradh Exp $");
#include <linux/dma-mapping.h>
@@ -126,7 +126,7 @@ fail3: __unused bus_dmamem_unmap(adev->
r = amdgpu_bo_create_kernel(adev, ih->ring_size, PAGE_SIZE,
AMDGPU_GEM_DOMAIN_GTT,
&ih->ring_obj, &ih->gpu_addr,
- (void **)&ih->ring);
+ (void **)__UNVOLATILE(&ih->ring));
if (r) {
amdgpu_device_wb_free(adev, rptr_offs);
amdgpu_device_wb_free(adev, wptr_offs);
@@ -173,7 +173,7 @@ void amdgpu_ih_ring_fini(struct amdgpu_d
ih->ring = NULL;
} else {
amdgpu_bo_free_kernel(&ih->ring_obj, &ih->gpu_addr,
- (void **)&ih->ring);
+ (void **)__UNVOLATILE(&ih->ring));
amdgpu_device_wb_free(adev, (ih->wptr_addr - ih->gpu_addr) / 4);
amdgpu_device_wb_free(adev, (ih->rptr_addr - ih->gpu_addr) / 4);
}
Index: src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/amdgpu_ttm.c
diff -u src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/amdgpu_ttm.c:1.7 src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/amdgpu_ttm.c:1.8
--- src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/amdgpu_ttm.c:1.7 Sun Dec 19 10:56:50 2021
+++ src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/amdgpu_ttm.c Sun Dec 19 12:02:39 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: amdgpu_ttm.c,v 1.7 2021/12/19 10:56:50 riastradh Exp $ */
+/* $NetBSD: amdgpu_ttm.c,v 1.8 2021/12/19 12:02:39 riastradh Exp $ */
/*
* Copyright 2009 Jerome Glisse.
@@ -33,7 +33,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: amdgpu_ttm.c,v 1.7 2021/12/19 10:56:50 riastradh Exp $");
+__KERNEL_RCSID(0, "$NetBSD: amdgpu_ttm.c,v 1.8 2021/12/19 12:02:39 riastradh Exp $");
#include <linux/dma-mapping.h>
#include <linux/iommu.h>
@@ -769,7 +769,11 @@ struct amdgpu_ttm_tt {
struct drm_gem_object *gobj;
u64 offset;
uint64_t userptr;
+#ifdef __NetBSD__
+ struct proc *usertask;
+#else
struct task_struct *usertask;
+#endif
uint32_t userflags;
#if IS_ENABLED(CONFIG_DRM_AMDGPU_USERPTR)
struct hmm_range *range;
@@ -1452,7 +1456,11 @@ int amdgpu_ttm_tt_set_userptr(struct ttm
/**
* amdgpu_ttm_tt_get_usermm - Return memory manager for ttm_tt object
*/
+#ifdef __NetBSD__
+struct vmspace *amdgpu_ttm_tt_get_usermm(struct ttm_tt *ttm)
+#else
struct mm_struct *amdgpu_ttm_tt_get_usermm(struct ttm_tt *ttm)
+#endif
{
struct amdgpu_ttm_tt *gtt = (void *)ttm;
@@ -1462,7 +1470,11 @@ struct mm_struct *amdgpu_ttm_tt_get_user
if (gtt->usertask == NULL)
return NULL;
+#ifdef __NetBSD__
+ return gtt->usertask->p_vmspace;
+#else
return gtt->usertask->mm;
+#endif
}
/**
Index: src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/amdgpu_ttm.h
diff -u src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/amdgpu_ttm.h:1.3 src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/amdgpu_ttm.h:1.4
--- src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/amdgpu_ttm.h:1.3 Sun Dec 19 10:59:01 2021
+++ src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/amdgpu_ttm.h Sun Dec 19 12:02:39 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: amdgpu_ttm.h,v 1.3 2021/12/19 10:59:01 riastradh Exp $ */
+/* $NetBSD: amdgpu_ttm.h,v 1.4 2021/12/19 12:02:39 riastradh Exp $ */
/*
* Copyright 2016 Advanced Micro Devices, Inc.
@@ -138,7 +138,11 @@ void amdgpu_ttm_tt_set_user_pages(struct
int amdgpu_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t addr,
uint32_t flags);
bool amdgpu_ttm_tt_has_userptr(struct ttm_tt *ttm);
+#ifdef __NetBSD__
+struct vmspace *amdgpu_ttm_tt_get_usermm(struct ttm_tt *ttm);
+#else
struct mm_struct *amdgpu_ttm_tt_get_usermm(struct ttm_tt *ttm);
+#endif
bool amdgpu_ttm_tt_affect_userptr(struct ttm_tt *ttm, unsigned long start,
unsigned long end);
bool amdgpu_ttm_tt_userptr_invalidated(struct ttm_tt *ttm,
Index: src/sys/external/bsd/drm2/dist/drm/amd/display/dc/basics/amdgpu_fixpt31_32.c
diff -u src/sys/external/bsd/drm2/dist/drm/amd/display/dc/basics/amdgpu_fixpt31_32.c:1.2 src/sys/external/bsd/drm2/dist/drm/amd/display/dc/basics/amdgpu_fixpt31_32.c:1.3
--- src/sys/external/bsd/drm2/dist/drm/amd/display/dc/basics/amdgpu_fixpt31_32.c:1.2 Sat Dec 18 23:45:00 2021
+++ src/sys/external/bsd/drm2/dist/drm/amd/display/dc/basics/amdgpu_fixpt31_32.c Sun Dec 19 12:02:39 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: amdgpu_fixpt31_32.c,v 1.2 2021/12/18 23:45:00 riastradh Exp $ */
+/* $NetBSD: amdgpu_fixpt31_32.c,v 1.3 2021/12/19 12:02:39 riastradh Exp $ */
/*
* Copyright 2012-15 Advanced Micro Devices, Inc.
@@ -26,7 +26,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: amdgpu_fixpt31_32.c,v 1.2 2021/12/18 23:45:00 riastradh Exp $");
+__KERNEL_RCSID(0, "$NetBSD: amdgpu_fixpt31_32.c,v 1.3 2021/12/19 12:02:39 riastradh Exp $");
#include "dm_services.h"
#include "include/fixed31_32.h"
@@ -51,10 +51,12 @@ static inline unsigned long long complet
unsigned long long *remainder)
{
unsigned long long result;
+ uint64_t r64;
ASSERT(divisor);
- result = div64_u64_rem(dividend, divisor, remainder);
+ result = div64_u64_rem(dividend, divisor, &r64);
+ *remainder = r64;
return result;
}
Index: src/sys/external/bsd/drm2/dist/drm/amd/display/dc/gpio/amdgpu_hw_ddc.c
diff -u src/sys/external/bsd/drm2/dist/drm/amd/display/dc/gpio/amdgpu_hw_ddc.c:1.2 src/sys/external/bsd/drm2/dist/drm/amd/display/dc/gpio/amdgpu_hw_ddc.c:1.3
--- src/sys/external/bsd/drm2/dist/drm/amd/display/dc/gpio/amdgpu_hw_ddc.c:1.2 Sat Dec 18 23:45:04 2021
+++ src/sys/external/bsd/drm2/dist/drm/amd/display/dc/gpio/amdgpu_hw_ddc.c Sun Dec 19 12:02:39 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: amdgpu_hw_ddc.c,v 1.2 2021/12/18 23:45:04 riastradh Exp $ */
+/* $NetBSD: amdgpu_hw_ddc.c,v 1.3 2021/12/19 12:02:39 riastradh Exp $ */
/*
* Copyright 2012-15 Advanced Micro Devices, Inc.
@@ -26,7 +26,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: amdgpu_hw_ddc.c,v 1.2 2021/12/18 23:45:04 riastradh Exp $");
+__KERNEL_RCSID(0, "$NetBSD: amdgpu_hw_ddc.c,v 1.3 2021/12/19 12:02:39 riastradh Exp $");
#include <linux/delay.h>
#include <linux/slab.h>
@@ -112,7 +112,7 @@ static enum gpio_result set_config(
msleep(3);
}
} else {
- uint32_t reg2;
+ uint32_t reg2 __unused;
uint32_t sda_pd_dis = 0;
uint32_t scl_pd_dis = 0;
Index: src/sys/external/bsd/drm2/dist/drm/amd/display/dc/gpio/amdgpu_hw_gpio.c
diff -u src/sys/external/bsd/drm2/dist/drm/amd/display/dc/gpio/amdgpu_hw_gpio.c:1.2 src/sys/external/bsd/drm2/dist/drm/amd/display/dc/gpio/amdgpu_hw_gpio.c:1.3
--- src/sys/external/bsd/drm2/dist/drm/amd/display/dc/gpio/amdgpu_hw_gpio.c:1.2 Sat Dec 18 23:45:04 2021
+++ src/sys/external/bsd/drm2/dist/drm/amd/display/dc/gpio/amdgpu_hw_gpio.c Sun Dec 19 12:02:39 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: amdgpu_hw_gpio.c,v 1.2 2021/12/18 23:45:04 riastradh Exp $ */
+/* $NetBSD: amdgpu_hw_gpio.c,v 1.3 2021/12/19 12:02:39 riastradh Exp $ */
/*
* Copyright 2012-15 Advanced Micro Devices, Inc.
@@ -26,7 +26,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: amdgpu_hw_gpio.c,v 1.2 2021/12/18 23:45:04 riastradh Exp $");
+__KERNEL_RCSID(0, "$NetBSD: amdgpu_hw_gpio.c,v 1.3 2021/12/19 12:02:39 riastradh Exp $");
#include "dm_services.h"
#include "include/gpio_types.h"
@@ -79,7 +79,7 @@ enum gpio_result dal_hw_gpio_get_value(
const struct hw_gpio_pin *ptr,
uint32_t *value)
{
- const struct hw_gpio *gpio = FROM_HW_GPIO_PIN(ptr);
+ const struct hw_gpio *gpio = const_container_of(ptr, struct hw_gpio, base);
enum gpio_result result = GPIO_RESULT_OK;
@@ -101,7 +101,7 @@ enum gpio_result dal_hw_gpio_set_value(
const struct hw_gpio_pin *ptr,
uint32_t value)
{
- struct hw_gpio *gpio = FROM_HW_GPIO_PIN(ptr);
+ const struct hw_gpio *gpio = const_container_of(ptr, struct hw_gpio, base);
/* This is the public interface
* where the input comes from client, not shifted yet
Index: src/sys/external/bsd/drm2/dist/drm/amd/display/dc/gpio/amdgpu_hw_hpd.c
diff -u src/sys/external/bsd/drm2/dist/drm/amd/display/dc/gpio/amdgpu_hw_hpd.c:1.2 src/sys/external/bsd/drm2/dist/drm/amd/display/dc/gpio/amdgpu_hw_hpd.c:1.3
--- src/sys/external/bsd/drm2/dist/drm/amd/display/dc/gpio/amdgpu_hw_hpd.c:1.2 Sat Dec 18 23:45:04 2021
+++ src/sys/external/bsd/drm2/dist/drm/amd/display/dc/gpio/amdgpu_hw_hpd.c Sun Dec 19 12:02:39 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: amdgpu_hw_hpd.c,v 1.2 2021/12/18 23:45:04 riastradh Exp $ */
+/* $NetBSD: amdgpu_hw_hpd.c,v 1.3 2021/12/19 12:02:39 riastradh Exp $ */
/*
* Copyright 2012-15 Advanced Micro Devices, Inc.
@@ -26,7 +26,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: amdgpu_hw_hpd.c,v 1.2 2021/12/18 23:45:04 riastradh Exp $");
+__KERNEL_RCSID(0, "$NetBSD: amdgpu_hw_hpd.c,v 1.3 2021/12/19 12:02:39 riastradh Exp $");
#include <linux/slab.h>
@@ -73,7 +73,8 @@ static enum gpio_result get_value(
const struct hw_gpio_pin *ptr,
uint32_t *value)
{
- struct hw_hpd *hpd = HW_HPD_FROM_BASE(ptr);
+ const struct hw_gpio *gpio = const_container_of(ptr, struct hw_gpio, base);
+ const struct hw_hpd *hpd = const_container_of(gpio, struct hw_hpd, base);
uint32_t hpd_delayed = 0;
/* in Interrupt mode we ask for SENSE bit */
Index: src/sys/external/bsd/drm2/dist/drm/amd/display/dc/hdcp/amdgpu_hdcp_msg.c
diff -u src/sys/external/bsd/drm2/dist/drm/amd/display/dc/hdcp/amdgpu_hdcp_msg.c:1.2 src/sys/external/bsd/drm2/dist/drm/amd/display/dc/hdcp/amdgpu_hdcp_msg.c:1.3
--- src/sys/external/bsd/drm2/dist/drm/amd/display/dc/hdcp/amdgpu_hdcp_msg.c:1.2 Sat Dec 18 23:45:05 2021
+++ src/sys/external/bsd/drm2/dist/drm/amd/display/dc/hdcp/amdgpu_hdcp_msg.c Sun Dec 19 12:02:39 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: amdgpu_hdcp_msg.c,v 1.2 2021/12/18 23:45:05 riastradh Exp $ */
+/* $NetBSD: amdgpu_hdcp_msg.c,v 1.3 2021/12/19 12:02:39 riastradh Exp $ */
/*
* Copyright 2019 Advanced Micro Devices, Inc.
@@ -26,7 +26,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: amdgpu_hdcp_msg.c,v 1.2 2021/12/18 23:45:05 riastradh Exp $");
+__KERNEL_RCSID(0, "$NetBSD: amdgpu_hdcp_msg.c,v 1.3 2021/12/19 12:02:39 riastradh Exp $");
#include <linux/slab.h>
@@ -121,7 +121,7 @@ struct protection_properties {
struct hdcp_protection_message *message_info);
};
-static const struct protection_properties non_supported_protection = {
+static const struct protection_properties non_supported_protection __unused = {
.supported = false
};
@@ -184,7 +184,7 @@ static bool hdmi_14_process_transaction(
return result;
}
-static const struct protection_properties hdmi_14_protection = {
+static const struct protection_properties hdmi_14_protection __unused = {
.supported = true,
.process_transaction = hdmi_14_process_transaction
};
@@ -322,7 +322,7 @@ static bool dp_11_process_transaction(
hdcp_cmd_is_read[message_info->msg_id]);
}
-static const struct protection_properties dp_11_protection = {
+static const struct protection_properties dp_11_protection __unused = {
.supported = true,
.process_transaction = dp_11_process_transaction
};
Index: src/sys/external/bsd/drm2/dist/drm/amd/display/modules/hdcp/amdgpu_hdcp1_execution.c
diff -u src/sys/external/bsd/drm2/dist/drm/amd/display/modules/hdcp/amdgpu_hdcp1_execution.c:1.2 src/sys/external/bsd/drm2/dist/drm/amd/display/modules/hdcp/amdgpu_hdcp1_execution.c:1.3
--- src/sys/external/bsd/drm2/dist/drm/amd/display/modules/hdcp/amdgpu_hdcp1_execution.c:1.2 Sat Dec 18 23:45:07 2021
+++ src/sys/external/bsd/drm2/dist/drm/amd/display/modules/hdcp/amdgpu_hdcp1_execution.c Sun Dec 19 12:02:39 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: amdgpu_hdcp1_execution.c,v 1.2 2021/12/18 23:45:07 riastradh Exp $ */
+/* $NetBSD: amdgpu_hdcp1_execution.c,v 1.3 2021/12/19 12:02:39 riastradh Exp $ */
/*
* Copyright 2019 Advanced Micro Devices, Inc.
@@ -26,7 +26,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: amdgpu_hdcp1_execution.c,v 1.2 2021/12/18 23:45:07 riastradh Exp $");
+__KERNEL_RCSID(0, "$NetBSD: amdgpu_hdcp1_execution.c,v 1.3 2021/12/19 12:02:39 riastradh Exp $");
#include "hdcp.h"
@@ -449,7 +449,7 @@ out:
uint8_t mod_hdcp_execute_and_set(
mod_hdcp_action func, uint8_t *flag,
- enum mod_hdcp_status *status, struct mod_hdcp *hdcp, char *str)
+ enum mod_hdcp_status *status, struct mod_hdcp *hdcp, const char *str)
{
*status = func(hdcp);
if (*status == MOD_HDCP_STATUS_SUCCESS && *flag != PASS) {
Index: src/sys/external/bsd/drm2/dist/drm/amd/display/modules/hdcp/amdgpu_hdcp_ddc.c
diff -u src/sys/external/bsd/drm2/dist/drm/amd/display/modules/hdcp/amdgpu_hdcp_ddc.c:1.2 src/sys/external/bsd/drm2/dist/drm/amd/display/modules/hdcp/amdgpu_hdcp_ddc.c:1.3
--- src/sys/external/bsd/drm2/dist/drm/amd/display/modules/hdcp/amdgpu_hdcp_ddc.c:1.2 Sat Dec 18 23:45:07 2021
+++ src/sys/external/bsd/drm2/dist/drm/amd/display/modules/hdcp/amdgpu_hdcp_ddc.c Sun Dec 19 12:02:39 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: amdgpu_hdcp_ddc.c,v 1.2 2021/12/18 23:45:07 riastradh Exp $ */
+/* $NetBSD: amdgpu_hdcp_ddc.c,v 1.3 2021/12/19 12:02:39 riastradh Exp $ */
/*
* Copyright 2019 Advanced Micro Devices, Inc.
@@ -26,11 +26,10 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: amdgpu_hdcp_ddc.c,v 1.2 2021/12/18 23:45:07 riastradh Exp $");
+__KERNEL_RCSID(0, "$NetBSD: amdgpu_hdcp_ddc.c,v 1.3 2021/12/19 12:02:39 riastradh Exp $");
#include "hdcp.h"
-#define MIN(a, b) ((a) < (b) ? (a) : (b))
#define HDCP_I2C_ADDR 0x3a /* 0x74 >> 1*/
#define KSV_READ_SIZE 0xf /* 0x6803b - 0x6802c */
#define HDCP_MAX_AUX_TRANSACTION_SIZE 16
Index: src/sys/external/bsd/drm2/dist/drm/amd/display/modules/hdcp/amdgpu_hdcp_log.c
diff -u src/sys/external/bsd/drm2/dist/drm/amd/display/modules/hdcp/amdgpu_hdcp_log.c:1.2 src/sys/external/bsd/drm2/dist/drm/amd/display/modules/hdcp/amdgpu_hdcp_log.c:1.3
--- src/sys/external/bsd/drm2/dist/drm/amd/display/modules/hdcp/amdgpu_hdcp_log.c:1.2 Sat Dec 18 23:45:07 2021
+++ src/sys/external/bsd/drm2/dist/drm/amd/display/modules/hdcp/amdgpu_hdcp_log.c Sun Dec 19 12:02:39 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: amdgpu_hdcp_log.c,v 1.2 2021/12/18 23:45:07 riastradh Exp $ */
+/* $NetBSD: amdgpu_hdcp_log.c,v 1.3 2021/12/19 12:02:39 riastradh Exp $ */
/*
* Copyright 2019 Advanced Micro Devices, Inc.
@@ -27,7 +27,7 @@
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: amdgpu_hdcp_log.c,v 1.2 2021/12/18 23:45:07 riastradh Exp $");
+__KERNEL_RCSID(0, "$NetBSD: amdgpu_hdcp_log.c,v 1.3 2021/12/19 12:02:39 riastradh Exp $");
#include "hdcp.h"
@@ -49,14 +49,14 @@ void mod_hdcp_dump_binary_message(uint8_
for (i = 0; i < msg_size; i++) {
if (i % bytes_per_line == 0)
buf[buf_pos++] = '\n';
- sprintf(&buf[buf_pos], "%02X ", msg[i]);
+ snprintf(&buf[buf_pos], sizeof(buf) - buf_pos, "%02X ", msg[i]);
buf_pos += byte_size;
}
buf[buf_pos++] = '\0';
}
}
-char *mod_hdcp_status_to_str(int32_t status)
+const char *mod_hdcp_status_to_str(int32_t status)
{
switch (status) {
case MOD_HDCP_STATUS_SUCCESS:
@@ -178,7 +178,7 @@ char *mod_hdcp_status_to_str(int32_t sta
}
}
-char *mod_hdcp_state_id_to_str(int32_t id)
+const char *mod_hdcp_state_id_to_str(int32_t id)
{
switch (id) {
case HDCP_UNINITIALIZED:
Index: src/sys/external/bsd/drm2/dist/drm/amd/display/modules/hdcp/hdcp.h
diff -u src/sys/external/bsd/drm2/dist/drm/amd/display/modules/hdcp/hdcp.h:1.2 src/sys/external/bsd/drm2/dist/drm/amd/display/modules/hdcp/hdcp.h:1.3
--- src/sys/external/bsd/drm2/dist/drm/amd/display/modules/hdcp/hdcp.h:1.2 Sat Dec 18 23:45:07 2021
+++ src/sys/external/bsd/drm2/dist/drm/amd/display/modules/hdcp/hdcp.h Sun Dec 19 12:02:39 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: hdcp.h,v 1.2 2021/12/18 23:45:07 riastradh Exp $ */
+/* $NetBSD: hdcp.h,v 1.3 2021/12/19 12:02:39 riastradh Exp $ */
/*
* Copyright 2019 Advanced Micro Devices, Inc.
@@ -291,7 +291,7 @@ enum mod_hdcp_hdcp2_dp_state_id {
typedef enum mod_hdcp_status (*mod_hdcp_action)(struct mod_hdcp *hdcp);
uint8_t mod_hdcp_execute_and_set(
mod_hdcp_action func, uint8_t *flag,
- enum mod_hdcp_status *status, struct mod_hdcp *hdcp, char *str);
+ enum mod_hdcp_status *status, struct mod_hdcp *hdcp, const char *str);
enum mod_hdcp_status mod_hdcp_hdcp1_execution(struct mod_hdcp *hdcp,
struct mod_hdcp_event_context *event_ctx,
struct mod_hdcp_transition_input_hdcp1 *input);
Index: src/sys/external/bsd/drm2/dist/drm/amd/display/modules/inc/mod_hdcp.h
diff -u src/sys/external/bsd/drm2/dist/drm/amd/display/modules/inc/mod_hdcp.h:1.2 src/sys/external/bsd/drm2/dist/drm/amd/display/modules/inc/mod_hdcp.h:1.3
--- src/sys/external/bsd/drm2/dist/drm/amd/display/modules/inc/mod_hdcp.h:1.2 Sat Dec 18 23:45:07 2021
+++ src/sys/external/bsd/drm2/dist/drm/amd/display/modules/inc/mod_hdcp.h Sun Dec 19 12:02:39 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: mod_hdcp.h,v 1.2 2021/12/18 23:45:07 riastradh Exp $ */
+/* $NetBSD: mod_hdcp.h,v 1.3 2021/12/19 12:02:39 riastradh Exp $ */
/*
* Copyright 2019 Advanced Micro Devices, Inc.
@@ -289,10 +289,10 @@ enum mod_hdcp_status mod_hdcp_process_ev
enum mod_hdcp_event event, struct mod_hdcp_output *output);
/* called to convert enum mod_hdcp_status to c string */
-char *mod_hdcp_status_to_str(int32_t status);
+const char *mod_hdcp_status_to_str(int32_t status);
/* called to convert state id to c string */
-char *mod_hdcp_state_id_to_str(int32_t id);
+const char *mod_hdcp_state_id_to_str(int32_t id);
/* called to convert signal type to operation mode */
enum mod_hdcp_operation_mode mod_hdcp_signal_type_to_operation_mode(
Index: src/sys/external/bsd/drm2/dist/drm/amd/powerplay/amdgpu_navi10_ppt.c
diff -u src/sys/external/bsd/drm2/dist/drm/amd/powerplay/amdgpu_navi10_ppt.c:1.2 src/sys/external/bsd/drm2/dist/drm/amd/powerplay/amdgpu_navi10_ppt.c:1.3
--- src/sys/external/bsd/drm2/dist/drm/amd/powerplay/amdgpu_navi10_ppt.c:1.2 Sat Dec 18 23:45:26 2021
+++ src/sys/external/bsd/drm2/dist/drm/amd/powerplay/amdgpu_navi10_ppt.c Sun Dec 19 12:02:39 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: amdgpu_navi10_ppt.c,v 1.2 2021/12/18 23:45:26 riastradh Exp $ */
+/* $NetBSD: amdgpu_navi10_ppt.c,v 1.3 2021/12/19 12:02:39 riastradh Exp $ */
/*
* Copyright 2019 Advanced Micro Devices, Inc.
@@ -24,7 +24,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: amdgpu_navi10_ppt.c,v 1.2 2021/12/18 23:45:26 riastradh Exp $");
+__KERNEL_RCSID(0, "$NetBSD: amdgpu_navi10_ppt.c,v 1.3 2021/12/19 12:02:39 riastradh Exp $");
#include "pp_debug.h"
#include <linux/firmware.h>
@@ -45,6 +45,10 @@ __KERNEL_RCSID(0, "$NetBSD: amdgpu_navi1
#include "asic_reg/mp/mp_11_0_sh_mask.h"
+/* XXX *@!#^@&*!#& */
+#define sprintf(buf, fmt, ...) \
+ snprintf(buf, (size_t)-1, fmt, ##__VA_ARGS__)
+
#define FEATURE_MASK(feature) (1ULL << feature)
#define SMC_DPM_FEATURE ( \
FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT) | \
@@ -1189,7 +1193,7 @@ static int navi10_get_current_activity_p
static bool navi10_is_dpm_running(struct smu_context *smu)
{
- int ret = 0;
+ int ret __unused = 0;
uint32_t feature_mask[2];
unsigned long feature_enabled;
ret = smu_feature_get_enabled_mask(smu, feature_mask, 2);
Index: src/sys/external/bsd/drm2/dist/drm/amd/powerplay/smumgr/amdgpu_fiji_smumgr.c
diff -u src/sys/external/bsd/drm2/dist/drm/amd/powerplay/smumgr/amdgpu_fiji_smumgr.c:1.2 src/sys/external/bsd/drm2/dist/drm/amd/powerplay/smumgr/amdgpu_fiji_smumgr.c:1.3
--- src/sys/external/bsd/drm2/dist/drm/amd/powerplay/smumgr/amdgpu_fiji_smumgr.c:1.2 Sat Dec 18 23:45:27 2021
+++ src/sys/external/bsd/drm2/dist/drm/amd/powerplay/smumgr/amdgpu_fiji_smumgr.c Sun Dec 19 12:02:40 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: amdgpu_fiji_smumgr.c,v 1.2 2021/12/18 23:45:27 riastradh Exp $ */
+/* $NetBSD: amdgpu_fiji_smumgr.c,v 1.3 2021/12/19 12:02:40 riastradh Exp $ */
/*
* Copyright 2015 Advanced Micro Devices, Inc.
@@ -24,7 +24,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: amdgpu_fiji_smumgr.c,v 1.2 2021/12/18 23:45:27 riastradh Exp $");
+__KERNEL_RCSID(0, "$NetBSD: amdgpu_fiji_smumgr.c,v 1.3 2021/12/19 12:02:40 riastradh Exp $");
#include "pp_debug.h"
#include "smumgr.h"
@@ -1607,7 +1607,7 @@ static int fiji_populate_smc_uvd_level(s
static int fiji_populate_smc_boot_level(struct pp_hwmgr *hwmgr,
struct SMU73_Discrete_DpmTable *table)
{
- int result = 0;
+ int result __unused = 0;
struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
table->GraphicsBootLevel = 0;
Index: src/sys/external/bsd/drm2/dist/drm/amd/powerplay/smumgr/amdgpu_iceland_smumgr.c
diff -u src/sys/external/bsd/drm2/dist/drm/amd/powerplay/smumgr/amdgpu_iceland_smumgr.c:1.2 src/sys/external/bsd/drm2/dist/drm/amd/powerplay/smumgr/amdgpu_iceland_smumgr.c:1.3
--- src/sys/external/bsd/drm2/dist/drm/amd/powerplay/smumgr/amdgpu_iceland_smumgr.c:1.2 Sat Dec 18 23:45:27 2021
+++ src/sys/external/bsd/drm2/dist/drm/amd/powerplay/smumgr/amdgpu_iceland_smumgr.c Sun Dec 19 12:02:40 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: amdgpu_iceland_smumgr.c,v 1.2 2021/12/18 23:45:27 riastradh Exp $ */
+/* $NetBSD: amdgpu_iceland_smumgr.c,v 1.3 2021/12/19 12:02:40 riastradh Exp $ */
/*
* Copyright 2016 Advanced Micro Devices, Inc.
@@ -25,7 +25,7 @@
*
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: amdgpu_iceland_smumgr.c,v 1.2 2021/12/18 23:45:27 riastradh Exp $");
+__KERNEL_RCSID(0, "$NetBSD: amdgpu_iceland_smumgr.c,v 1.3 2021/12/19 12:02:40 riastradh Exp $");
#include "pp_debug.h"
#include <linux/types.h>
@@ -2095,7 +2095,7 @@ int iceland_thermal_setup_fan_table(stru
uint32_t t_diff1, t_diff2, pwm_diff1, pwm_diff2;
uint16_t fdo_min, slope1, slope2;
uint32_t reference_clock;
- int res;
+ int res __unused;
uint64_t tmp64;
if (!phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_MicrocodeFanControl))
Index: src/sys/external/bsd/drm2/include/linux/dma-fence.h
diff -u src/sys/external/bsd/drm2/include/linux/dma-fence.h:1.13 src/sys/external/bsd/drm2/include/linux/dma-fence.h:1.14
--- src/sys/external/bsd/drm2/include/linux/dma-fence.h:1.13 Sun Dec 19 12:00:48 2021
+++ src/sys/external/bsd/drm2/include/linux/dma-fence.h Sun Dec 19 12:02:40 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: dma-fence.h,v 1.13 2021/12/19 12:00:48 riastradh Exp $ */
+/* $NetBSD: dma-fence.h,v 1.14 2021/12/19 12:02:40 riastradh Exp $ */
/*-
* Copyright (c) 2018 The NetBSD Foundation, Inc.
@@ -55,10 +55,10 @@ struct dma_fence {
const struct dma_fence_ops *ops;
int error;
ktime_t timestamp;
+ struct rcu_head rcu;
TAILQ_HEAD(, dma_fence_cb) f_callbacks;
kcondvar_t f_cv;
- struct rcu_head f_rcu;
};
#define DMA_FENCE_FLAG_ENABLE_SIGNAL_BIT 0
Index: src/sys/external/bsd/drm2/include/linux/hash.h
diff -u src/sys/external/bsd/drm2/include/linux/hash.h:1.4 src/sys/external/bsd/drm2/include/linux/hash.h:1.5
--- src/sys/external/bsd/drm2/include/linux/hash.h:1.4 Sun Dec 19 09:48:06 2021
+++ src/sys/external/bsd/drm2/include/linux/hash.h Sun Dec 19 12:02:40 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: hash.h,v 1.4 2021/12/19 09:48:06 riastradh Exp $ */
+/* $NetBSD: hash.h,v 1.5 2021/12/19 12:02:40 riastradh Exp $ */
/*-
* Copyright (c) 2013 The NetBSD Foundation, Inc.
@@ -50,4 +50,10 @@ hash_32(uint32_t value, unsigned int bit
return (value * 0x61c88647) >> (32 - bits);
}
+static inline uint64_t
+hash_64(uint64_t value, unsigned int bits)
+{
+ return (value * 0x61c8864680b583ebull) >> (64 - bits);
+}
+
#endif /* _LINUX_HASH_H_ */
Index: src/sys/external/bsd/drm2/include/linux/hashtable.h
diff -u src/sys/external/bsd/drm2/include/linux/hashtable.h:1.5 src/sys/external/bsd/drm2/include/linux/hashtable.h:1.6
--- src/sys/external/bsd/drm2/include/linux/hashtable.h:1.5 Mon Aug 27 06:39:27 2018
+++ src/sys/external/bsd/drm2/include/linux/hashtable.h Sun Dec 19 12:02:40 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: hashtable.h,v 1.5 2018/08/27 06:39:27 riastradh Exp $ */
+/* $NetBSD: hashtable.h,v 1.6 2021/12/19 12:02:40 riastradh Exp $ */
/*-
* Copyright (c) 2018 The NetBSD Foundation, Inc.
@@ -34,6 +34,7 @@
#include <sys/cdefs.h>
+#include <linux/hash.h>
#include <linux/list.h>
#define DECLARE_HASHTABLE(name, bits) \
Index: src/sys/external/bsd/drm2/include/uapi/linux/kfd_ioctl.h
diff -u src/sys/external/bsd/drm2/include/uapi/linux/kfd_ioctl.h:1.1 src/sys/external/bsd/drm2/include/uapi/linux/kfd_ioctl.h:1.2
--- src/sys/external/bsd/drm2/include/uapi/linux/kfd_ioctl.h:1.1 Sun Dec 19 10:56:23 2021
+++ src/sys/external/bsd/drm2/include/uapi/linux/kfd_ioctl.h Sun Dec 19 12:02:40 2021
@@ -0,0 +1,37 @@
+/* $NetBSD: kfd_ioctl.h,v 1.2 2021/12/19 12:02:40 riastradh Exp $ */
+
+/*-
+ * Copyright (c) 2021 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _LINUX_UAPI_KFD_IOCTL_H_
+#define _LINUX_UAPI_KFD_IOCTL_H_
+
+enum {
+ KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL = 0,
+ KFD_MMIO_REMAP_HDP_REG_FLUSH_CNTL = 4,
+};
+
+#endif /* _LINUX_UAPI_KFD_IOCTL_H_ */
Index: src/sys/external/bsd/drm2/linux/linux_dma_fence.c
diff -u src/sys/external/bsd/drm2/linux/linux_dma_fence.c:1.18 src/sys/external/bsd/drm2/linux/linux_dma_fence.c:1.19
--- src/sys/external/bsd/drm2/linux/linux_dma_fence.c:1.18 Sun Dec 19 12:00:48 2021
+++ src/sys/external/bsd/drm2/linux/linux_dma_fence.c Sun Dec 19 12:02:40 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: linux_dma_fence.c,v 1.18 2021/12/19 12:00:48 riastradh Exp $ */
+/* $NetBSD: linux_dma_fence.c,v 1.19 2021/12/19 12:02:40 riastradh Exp $ */
/*-
* Copyright (c) 2018 The NetBSD Foundation, Inc.
@@ -30,7 +30,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: linux_dma_fence.c,v 1.18 2021/12/19 12:00:48 riastradh Exp $");
+__KERNEL_RCSID(0, "$NetBSD: linux_dma_fence.c,v 1.19 2021/12/19 12:02:40 riastradh Exp $");
#include <sys/atomic.h>
#include <sys/condvar.h>
@@ -120,6 +120,8 @@ dma_fence_reset(struct dma_fence *fence,
*
* Clean up memory initialized with dma_fence_init. This is meant
* to be used after a fence release callback.
+ *
+ * XXX extension to Linux API
*/
void
dma_fence_destroy(struct dma_fence *fence)
@@ -134,7 +136,7 @@ dma_fence_destroy(struct dma_fence *fenc
static void
dma_fence_free_cb(struct rcu_head *rcu)
{
- struct dma_fence *fence = container_of(rcu, struct dma_fence, f_rcu);
+ struct dma_fence *fence = container_of(rcu, struct dma_fence, rcu);
KASSERT(!dma_fence_referenced_p(fence));
@@ -160,7 +162,7 @@ dma_fence_free(struct dma_fence *fence)
KASSERT(!dma_fence_referenced_p(fence));
- call_rcu(&fence->f_rcu, &dma_fence_free_cb);
+ call_rcu(&fence->rcu, &dma_fence_free_cb);
}
/*
