Module Name: src
Committed By: martin
Date: Fri Dec 24 13:02:25 UTC 2021
Modified Files:
src/sys/arch/x86/include [netbsd-8]: cacheinfo.h cpu.h
src/sys/arch/x86/x86 [netbsd-8]: identcpu.c identcpu_subr.c
src/usr.sbin/cpuctl/arch [netbsd-8]: cpuctl_i386.h i386.c
Log Message:
Pull up the following (all via patch), requested by msaitoh in ticket #1721:
usr.sbin/cpuctl/arch/i386.c 1.118-1.119, 1.121-1.122
usr.sbin/cpuctl/arch/cpuctl_i386.h 1.6
sys/arch/x86/x86/identcpu_subr.c 1.8-1.9
sys/arch/x86/x86/identcpu.c 1.123
sys/arch/x86/include/cacheinfo.h 1.30
sys/arch/x86/include/cpu.h 1.132
- Fix a bug that some TLB related lines were not printed.
- Fix a bug that STLB is printed as DTLB.
- If a TLB is variable sized, print the max size instead of error message.
- Cosmetic changes to improve readability.
To generate a diff of this commit:
cvs rdiff -u -r1.22.10.4 -r1.22.10.5 src/sys/arch/x86/include/cacheinfo.h
cvs rdiff -u -r1.71.2.9 -r1.71.2.10 src/sys/arch/x86/include/cpu.h
cvs rdiff -u -r1.55.2.12 -r1.55.2.13 src/sys/arch/x86/x86/identcpu.c
cvs rdiff -u -r1.7.4.2 -r1.7.4.3 src/sys/arch/x86/x86/identcpu_subr.c
cvs rdiff -u -r1.2.28.1 -r1.2.28.2 src/usr.sbin/cpuctl/arch/cpuctl_i386.h
cvs rdiff -u -r1.74.6.12 -r1.74.6.13 src/usr.sbin/cpuctl/arch/i386.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/x86/include/cacheinfo.h
diff -u src/sys/arch/x86/include/cacheinfo.h:1.22.10.4 src/sys/arch/x86/include/cacheinfo.h:1.22.10.5
--- src/sys/arch/x86/include/cacheinfo.h:1.22.10.4 Fri Aug 16 15:36:17 2019
+++ src/sys/arch/x86/include/cacheinfo.h Fri Dec 24 13:02:25 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: cacheinfo.h,v 1.22.10.4 2019/08/16 15:36:17 martin Exp $ */
+/* $NetBSD: cacheinfo.h,v 1.22.10.5 2021/12/24 13:02:25 martin Exp $ */
#ifndef _X86_CACHEINFO_H_
#define _X86_CACHEINFO_H_
@@ -222,39 +222,39 @@ __CI_TBL(CAI_DTLB2, 0x04, 4, 8, 4
__CI_TBL(CAI_DTLB2, 0x05, 4, 32, 4 * 1024 * 1024, NULL), \
__CI_TBL(CAI_ITLB2, 0x0b, 4, 4, 4 * 1024 * 1024, NULL), \
__CI_TBL(CAI_ITLB, 0x4f, 0xff, 32, 4 * 1024, NULL), \
-__CI_TBL(CAI_ITLB, 0x50, 0xff, 64, 4 * 1024, "4K/4M: 64 entries"), \
-__CI_TBL(CAI_ITLB, 0x51, 0xff, 64, 4 * 1024, "4K/4M: 128 entries"),\
-__CI_TBL(CAI_ITLB, 0x52, 0xff, 64, 4 * 1024, "4K/4M: 256 entries"),\
-__CI_TBL(CAI_ITLB2, 0x55, 0xff, 64, 4 * 1024, "2M/4M: 7 entries"), \
+__CI_TBL(CAI_ITLB, 0x50, 0xff, 64, 4 * 1024, "64 4K/4M entries"), \
+__CI_TBL(CAI_ITLB, 0x51, 0xff, 64, 4 * 1024, "128 4K/4M entries"),\
+__CI_TBL(CAI_ITLB, 0x52, 0xff, 64, 4 * 1024, "256 4K/4M entries"),\
+__CI_TBL(CAI_ITLB2, 0x55, 0xff, 64, 4 * 1024, "7 2M/4M entries"), \
__CI_TBL(CAI_DTLB2, 0x56, 4, 16, 4 * 1024 * 1024, NULL), \
__CI_TBL(CAI_DTLB, 0x57, 4, 16, 4 * 1024, NULL), \
__CI_TBL(CAI_DTLB, 0x59, 0xff, 16, 4 * 1024, NULL), \
-__CI_TBL(CAI_DTLB2, 0x5a, 0xff, 64, 4 * 1024, "2M/4M: 32 entries (L0)"), \
-__CI_TBL(CAI_DTLB, 0x5b, 0xff, 64, 4 * 1024, "4K/4M: 64 entries"), \
-__CI_TBL(CAI_DTLB, 0x5c, 0xff, 64, 4 * 1024, "4K/4M: 128 entries"),\
-__CI_TBL(CAI_DTLB, 0x5d, 0xff, 64, 4 * 1024, "4K/4M: 256 entries"),\
+__CI_TBL(CAI_DTLB2, 0x5a, 0xff, 64, 4 * 1024, "32 2M/4M entries (L0)"), \
+__CI_TBL(CAI_DTLB, 0x5b, 0xff, 64, 4 * 1024, "64 4K/4M entries"), \
+__CI_TBL(CAI_DTLB, 0x5c, 0xff, 64, 4 * 1024, "128 4K/4M entries"),\
+__CI_TBL(CAI_DTLB, 0x5d, 0xff, 64, 4 * 1024, "256 4K/4M entries"),\
__CI_TBL(CAI_ITLB, 0x61, 0xff, 48, 4 * 1024, NULL), \
__CI_TBL(CAI_L1_1GBDTLB,0x63, 4, 4,1024*1024 * 1024, NULL), \
__CI_TBL(CAI_DTLB, 0x64, 4,512, 4 * 1024, NULL), \
__CI_TBL(CAI_ITLB, 0x6a, 8, 64, 4 * 1024, NULL), \
__CI_TBL(CAI_DTLB, 0x6b, 8,256, 4 * 1024, NULL), \
-__CI_TBL(CAI_L2_DTLB2, 0x6c, 8,128, 0, "2M/4M: 128 entries"),\
+__CI_TBL(CAI_L2_DTLB2, 0x6c, 8,128, 0, "128 2M/4M entries"),\
__CI_TBL(CAI_L1_1GBDTLB,0x6d,0xff, 16,1024*1024 * 1024, NULL), \
-__CI_TBL(CAI_ITLB2, 0x76, 0xff, 8, 4 * 1024 * 1024, "2M/4M: 8 entries"), \
+__CI_TBL(CAI_ITLB2, 0x76, 0xff, 8, 4 * 1024 * 1024, "8 2M/4M entries"), \
__CI_TBL(CAI_DTLB, 0xa0, 0xff, 32, 4 * 1024, NULL), \
__CI_TBL(CAI_ITLB, 0xb0, 4,128, 4 * 1024, NULL), \
-__CI_TBL(CAI_ITLB2, 0xb1, 4, 64, 0, "8 2M/4 4M entries"), \
+__CI_TBL(CAI_ITLB2, 0xb1, 4, 64, 0, "8 2M & 4 4M entries"), \
__CI_TBL(CAI_ITLB, 0xb2, 4, 64, 4 * 1024, NULL), \
__CI_TBL(CAI_DTLB, 0xb3, 4,128, 4 * 1024, NULL), \
__CI_TBL(CAI_DTLB, 0xb4, 4,256, 4 * 1024, NULL), \
__CI_TBL(CAI_ITLB, 0xb5, 8, 64, 4 * 1024, NULL), \
__CI_TBL(CAI_ITLB, 0xb6, 8,128, 4 * 1024, NULL), \
__CI_TBL(CAI_DTLB, 0xba, 4, 64, 4 * 1024, NULL), \
-__CI_TBL(CAI_DTLB2, 0xc0, 4, 8, 4 * 1024, "4K/4M: 8 entries"), \
-__CI_TBL(CAI_L2_STLB2, 0xc1, 8,1024, 4 * 1024, "4K/2M: 1024 entries"), \
-__CI_TBL(CAI_DTLB2, 0xc2, 4, 16, 4 * 1024, "4K/2M: 16 entries"), \
+__CI_TBL(CAI_DTLB2, 0xc0, 4, 8, 4 * 1024, "8 4K/4M entries"), \
+__CI_TBL(CAI_L2_STLB2, 0xc1, 8,1024, 4 * 1024, "1024 4K/2M entries"), \
+__CI_TBL(CAI_DTLB2, 0xc2, 4, 16, 4 * 1024, "16 4K/2M entries"), \
__CI_TBL(CAI_L2_STLB, 0xc3, 6,1536, 4 * 1024, NULL), \
-__CI_TBL(CAI_DTLB2, 0xc4, 4, 32, 4 * 1024, "2M/4M: 32 entries"), \
+__CI_TBL(CAI_DTLB2, 0xc4, 4, 32, 4 * 1024, "32 2M/4M entries"), \
__CI_TBL(CAI_L2_STLB, 0xca, 4,512, 4 * 1024, NULL), \
__CI_TBL(CAI_ICACHE, 0x06, 4, 8 * 1024, 32, NULL), \
__CI_TBL(CAI_ICACHE, 0x08, 4, 16 * 1024, 32, NULL), \
@@ -357,4 +357,7 @@ __CI_TBL(0, 0x0f, 0xff, 0, 0, NULL), \
__CI_TBL(0, 0x00, 0, 0, 0, NULL) \
}
+const struct x86_cache_info *cpu_cacheinfo_lookup(
+ const struct x86_cache_info *, uint8_t);
+
#endif /* _X86_CACHEINFO_H_ */
Index: src/sys/arch/x86/include/cpu.h
diff -u src/sys/arch/x86/include/cpu.h:1.71.2.9 src/sys/arch/x86/include/cpu.h:1.71.2.10
--- src/sys/arch/x86/include/cpu.h:1.71.2.9 Wed Aug 5 16:20:08 2020
+++ src/sys/arch/x86/include/cpu.h Fri Dec 24 13:02:25 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: cpu.h,v 1.71.2.9 2020/08/05 16:20:08 martin Exp $ */
+/* $NetBSD: cpu.h,v 1.71.2.10 2021/12/24 13:02:25 martin Exp $ */
/*-
* Copyright (c) 1990 The Regents of the University of California.
@@ -453,6 +453,7 @@ void identify_hypervisor(void);
/* identcpu_subr.c */
uint64_t cpu_tsc_freq_cpuid(struct cpu_info *);
+void cpu_dcp_cacheinfo(struct cpu_info *, uint32_t);
typedef enum vm_guest {
VM_GUEST_NO = 0,
Index: src/sys/arch/x86/x86/identcpu.c
diff -u src/sys/arch/x86/x86/identcpu.c:1.55.2.12 src/sys/arch/x86/x86/identcpu.c:1.55.2.13
--- src/sys/arch/x86/x86/identcpu.c:1.55.2.12 Wed Dec 8 15:56:18 2021
+++ src/sys/arch/x86/x86/identcpu.c Fri Dec 24 13:02:25 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: identcpu.c,v 1.55.2.12 2021/12/08 15:56:18 martin Exp $ */
+/* $NetBSD: identcpu.c,v 1.55.2.13 2021/12/24 13:02:25 martin Exp $ */
/*-
* Copyright (c) 1999, 2000, 2001, 2006, 2007, 2008 The NetBSD Foundation, Inc.
@@ -30,7 +30,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: identcpu.c,v 1.55.2.12 2021/12/08 15:56:18 martin Exp $");
+__KERNEL_RCSID(0, "$NetBSD: identcpu.c,v 1.55.2.13 2021/12/24 13:02:25 martin Exp $");
#include "opt_xen.h"
@@ -91,79 +91,6 @@ static const char cpu_vendor_names[][10]
"Vortex86"
};
-static const struct x86_cache_info *
-cache_info_lookup(const struct x86_cache_info *cai, uint8_t desc)
-{
- int i;
-
- for (i = 0; cai[i].cai_desc != 0; i++) {
- if (cai[i].cai_desc == desc)
- return (&cai[i]);
- }
-
- return (NULL);
-}
-
-/*
- * Get cache info from one of the following:
- * Intel Deterministic Cache Parameter Leaf (0x04)
- * AMD Cache Topology Information Leaf (0x8000001d)
- */
-static void
-cpu_dcp_cacheinfo(struct cpu_info *ci, uint32_t leaf)
-{
- u_int descs[4];
- int type, level, ways, partitions, linesize, sets, totalsize;
- int caitype = -1;
- int i;
-
- for (i = 0; ; i++) {
- x86_cpuid2(leaf, i, descs);
- type = __SHIFTOUT(descs[0], CPUID_DCP_CACHETYPE);
- if (type == CPUID_DCP_CACHETYPE_N)
- break;
- level = __SHIFTOUT(descs[0], CPUID_DCP_CACHELEVEL);
- switch (level) {
- case 1:
- if (type == CPUID_DCP_CACHETYPE_I)
- caitype = CAI_ICACHE;
- else if (type == CPUID_DCP_CACHETYPE_D)
- caitype = CAI_DCACHE;
- else
- caitype = -1;
- break;
- case 2:
- if (type == CPUID_DCP_CACHETYPE_U)
- caitype = CAI_L2CACHE;
- else
- caitype = -1;
- break;
- case 3:
- if (type == CPUID_DCP_CACHETYPE_U)
- caitype = CAI_L3CACHE;
- else
- caitype = -1;
- break;
- default:
- caitype = -1;
- break;
- }
- if (caitype == -1)
- continue;
-
- ways = __SHIFTOUT(descs[1], CPUID_DCP_WAYS) + 1;
- partitions =__SHIFTOUT(descs[1], CPUID_DCP_PARTITIONS)
- + 1;
- linesize = __SHIFTOUT(descs[1], CPUID_DCP_LINESIZE)
- + 1;
- sets = descs[2] + 1;
- totalsize = ways * partitions * linesize * sets;
- ci->ci_cinfo[caitype].cai_totalsize = totalsize;
- ci->ci_cinfo[caitype].cai_associativity = ways;
- ci->ci_cinfo[caitype].cai_linesize = linesize;
- }
-}
-
static void
cpu_probe_intel_cache(struct cpu_info *ci)
{
@@ -186,7 +113,7 @@ cpu_probe_intel_cache(struct cpu_info *c
desc = (descs[i] >> (j * 8)) & 0xff;
if (desc == 0)
continue;
- cai = cache_info_lookup(
+ cai = cpu_cacheinfo_lookup(
intel_cpuid_cache_info, desc);
if (cai != NULL) {
ci->ci_cinfo[cai->cai_index] =
@@ -303,7 +230,7 @@ cpu_probe_amd_cache(struct cpu_info *ci)
cai->cai_associativity = AMD_L2_ECX_C_ASSOC(descs[2]);
cai->cai_linesize = AMD_L2_ECX_C_LS(descs[2]);
- cp = cache_info_lookup(amd_cpuid_l2l3cache_assoc_info,
+ cp = cpu_cacheinfo_lookup(amd_cpuid_l2l3cache_assoc_info,
cai->cai_associativity);
if (cp != NULL)
cai->cai_associativity = cp->cai_associativity;
@@ -319,7 +246,7 @@ cpu_probe_amd_cache(struct cpu_info *ci)
cai->cai_associativity = AMD_L3_EDX_C_ASSOC(descs[3]);
cai->cai_linesize = AMD_L3_EDX_C_LS(descs[3]);
- cp = cache_info_lookup(amd_cpuid_l2l3cache_assoc_info,
+ cp = cpu_cacheinfo_lookup(amd_cpuid_l2l3cache_assoc_info,
cai->cai_associativity);
if (cp != NULL)
cai->cai_associativity = cp->cai_associativity;
Index: src/sys/arch/x86/x86/identcpu_subr.c
diff -u src/sys/arch/x86/x86/identcpu_subr.c:1.7.4.2 src/sys/arch/x86/x86/identcpu_subr.c:1.7.4.3
--- src/sys/arch/x86/x86/identcpu_subr.c:1.7.4.2 Wed Aug 5 15:48:53 2020
+++ src/sys/arch/x86/x86/identcpu_subr.c Fri Dec 24 13:02:25 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: identcpu_subr.c,v 1.7.4.2 2020/08/05 15:48:53 martin Exp $ */
+/* $NetBSD: identcpu_subr.c,v 1.7.4.3 2021/12/24 13:02:25 martin Exp $ */
/*-
* Copyright (c) 2020 The NetBSD Foundation, Inc.
@@ -35,7 +35,7 @@
* See src/usr.sbin/cpuctl/{Makefile, arch/i386.c}).
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: identcpu_subr.c,v 1.7.4.2 2020/08/05 15:48:53 martin Exp $");
+__KERNEL_RCSID(0, "$NetBSD: identcpu_subr.c,v 1.7.4.3 2021/12/24 13:02:25 martin Exp $");
#ifdef _KERNEL_OPT
#include "lapic.h"
@@ -47,6 +47,7 @@ __KERNEL_RCSID(0, "$NetBSD: identcpu_sub
#include <sys/systm.h>
#include <x86/cpuvar.h>
#include <x86/apicvar.h>
+#include <x86/cacheinfo.h>
#include <machine/cpufunc.h>
#include <machine/cputypes.h>
#include <machine/specialreg.h>
@@ -56,6 +57,7 @@ __KERNEL_RCSID(0, "$NetBSD: identcpu_sub
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
+#include <x86/cacheinfo.h>
#include "cpuctl.h"
#include "cpuctl_i386.h"
#endif
@@ -69,7 +71,7 @@ cpu_tsc_freq_cpuid(struct cpu_info *ci)
if (!((ci->ci_max_cpuid >= 0x15) && (cpu_vendor == CPUVENDOR_INTEL)))
return 0;
-
+
x86_cpuid(0x15, descs);
denominator = descs[0];
numerator = descs[1];
@@ -143,3 +145,76 @@ cpu_tsc_freq_cpuid(struct cpu_info *ci)
return freq;
}
+
+const struct x86_cache_info *
+cpu_cacheinfo_lookup(const struct x86_cache_info *cai, uint8_t desc)
+{
+ int i;
+
+ for (i = 0; cai[i].cai_desc != 0; i++) {
+ if (cai[i].cai_desc == desc)
+ return &cai[i];
+ }
+
+ return NULL;
+}
+
+/*
+ * Get cache info from one of the following:
+ * Intel Deterministic Cache Parameter Leaf (0x04)
+ * AMD Cache Topology Information Leaf (0x8000001d)
+ */
+void
+cpu_dcp_cacheinfo(struct cpu_info *ci, uint32_t leaf)
+{
+ u_int descs[4];
+ int type, level, ways, partitions, linesize, sets, totalsize;
+ int caitype = -1;
+ int i;
+
+ for (i = 0; ; i++) {
+ x86_cpuid2(leaf, i, descs);
+ type = __SHIFTOUT(descs[0], CPUID_DCP_CACHETYPE);
+ if (type == CPUID_DCP_CACHETYPE_N)
+ break;
+ level = __SHIFTOUT(descs[0], CPUID_DCP_CACHELEVEL);
+ switch (level) {
+ case 1:
+ if (type == CPUID_DCP_CACHETYPE_I)
+ caitype = CAI_ICACHE;
+ else if (type == CPUID_DCP_CACHETYPE_D)
+ caitype = CAI_DCACHE;
+ else
+ caitype = -1;
+ break;
+ case 2:
+ if (type == CPUID_DCP_CACHETYPE_U)
+ caitype = CAI_L2CACHE;
+ else
+ caitype = -1;
+ break;
+ case 3:
+ if (type == CPUID_DCP_CACHETYPE_U)
+ caitype = CAI_L3CACHE;
+ else
+ caitype = -1;
+ break;
+ default:
+ caitype = -1;
+ break;
+ }
+ if (caitype == -1)
+ continue;
+
+ ways = __SHIFTOUT(descs[1], CPUID_DCP_WAYS) + 1;
+ partitions =__SHIFTOUT(descs[1], CPUID_DCP_PARTITIONS)
+ + 1;
+ linesize = __SHIFTOUT(descs[1], CPUID_DCP_LINESIZE)
+ + 1;
+ sets = descs[2] + 1;
+ totalsize = ways * partitions * linesize * sets;
+ ci->ci_cinfo[caitype].cai_totalsize = totalsize;
+ ci->ci_cinfo[caitype].cai_associativity = ways;
+ ci->ci_cinfo[caitype].cai_linesize = linesize;
+ }
+}
Index: src/usr.sbin/cpuctl/arch/cpuctl_i386.h
diff -u src/usr.sbin/cpuctl/arch/cpuctl_i386.h:1.2.28.1 src/usr.sbin/cpuctl/arch/cpuctl_i386.h:1.2.28.2
--- src/usr.sbin/cpuctl/arch/cpuctl_i386.h:1.2.28.1 Wed Aug 5 15:48:53 2020
+++ src/usr.sbin/cpuctl/arch/cpuctl_i386.h Fri Dec 24 13:02:24 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: cpuctl_i386.h,v 1.2.28.1 2020/08/05 15:48:53 martin Exp $ */
+/* $NetBSD: cpuctl_i386.h,v 1.2.28.2 2021/12/24 13:02:24 martin Exp $ */
#include <machine/specialreg.h>
#include <x86/cputypes.h>
@@ -45,6 +45,7 @@ extern int cpu_vendor;
/* For x86/x86/identcpu_subr.c */
uint64_t cpu_tsc_freq_cpuid(struct cpu_info *);
+void cpu_dcp_cacheinfo(struct cpu_info *, uint32_t);
/* Interfaces to code in i386-asm.S */
Index: src/usr.sbin/cpuctl/arch/i386.c
diff -u src/usr.sbin/cpuctl/arch/i386.c:1.74.6.12 src/usr.sbin/cpuctl/arch/i386.c:1.74.6.13
--- src/usr.sbin/cpuctl/arch/i386.c:1.74.6.12 Wed Dec 8 15:56:18 2021
+++ src/usr.sbin/cpuctl/arch/i386.c Fri Dec 24 13:02:24 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: i386.c,v 1.74.6.12 2021/12/08 15:56:18 martin Exp $ */
+/* $NetBSD: i386.c,v 1.74.6.13 2021/12/24 13:02:24 martin Exp $ */
/*-
* Copyright (c) 1999, 2000, 2001, 2006, 2007, 2008 The NetBSD Foundation, Inc.
@@ -57,7 +57,7 @@
#include <sys/cdefs.h>
#ifndef lint
-__RCSID("$NetBSD: i386.c,v 1.74.6.12 2021/12/08 15:56:18 martin Exp $");
+__RCSID("$NetBSD: i386.c,v 1.74.6.13 2021/12/24 13:02:24 martin Exp $");
#endif /* not lint */
#include <sys/types.h>
@@ -178,7 +178,6 @@ static void powernow_probe(struct cpu_in
static void intel_family_new_probe(struct cpu_info *);
static void via_cpu_probe(struct cpu_info *);
/* (Cache) Info functions */
-static void cpu_dcp_cacheinfo(struct cpu_info *, uint32_t);
static void intel_cpu_cacheinfo(struct cpu_info *);
static void amd_cpu_cacheinfo(struct cpu_info *);
static void via_cpu_cacheinfo(struct cpu_info *);
@@ -190,8 +189,6 @@ static void cpu_probe_hv_features(struct
static void cpu_probe_features(struct cpu_info *);
static void print_bits(const char *, const char *, const char *, uint32_t);
static void identifycpu_cpuids(struct cpu_info *);
-static const struct x86_cache_info *cache_info_lookup(
- const struct x86_cache_info *, uint8_t);
static const char *print_cache_config(struct cpu_info *, int, const char *,
const char *);
static const char *print_tlb_config(struct cpu_info *, int, const char *,
@@ -956,69 +953,6 @@ amd_family6_probe(struct cpu_info *ci)
}
}
-/*
- * Get cache info from one of the following:
- * Intel Deterministic Cache Parameter Leaf (0x04)
- * AMD Cache Topology Information Leaf (0x8000001d)
- */
-static void
-cpu_dcp_cacheinfo(struct cpu_info *ci, uint32_t leaf)
-{
- u_int descs[4];
- int type, level, ways, partitions, linesize, sets, totalsize;
- int caitype = -1;
- int i;
-
- for (i = 0; ; i++) {
- x86_cpuid2(leaf, i, descs);
- type = __SHIFTOUT(descs[0], CPUID_DCP_CACHETYPE);
- if (type == CPUID_DCP_CACHETYPE_N)
- break;
- level = __SHIFTOUT(descs[0], CPUID_DCP_CACHELEVEL);
- switch (level) {
- case 1:
- if (type == CPUID_DCP_CACHETYPE_I)
- caitype = CAI_ICACHE;
- else if (type == CPUID_DCP_CACHETYPE_D)
- caitype = CAI_DCACHE;
- else
- caitype = -1;
- break;
- case 2:
- if (type == CPUID_DCP_CACHETYPE_U)
- caitype = CAI_L2CACHE;
- else
- caitype = -1;
- break;
- case 3:
- if (type == CPUID_DCP_CACHETYPE_U)
- caitype = CAI_L3CACHE;
- else
- caitype = -1;
- break;
- default:
- caitype = -1;
- break;
- }
- if (caitype == -1) {
- aprint_error_dev(ci->ci_dev,
- "error: unknown cache level&type (%d & %d)\n",
- level, type);
- continue;
- }
- ways = __SHIFTOUT(descs[1], CPUID_DCP_WAYS) + 1;
- partitions =__SHIFTOUT(descs[1], CPUID_DCP_PARTITIONS)
- + 1;
- linesize = __SHIFTOUT(descs[1], CPUID_DCP_LINESIZE)
- + 1;
- sets = descs[2] + 1;
- totalsize = ways * partitions * linesize * sets;
- ci->ci_cinfo[caitype].cai_totalsize = totalsize;
- ci->ci_cinfo[caitype].cai_associativity = ways;
- ci->ci_cinfo[caitype].cai_linesize = linesize;
- }
-}
-
static void
intel_cpu_cacheinfo(struct cpu_info *ci)
{
@@ -1057,8 +991,8 @@ intel_cpu_cacheinfo(struct cpu_info *ci)
desc = (descs[i] >> (j * 8)) & 0xff;
if (desc == 0)
continue;
- cai = cache_info_lookup(intel_cpuid_cache_info,
- desc);
+ cai = cpu_cacheinfo_lookup(
+ intel_cpuid_cache_info, desc);
if (cai != NULL)
ci->ci_cinfo[cai->cai_index] = *cai;
else if ((verbose != 0) && (desc != 0xff)
@@ -1141,24 +1075,35 @@ intel_cpu_cacheinfo(struct cpu_info *ci)
else if (type == CPUID_DATP_TCTYPE_D)
caitype = CAI_L2_DTLB;
else if (type == CPUID_DATP_TCTYPE_U) {
- switch (pgsize) {
- case CPUID_DATP_PGSIZE_4KB:
+ if (pgsize == CPUID_DATP_PGSIZE_4KB)
caitype = CAI_L2_STLB;
- break;
- case CPUID_DATP_PGSIZE_4KB
- | CPUID_DATP_PGSIZE_2MB:
+ else if (pgsize == (CPUID_DATP_PGSIZE_4KB
+ | CPUID_DATP_PGSIZE_2MB))
caitype = CAI_L2_STLB2;
- break;
- case CPUID_DATP_PGSIZE_2MB
- | CPUID_DATP_PGSIZE_4MB:
+ else if (pgsize == (CPUID_DATP_PGSIZE_2MB
+ | CPUID_DATP_PGSIZE_4MB))
caitype = CAI_L2_STLB3;
- break;
- default:
- aprint_error_dev(ci->ci_dev,
- "error: unknown L2 STLB size (%d)\n",
+ else if ((pgsize & CPUID_DATP_PGSIZE_1GB)
+ != 0) {
+ /* FIXME: 1GB max TLB */
+ caitype = CAI_L2_STLB3;
+ linesize = 1024 * 1024 * 1024;
+ } else if ((pgsize & CPUID_DATP_PGSIZE_4MB)
+ != 0) {
+ /* FIXME: 4MB max TLB */
+ caitype = CAI_L2_STLB3;
+ linesize = 4 * 1024 * 1024;
+ } else if ((pgsize & CPUID_DATP_PGSIZE_2MB)
+ != 0) {
+ /* FIXME: 2MB max TLB */
+ caitype = CAI_L2_STLB2;
+ linesize = 2 * 1024 * 1024;
+ } else {
+ aprint_error_dev(ci->ci_dev, "error: "
+ "unknown L2 STLB size (%d)\n",
pgsize);
- caitype = CAI_DTLB;
- break;
+ caitype = CAI_L2_STLB;
+ linesize = 4 * 1024;
}
} else
caitype = -1;
@@ -1190,15 +1135,19 @@ intel_cpu_cacheinfo(struct cpu_info *ci)
case CPUID_DATP_PGSIZE_1GB:
linesize = 1024 * 1024 * 1024;
break;
- case CPUID_DATP_PGSIZE_2MB | CPUID_DATP_PGSIZE_4MB:
- aprint_error_dev(ci->ci_dev,
- "WARINING: Currently 2M/4M info can't print correctly\n");
- linesize = 4 * 1024 * 1024;
- break;
default:
- aprint_error_dev(ci->ci_dev,
- "error: Unknown size combination\n");
- linesize = 4 * 1024;
+ if ((pgsize & CPUID_DATP_PGSIZE_1GB) != 0)
+ linesize = 1024 * 1024 * 1024; /* MAX 1G */
+ else if ((pgsize & CPUID_DATP_PGSIZE_4MB) != 0)
+ linesize = 4 * 1024 * 1024; /* MAX 4M */
+ else if ((pgsize & CPUID_DATP_PGSIZE_2MB) != 0)
+ linesize = 2 * 1024 * 1024; /* MAX 2M */
+ else
+ linesize = 4 * 1024; /* XXX default to 4K */
+ aprint_error_dev(ci->ci_dev, "WARNING: Currently "
+ "this info can't print correctly "
+ "(level = %d, pgsize = %d)\n",
+ level, pgsize);
break;
}
ways = __SHIFTOUT(descs[1], CPUID_DATP_WAYS);
@@ -1280,7 +1229,7 @@ amd_cpu_cacheinfo(struct cpu_info *ci)
cai->cai_totalsize = AMD_L2_EBX_IUTLB_ENTRIES(descs[1]);
cai->cai_associativity = AMD_L2_EBX_IUTLB_ASSOC(descs[1]);
cai->cai_linesize = (4 * 1024);
- cp = cache_info_lookup(amd_cpuid_l2l3cache_assoc_info,
+ cp = cpu_cacheinfo_lookup(amd_cpuid_l2l3cache_assoc_info,
cai->cai_associativity);
if (cp != NULL)
cai->cai_associativity = cp->cai_associativity;
@@ -1291,7 +1240,7 @@ amd_cpu_cacheinfo(struct cpu_info *ci)
cai->cai_totalsize = AMD_L2_EAX_IUTLB_ENTRIES(descs[0]);
cai->cai_associativity = AMD_L2_EAX_IUTLB_ASSOC(descs[0]);
cai->cai_linesize = largepagesize;
- cp = cache_info_lookup(amd_cpuid_l2l3cache_assoc_info,
+ cp = cpu_cacheinfo_lookup(amd_cpuid_l2l3cache_assoc_info,
cai->cai_associativity);
if (cp != NULL)
cai->cai_associativity = cp->cai_associativity;
@@ -1302,7 +1251,7 @@ amd_cpu_cacheinfo(struct cpu_info *ci)
cai->cai_totalsize = AMD_L2_EBX_DTLB_ENTRIES(descs[1]);
cai->cai_associativity = AMD_L2_EBX_DTLB_ASSOC(descs[1]);
cai->cai_linesize = (4 * 1024);
- cp = cache_info_lookup(amd_cpuid_l2l3cache_assoc_info,
+ cp = cpu_cacheinfo_lookup(amd_cpuid_l2l3cache_assoc_info,
cai->cai_associativity);
if (cp != NULL)
cai->cai_associativity = cp->cai_associativity;
@@ -1313,7 +1262,7 @@ amd_cpu_cacheinfo(struct cpu_info *ci)
cai->cai_totalsize = AMD_L2_EAX_DTLB_ENTRIES(descs[0]);
cai->cai_associativity = AMD_L2_EAX_DTLB_ASSOC(descs[0]);
cai->cai_linesize = largepagesize;
- cp = cache_info_lookup(amd_cpuid_l2l3cache_assoc_info,
+ cp = cpu_cacheinfo_lookup(amd_cpuid_l2l3cache_assoc_info,
cai->cai_associativity);
if (cp != NULL)
cai->cai_associativity = cp->cai_associativity;
@@ -1325,7 +1274,7 @@ amd_cpu_cacheinfo(struct cpu_info *ci)
cai->cai_associativity = AMD_L2_ECX_C_ASSOC(descs[2]);
cai->cai_linesize = AMD_L2_ECX_C_LS(descs[2]);
- cp = cache_info_lookup(amd_cpuid_l2l3cache_assoc_info,
+ cp = cpu_cacheinfo_lookup(amd_cpuid_l2l3cache_assoc_info,
cai->cai_associativity);
if (cp != NULL)
cai->cai_associativity = cp->cai_associativity;
@@ -1339,7 +1288,7 @@ amd_cpu_cacheinfo(struct cpu_info *ci)
cai->cai_associativity = AMD_L3_EDX_C_ASSOC(descs[3]);
cai->cai_linesize = AMD_L3_EDX_C_LS(descs[3]);
- cp = cache_info_lookup(amd_cpuid_l2l3cache_assoc_info,
+ cp = cpu_cacheinfo_lookup(amd_cpuid_l2l3cache_assoc_info,
cai->cai_associativity);
if (cp != NULL)
cai->cai_associativity = cp->cai_associativity;
@@ -1357,7 +1306,7 @@ amd_cpu_cacheinfo(struct cpu_info *ci)
cai->cai_totalsize = AMD_L1_1GB_EAX_IUTLB_ENTRIES(descs[0]);
cai->cai_associativity = AMD_L1_1GB_EAX_IUTLB_ASSOC(descs[0]);
cai->cai_linesize = (1024 * 1024 * 1024);
- cp = cache_info_lookup(amd_cpuid_l2l3cache_assoc_info,
+ cp = cpu_cacheinfo_lookup(amd_cpuid_l2l3cache_assoc_info,
cai->cai_associativity);
if (cp != NULL)
cai->cai_associativity = cp->cai_associativity;
@@ -1368,7 +1317,7 @@ amd_cpu_cacheinfo(struct cpu_info *ci)
cai->cai_totalsize = AMD_L1_1GB_EAX_DTLB_ENTRIES(descs[0]);
cai->cai_associativity = AMD_L1_1GB_EAX_DTLB_ASSOC(descs[0]);
cai->cai_linesize = (1024 * 1024 * 1024);
- cp = cache_info_lookup(amd_cpuid_l2l3cache_assoc_info,
+ cp = cpu_cacheinfo_lookup(amd_cpuid_l2l3cache_assoc_info,
cai->cai_associativity);
if (cp != NULL)
cai->cai_associativity = cp->cai_associativity;
@@ -1379,7 +1328,7 @@ amd_cpu_cacheinfo(struct cpu_info *ci)
cai->cai_totalsize = AMD_L2_1GB_EBX_IUTLB_ENTRIES(descs[1]);
cai->cai_associativity = AMD_L2_1GB_EBX_IUTLB_ASSOC(descs[1]);
cai->cai_linesize = (1024 * 1024 * 1024);
- cp = cache_info_lookup(amd_cpuid_l2l3cache_assoc_info,
+ cp = cpu_cacheinfo_lookup(amd_cpuid_l2l3cache_assoc_info,
cai->cai_associativity);
if (cp != NULL)
cai->cai_associativity = cp->cai_associativity;
@@ -1390,7 +1339,7 @@ amd_cpu_cacheinfo(struct cpu_info *ci)
cai->cai_totalsize = AMD_L2_1GB_EBX_DUTLB_ENTRIES(descs[1]);
cai->cai_associativity = AMD_L2_1GB_EBX_DUTLB_ASSOC(descs[1]);
cai->cai_linesize = (1024 * 1024 * 1024);
- cp = cache_info_lookup(amd_cpuid_l2l3cache_assoc_info,
+ cp = cpu_cacheinfo_lookup(amd_cpuid_l2l3cache_assoc_info,
cai->cai_associativity);
if (cp != NULL)
cai->cai_associativity = cp->cai_associativity;
@@ -2279,19 +2228,6 @@ identifycpu(int fd, const char *cpuname)
ucvers.intel1.ucodeversion, ucvers.intel1.platformid);
}
-static const struct x86_cache_info *
-cache_info_lookup(const struct x86_cache_info *cai, uint8_t desc)
-{
- int i;
-
- for (i = 0; cai[i].cai_desc != 0; i++) {
- if (cai[i].cai_desc == desc)
- return (&cai[i]);
- }
-
- return (NULL);
-}
-
static const char *
print_cache_config(struct cpu_info *ci, int cache_tag, const char *name,
const char *sep)
@@ -2347,7 +2283,7 @@ print_tlb_config(struct cpu_info *ci, in
aprint_verbose_dev(ci->ci_dev, "");
else
aprint_verbose("%s", sep);
- if (name != NULL)
+ if ((name != NULL) && (sep == NULL))
aprint_verbose("%s ", name);
if (cai->cai_string != NULL) {
@@ -2382,18 +2318,18 @@ x86_print_cache_and_tlb_info(struct cpu_
if (ci->ci_cinfo[CAI_ICACHE].cai_totalsize != 0 ||
ci->ci_cinfo[CAI_DCACHE].cai_totalsize != 0) {
- sep = print_cache_config(ci, CAI_ICACHE, "I-cache", NULL);
- sep = print_cache_config(ci, CAI_DCACHE, "D-cache", sep);
+ sep = print_cache_config(ci, CAI_ICACHE, "I-cache:", NULL);
+ sep = print_cache_config(ci, CAI_DCACHE, "D-cache:", sep);
if (sep != NULL)
aprint_verbose("\n");
}
if (ci->ci_cinfo[CAI_L2CACHE].cai_totalsize != 0) {
- sep = print_cache_config(ci, CAI_L2CACHE, "L2 cache", NULL);
+ sep = print_cache_config(ci, CAI_L2CACHE, "L2 cache:", NULL);
if (sep != NULL)
aprint_verbose("\n");
}
if (ci->ci_cinfo[CAI_L3CACHE].cai_totalsize != 0) {
- sep = print_cache_config(ci, CAI_L3CACHE, "L3 cache", NULL);
+ sep = print_cache_config(ci, CAI_L3CACHE, "L3 cache:", NULL);
if (sep != NULL)
aprint_verbose("\n");
}
@@ -2403,61 +2339,36 @@ x86_print_cache_and_tlb_info(struct cpu_
if (sep != NULL)
aprint_verbose("\n");
}
- if (ci->ci_cinfo[CAI_ITLB].cai_totalsize != 0) {
- sep = print_tlb_config(ci, CAI_ITLB, "ITLB", NULL);
- sep = print_tlb_config(ci, CAI_ITLB2, NULL, sep);
- if (sep != NULL)
- aprint_verbose("\n");
- }
- if (ci->ci_cinfo[CAI_DTLB].cai_totalsize != 0) {
- sep = print_tlb_config(ci, CAI_DTLB, "DTLB", NULL);
- sep = print_tlb_config(ci, CAI_DTLB2, NULL, sep);
- if (sep != NULL)
- aprint_verbose("\n");
- }
- if (ci->ci_cinfo[CAI_L2_ITLB].cai_totalsize != 0) {
- sep = print_tlb_config(ci, CAI_L2_ITLB, "L2 ITLB", NULL);
- sep = print_tlb_config(ci, CAI_L2_ITLB2, NULL, sep);
- if (sep != NULL)
- aprint_verbose("\n");
- }
- if (ci->ci_cinfo[CAI_L2_DTLB].cai_totalsize != 0) {
- sep = print_tlb_config(ci, CAI_L2_DTLB, "L2 DTLB", NULL);
- sep = print_tlb_config(ci, CAI_L2_DTLB2, NULL, sep);
- if (sep != NULL)
- aprint_verbose("\n");
- }
- if (ci->ci_cinfo[CAI_L2_STLB].cai_totalsize != 0) {
- sep = print_tlb_config(ci, CAI_L2_STLB, "L2 STLB", NULL);
- sep = print_tlb_config(ci, CAI_L2_STLB2, NULL, sep);
- sep = print_tlb_config(ci, CAI_L2_STLB3, NULL, sep);
- if (sep != NULL)
- aprint_verbose("\n");
- }
- if (ci->ci_cinfo[CAI_L1_1GBITLB].cai_totalsize != 0) {
- sep = print_tlb_config(ci, CAI_L1_1GBITLB, "L1 1GB page ITLB",
- NULL);
- if (sep != NULL)
- aprint_verbose("\n");
- }
- if (ci->ci_cinfo[CAI_L1_1GBDTLB].cai_totalsize != 0) {
- sep = print_tlb_config(ci, CAI_L1_1GBDTLB, "L1 1GB page DTLB",
- NULL);
- if (sep != NULL)
- aprint_verbose("\n");
- }
- if (ci->ci_cinfo[CAI_L2_1GBITLB].cai_totalsize != 0) {
- sep = print_tlb_config(ci, CAI_L2_1GBITLB, "L2 1GB page ITLB",
- NULL);
- if (sep != NULL)
- aprint_verbose("\n");
- }
- if (ci->ci_cinfo[CAI_L2_1GBDTLB].cai_totalsize != 0) {
- sep = print_tlb_config(ci, CAI_L2_1GBDTLB, "L2 1GB page DTLB",
- NULL);
- if (sep != NULL)
- aprint_verbose("\n");
- }
+
+ sep = print_tlb_config(ci, CAI_ITLB, "ITLB:", NULL);
+ sep = print_tlb_config(ci, CAI_ITLB2, "ITLB:", sep);
+ sep = print_tlb_config(ci, CAI_L1_1GBITLB, "ITLB:", sep);
+ if (sep != NULL)
+ aprint_verbose("\n");
+
+ sep = print_tlb_config(ci, CAI_DTLB, "DTLB:", NULL);
+ sep = print_tlb_config(ci, CAI_DTLB2, "DTLB:", sep);
+ sep = print_tlb_config(ci, CAI_L1_1GBDTLB, "DTLB:", sep);
+ if (sep != NULL)
+ aprint_verbose("\n");
+
+ sep = print_tlb_config(ci, CAI_L2_ITLB, "L2 ITLB:", NULL);
+ sep = print_tlb_config(ci, CAI_L2_ITLB2, "L2 ITLB:", sep);
+ sep = print_tlb_config(ci, CAI_L2_1GBITLB, "L2 ITLB:", sep);
+ if (sep != NULL)
+ aprint_verbose("\n");
+
+ sep = print_tlb_config(ci, CAI_L2_DTLB, "L2 DTLB:", NULL);
+ sep = print_tlb_config(ci, CAI_L2_DTLB2, "L2 DTLB:", sep);
+ sep = print_tlb_config(ci, CAI_L2_1GBDTLB, "L2 DTLB:", sep);
+ if (sep != NULL)
+ aprint_verbose("\n");
+
+ sep = print_tlb_config(ci, CAI_L2_STLB, "L2 STLB:", NULL);
+ sep = print_tlb_config(ci, CAI_L2_STLB2, "L2 STLB:", sep);
+ sep = print_tlb_config(ci, CAI_L2_STLB3, "L2 STLB:", sep);
+ if (sep != NULL)
+ aprint_verbose("\n");
}
static void
