Module Name: src
Committed By: msaitoh
Date: Mon Jan 31 10:11:33 UTC 2022
Modified Files:
src/sys/dev/pci: pci_subr.c pcireg.h
Log Message:
Add three new extended capabilities:
- Physical Layer 32.0 GT/s
- Alternate Protocol
- System Firmware Intermediary
To generate a diff of this commit:
cvs rdiff -u -r1.239 -r1.240 src/sys/dev/pci/pci_subr.c
cvs rdiff -u -r1.163 -r1.164 src/sys/dev/pci/pcireg.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/dev/pci/pci_subr.c
diff -u src/sys/dev/pci/pci_subr.c:1.239 src/sys/dev/pci/pci_subr.c:1.240
--- src/sys/dev/pci/pci_subr.c:1.239 Sat Jan 8 12:59:34 2022
+++ src/sys/dev/pci/pci_subr.c Mon Jan 31 10:11:33 2022
@@ -1,4 +1,4 @@
-/* $NetBSD: pci_subr.c,v 1.239 2022/01/08 12:59:34 tnn Exp $ */
+/* $NetBSD: pci_subr.c,v 1.240 2022/01/31 10:11:33 msaitoh Exp $ */
/*
* Copyright (c) 1997 Zubin D. Dittia. All rights reserved.
@@ -40,7 +40,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: pci_subr.c,v 1.239 2022/01/08 12:59:34 tnn Exp $");
+__KERNEL_RCSID(0, "$NetBSD: pci_subr.c,v 1.240 2022/01/31 10:11:33 msaitoh Exp $");
#ifdef _KERNEL_OPT
#include "opt_pci.h"
@@ -4572,6 +4572,12 @@ static struct {
NULL },
{ PCI_EXTCAP_NPEM, "Native PCIe Enclosure Management",
NULL },
+ { PCI_EXTCAP_PL32G, "Physical Layer 32.0 GT/s",
+ NULL },
+ { PCI_EXTCAP_AP, "Alternate Protocol",
+ NULL },
+ { PCI_EXTCAP_SFI, "System Firmware Intermediary",
+ NULL },
};
static int
Index: src/sys/dev/pci/pcireg.h
diff -u src/sys/dev/pci/pcireg.h:1.163 src/sys/dev/pci/pcireg.h:1.164
--- src/sys/dev/pci/pcireg.h:1.163 Sat Jan 1 03:27:53 2022
+++ src/sys/dev/pci/pcireg.h Mon Jan 31 10:11:33 2022
@@ -1,4 +1,4 @@
-/* $NetBSD: pcireg.h,v 1.163 2022/01/01 03:27:53 msaitoh Exp $ */
+/* $NetBSD: pcireg.h,v 1.164 2022/01/31 10:11:33 msaitoh Exp $ */
/*
* Copyright (c) 1995, 1996, 1999, 2000
@@ -1571,6 +1571,9 @@ struct pci_rom {
#define PCI_EXTCAP_LMR 0x0027 /* Lane Margining at the Receiver */
#define PCI_EXTCAP_HIERARCHYID 0x0028 /* Hierarchy ID */
#define PCI_EXTCAP_NPEM 0x0029 /* Native PCIe Enclosure Management */
+#define PCI_EXTCAP_PL32G 0x002a /* Physical Layer 32.0 GT/s */
+#define PCI_EXTCAP_AP 0x002b /* Alternate Protocol */
+#define PCI_EXTCAP_SFI 0x002c /* System Firmware Intermediary */
/*
* Extended capability ID: 0x0001
