Module Name: src
Committed By: riastradh
Date: Mon Feb 14 08:12:48 UTC 2022
Modified Files:
src/sys/arch/hppa/dev: cpu.c
Log Message:
hppa: Membar audit in cpu.c.
To generate a diff of this commit:
cvs rdiff -u -r1.2 -r1.3 src/sys/arch/hppa/dev/cpu.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/hppa/dev/cpu.c
diff -u src/sys/arch/hppa/dev/cpu.c:1.2 src/sys/arch/hppa/dev/cpu.c:1.3
--- src/sys/arch/hppa/dev/cpu.c:1.2 Thu Apr 16 05:44:44 2020
+++ src/sys/arch/hppa/dev/cpu.c Mon Feb 14 08:12:48 2022
@@ -1,4 +1,4 @@
-/* $NetBSD: cpu.c,v 1.2 2020/04/16 05:44:44 skrll Exp $ */
+/* $NetBSD: cpu.c,v 1.3 2022/02/14 08:12:48 riastradh Exp $ */
/* $OpenBSD: cpu.c,v 1.29 2009/02/08 18:33:28 miod Exp $ */
@@ -29,7 +29,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.2 2020/04/16 05:44:44 skrll Exp $");
+__KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.3 2022/02/14 08:12:48 riastradh Exp $");
#include "opt_multiprocessor.h"
@@ -240,11 +240,26 @@ cpu_boot_secondary_processors(void)
if (ci->ci_flags & CPUF_PRIMARY)
continue;
- /* Release the specified CPU by triggering an EIR{0}. */
+ /*
+ * Release the specified CPU by triggering an EIR{0}.
+ *
+ * The `load-acquire operation' matching this
+ * store-release is somewhere inside the silicon or
+ * firmware -- the point is that the store to
+ * cpu_hatch_info must happen before writing EIR{0};
+ * there is conceptually some magic inside the silicon
+ * or firmware that effectively does
+ *
+ * if (atomic_load_acquire(&cpu->io_eir) == 0) {
+ * hw_cpu_spinup_trampoline();
+ * }
+ *
+ * so that hw_cpu_spinup_trampoline correctly sees the
+ * value we just stored at cpu_hatch_info.
+ */
cpu_hatch_info = ci;
cpu = (struct iomod *)(ci->ci_hpa);
- cpu->io_eir = 0;
- membar_sync();
+ atomic_store_release(&cpu->io_eir, 0);
/* Wait for CPU to wake up... */
j = 0;
@@ -254,9 +269,12 @@ cpu_boot_secondary_processors(void)
printf("failed to hatch cpu %i!\n", ci->ci_cpuid);
}
- /* Release secondary CPUs. */
- start_secondary_cpu = 1;
- membar_sync();
+ /*
+ * Release secondary CPUs.
+ *
+ * Matches load-acquire in cpu_hatch.
+ */
+ atomic_store_release(&start_secondary_cpu, 1);
}
void
@@ -282,8 +300,12 @@ cpu_hatch(void)
ci->ci_flags |= CPUF_RUNNING;
- /* Wait for additional CPUs to spinup. */
- while (!start_secondary_cpu)
+ /*
+ * Wait for additional CPUs to spinup.
+ *
+ * Matches store-release in cpu_boot_secondary_processors.
+ */
+ while (!atomic_load_acquire(&start_secondary_cpu))
;
/* Spin for now */
