Module Name: src
Committed By: yamaguchi
Date: Wed Mar 16 05:26:37 UTC 2022
Modified Files:
src/sys/dev/pci: if_ixl.c if_ixlvar.h
Log Message:
ixl: Added support for Intel ethernet X710-T*L
To generate a diff of this commit:
cvs rdiff -u -r1.77 -r1.78 src/sys/dev/pci/if_ixl.c
cvs rdiff -u -r1.7 -r1.8 src/sys/dev/pci/if_ixlvar.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/dev/pci/if_ixl.c
diff -u src/sys/dev/pci/if_ixl.c:1.77 src/sys/dev/pci/if_ixl.c:1.78
--- src/sys/dev/pci/if_ixl.c:1.77 Wed Jun 16 00:21:18 2021
+++ src/sys/dev/pci/if_ixl.c Wed Mar 16 05:26:37 2022
@@ -1,4 +1,4 @@
-/* $NetBSD: if_ixl.c,v 1.77 2021/06/16 00:21:18 riastradh Exp $ */
+/* $NetBSD: if_ixl.c,v 1.78 2022/03/16 05:26:37 yamaguchi Exp $ */
/*
* Copyright (c) 2013-2015, Intel Corporation
@@ -74,7 +74,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: if_ixl.c,v 1.77 2021/06/16 00:21:18 riastradh Exp $");
+__KERNEL_RCSID(0, "$NetBSD: if_ixl.c,v 1.78 2022/03/16 05:26:37 yamaguchi Exp $");
#ifdef _KERNEL_OPT
#include "opt_net_mpsafe.h"
@@ -899,12 +899,18 @@ static const struct ixl_phy_type ixl_phy
{ 1ULL << IXL_PHY_TYPE_25GBASE_LR, IFM_25G_LR },
{ 1ULL << IXL_PHY_TYPE_25GBASE_AOC, IFM_25G_AOC },
{ 1ULL << IXL_PHY_TYPE_25GBASE_ACC, IFM_25G_ACC },
+ { 1ULL << IXL_PHY_TYPE_2500BASE_T_1, IFM_2500_T },
+ { 1ULL << IXL_PHY_TYPE_5000BASE_T_1, IFM_5000_T },
+ { 1ULL << IXL_PHY_TYPE_2500BASE_T_2, IFM_2500_T },
+ { 1ULL << IXL_PHY_TYPE_5000BASE_T_2, IFM_5000_T },
};
static const struct ixl_speed_type ixl_speed_type_map[] = {
{ IXL_AQ_LINK_SPEED_40GB, IF_Gbps(40) },
{ IXL_AQ_LINK_SPEED_25GB, IF_Gbps(25) },
{ IXL_AQ_LINK_SPEED_10GB, IF_Gbps(10) },
+ { IXL_AQ_LINK_SPEED_5000MB, IF_Mbps(5000) },
+ { IXL_AQ_LINK_SPEED_2500MB, IF_Mbps(2500) },
{ IXL_AQ_LINK_SPEED_1000MB, IF_Mbps(1000) },
{ IXL_AQ_LINK_SPEED_100MB, IF_Mbps(100)},
};
@@ -949,7 +955,8 @@ static const struct ixl_product ixl_prod
{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_XL710_QSFP_A },
{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_XL710_QSFP_B },
{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_XL710_QSFP_C },
- { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_X710_10G_T },
+ { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_X710_10G_T_1 },
+ { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_X710_10G_T_2 },
{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_XL710_20G_BP_1 },
{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_XL710_20G_BP_2 },
{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_X710_T4_10G },
@@ -961,6 +968,8 @@ static const struct ixl_product ixl_prod
{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_X722_1G_BASET },
{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_X722_10G_BASET },
{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_X722_I_SFP },
+ { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_X710_10G_SFP },
+ { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_X710_10G_BP },
/* required last entry */
{0, 0}
};
@@ -1836,12 +1845,15 @@ ixl_mactype(pci_product_id_t id)
case PCI_PRODUCT_INTEL_XL710_QSFP_A:
case PCI_PRODUCT_INTEL_XL710_QSFP_B:
case PCI_PRODUCT_INTEL_XL710_QSFP_C:
- case PCI_PRODUCT_INTEL_X710_10G_T:
+ case PCI_PRODUCT_INTEL_X710_10G_T_1:
+ case PCI_PRODUCT_INTEL_X710_10G_T_2:
case PCI_PRODUCT_INTEL_XL710_20G_BP_1:
case PCI_PRODUCT_INTEL_XL710_20G_BP_2:
case PCI_PRODUCT_INTEL_X710_T4_10G:
case PCI_PRODUCT_INTEL_XXV710_25G_BP:
case PCI_PRODUCT_INTEL_XXV710_25G_SFP28:
+ case PCI_PRODUCT_INTEL_X710_10G_SFP:
+ case PCI_PRODUCT_INTEL_X710_10G_BP:
return I40E_MAC_XL710;
case PCI_PRODUCT_INTEL_X722_KX:
Index: src/sys/dev/pci/if_ixlvar.h
diff -u src/sys/dev/pci/if_ixlvar.h:1.7 src/sys/dev/pci/if_ixlvar.h:1.8
--- src/sys/dev/pci/if_ixlvar.h:1.7 Tue Sep 8 10:05:47 2020
+++ src/sys/dev/pci/if_ixlvar.h Wed Mar 16 05:26:37 2022
@@ -1,4 +1,4 @@
-/* $NetBSD: if_ixlvar.h,v 1.7 2020/09/08 10:05:47 yamaguchi Exp $ */
+/* $NetBSD: if_ixlvar.h,v 1.8 2022/03/16 05:26:37 yamaguchi Exp $ */
/*
* Copyright (c) 2019 Internet Initiative Japan, Inc.
@@ -326,12 +326,20 @@ struct ixl_aq_switch_config_element {
#define IXL_PHY_TYPE_25GBASE_AOC 0x23
#define IXL_PHY_TYPE_25GBASE_ACC 0x24
+#define IXL_PHY_TYPE_2500BASE_T_1 0x26
+#define IXL_PHY_TYPE_5000BASE_T_1 0x27
+
+#define IXL_PHY_TYPE_2500BASE_T_2 0x30
+#define IXL_PHY_TYPE_5000BASE_T_2 0x31
+
+#define IXL_PHY_LINK_SPEED_2500MB (1 << 0)
#define IXL_PHY_LINK_SPEED_100MB (1 << 1)
#define IXL_PHY_LINK_SPEED_1000MB (1 << 2)
#define IXL_PHY_LINK_SPEED_10GB (1 << 3)
#define IXL_PHY_LINK_SPEED_40GB (1 << 4)
#define IXL_PHY_LINK_SPEED_20GB (1 << 5)
#define IXL_PHY_LINK_SPEED_25GB (1 << 6)
+#define IXL_PHY_LINK_SPEED_5000MB (1 << 7)
#define IXL_PHY_ABILITY_PAUSE_TX (1 << 0)
#define IXL_PHY_ABILITY_PAUSE_RX (1 << 1)
@@ -363,6 +371,10 @@ struct ixl_aq_phy_abilities {
#define IXL_AQ_PHY_TYPE_EXT_25G_CR 0x02
#define IXL_AQ_PHY_TYPE_EXT_25G_SR 0x04
#define IXL_AQ_PHY_TYPE_EXT_25G_LR 0x08
+#define IXL_AQ_PHY_TYPE_EXT_25G_AOC 0x10
+#define IXL_AQ_PHY_TYPE_EXT_25G_ACC 0x20
+#define IXL_AQ_PHY_TYPE_EXT_2500_T 0x40
+#define IXL_AQ_PHY_TYPE_EXT_5000_T 0x80
uint8_t fec_cfg_curr_mod_ext_info;
#define IXL_AQ_ENABLE_FEC_KR 0x01
#define IXL_AQ_ENABLE_FEC_RS 0x02
@@ -669,11 +681,13 @@ struct ixl_aq_link_status { /* this occu
#define IXL_AQ_LSE_IS_ENABLED 0x1 /* only set in response */
uint8_t phy_type;
uint8_t link_speed;
+#define IXL_AQ_LINK_SPEED_2500MB (1 << 0)
#define IXL_AQ_LINK_SPEED_100MB (1 << 1)
#define IXL_AQ_LINK_SPEED_1000MB (1 << 2)
#define IXL_AQ_LINK_SPEED_10GB (1 << 3)
#define IXL_AQ_LINK_SPEED_40GB (1 << 4)
#define IXL_AQ_LINK_SPEED_25GB (1 << 6)
+#define IXL_AQ_LINK_SPEED_5000MB (1 << 7)
uint8_t link_info;
#define IXL_AQ_LINK_UP_FUNCTION 0x01
#define IXL_AQ_LINK_FAULT 0x02
