Module Name: src
Committed By: andvar
Date: Thu Mar 24 12:12:00 UTC 2022
Modified Files:
src/lib/libm/noieee_src: n_cbrt.c
src/libexec/ld.elf_so/arch/aarch64: rtld_start.S
src/sys/arch/arm/ep93xx: eprtcreg.h
Log Message:
s/interger/integer/ and s/Compensatin/Compensation/ in comments.
To generate a diff of this commit:
cvs rdiff -u -r1.6 -r1.7 src/lib/libm/noieee_src/n_cbrt.c
cvs rdiff -u -r1.4 -r1.5 src/libexec/ld.elf_so/arch/aarch64/rtld_start.S
cvs rdiff -u -r1.1 -r1.2 src/sys/arch/arm/ep93xx/eprtcreg.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/lib/libm/noieee_src/n_cbrt.c
diff -u src/lib/libm/noieee_src/n_cbrt.c:1.6 src/lib/libm/noieee_src/n_cbrt.c:1.7
--- src/lib/libm/noieee_src/n_cbrt.c:1.6 Sun Nov 24 14:49:00 2013
+++ src/lib/libm/noieee_src/n_cbrt.c Thu Mar 24 12:12:00 2022
@@ -1,4 +1,4 @@
-/* $NetBSD: n_cbrt.c,v 1.6 2013/11/24 14:49:00 martin Exp $ */
+/* $NetBSD: n_cbrt.c,v 1.7 2022/03/24 12:12:00 andvar Exp $ */
/*
* Copyright (c) 1985, 1993
* The Regents of the University of California. All rights reserved.
@@ -44,7 +44,7 @@ static char sccsid[] = "@(#)cbrt.c 8.1 (
*
* Warning: this code is semi machine dependent; the ordering of words in
* a floating point number must be known in advance. I assume that the
- * long interger at the address of a floating point number will be the
+ * long integer at the address of a floating point number will be the
* leading 32 bits of that floating point number (i.e., sign, exponent,
* and the 20 most significant bits).
* On a National machine, it has different ordering; therefore, this code
Index: src/libexec/ld.elf_so/arch/aarch64/rtld_start.S
diff -u src/libexec/ld.elf_so/arch/aarch64/rtld_start.S:1.4 src/libexec/ld.elf_so/arch/aarch64/rtld_start.S:1.5
--- src/libexec/ld.elf_so/arch/aarch64/rtld_start.S:1.4 Fri Jan 18 11:59:03 2019
+++ src/libexec/ld.elf_so/arch/aarch64/rtld_start.S Thu Mar 24 12:12:00 2022
@@ -1,4 +1,4 @@
-/* $NetBSD: rtld_start.S,v 1.4 2019/01/18 11:59:03 skrll Exp $ */
+/* $NetBSD: rtld_start.S,v 1.5 2022/03/24 12:12:00 andvar Exp $ */
/*-
* Copyright (c) 2014 The NetBSD Foundation, Inc.
@@ -60,7 +60,7 @@
#include <machine/asm.h>
-RCSID("$NetBSD: rtld_start.S,v 1.4 2019/01/18 11:59:03 skrll Exp $")
+RCSID("$NetBSD: rtld_start.S,v 1.5 2022/03/24 12:12:00 andvar Exp $")
/*
* void _rtld_start(void (*cleanup)(void), const Obj_Entry *obj,
@@ -230,7 +230,7 @@ ENTRY(_rtld_tlsdesc_dynamic)
*
*/
1:
- /* Save all interger registers */
+ /* Save all integer registers */
stp x29, x30, [sp, #-(8 * 16)]!
.cfi_adjust_cfa_offset 8 * 16
.cfi_rel_offset x29, 0
Index: src/sys/arch/arm/ep93xx/eprtcreg.h
diff -u src/sys/arch/arm/ep93xx/eprtcreg.h:1.1 src/sys/arch/arm/ep93xx/eprtcreg.h:1.2
--- src/sys/arch/arm/ep93xx/eprtcreg.h:1.1 Sat Nov 12 05:33:23 2005
+++ src/sys/arch/arm/ep93xx/eprtcreg.h Thu Mar 24 12:12:00 2022
@@ -1,4 +1,4 @@
-/* $NetBSD: eprtcreg.h,v 1.1 2005/11/12 05:33:23 hamajima Exp $ */
+/* $NetBSD: eprtcreg.h,v 1.2 2022/03/24 12:12:00 andvar Exp $ */
/*
* Copyright (c) 2005 HAMAJIMA Katsuomi. All rights reserved.
@@ -39,10 +39,10 @@
#define EP93XX_RTC_Load 0x0c /* RTC Load Register (R/W) */
#define EP93XX_RTC_Ctrl 0x10 /* RTC Control Register (R/W) */
#define EP93XX_RTC_MIE (1<<0) /* Match Interrupt Enable */
-#define EP93XX_RTC_SWComp 0x108 /* RTC Software Compensatin (R/W) */
+#define EP93XX_RTC_SWComp 0x108 /* RTC Software Compensation (R/W) */
#define EP93XX_RTC_DEL_SHIFT (1<<16) /* Number of clocks to delete */
#define EP93XX_RTC_DEL_MASK 0x001f0000
-#define EP93XX_RTC_INT_SHIFT (1<<0) /* Counter pre-load Interger value */
+#define EP93XX_RTC_INT_SHIFT (1<<0) /* Counter pre-load Integer value */
#define EP93XX_RTC_INT_MASK 0x0000ffff
#endif /* _EPRTCREG_H_ */
