Module Name: src Committed By: riastradh Date: Sat Apr 9 12:06:39 UTC 2022
Modified Files: src/common/lib/libc/arch/sparc/atomic: membar_ops.S Log Message: sparc: Fix membar_sync with LDSTUB. membar_sync is required to be a full sequential consistency barrier, equivalent to MEMBAR #StoreStore|LoadStore|StoreLoad|LoadLoad on sparcv9. LDSTUB and SWAP are the only pre-v9 instructions that do this and SWAP doesn't exist on all v7 hardware, so use LDSTUB. Note: I'm having a hard time nailing down a reference for the ordering implied by LDSTUB and SWAP. I'm _pretty sure_ SWAP has to imply store-load ordering since the SPARCv8 manual recommends it for Dekker's algorithm (which notoriously requires store-load ordering), and the formal memory model treats LDSTUB and SWAP the same for ordering. But the v8 and v9 manuals aren't clear. GCC issues STBAR and LDSTUB, but (a) I don't see why STBAR is necessary here, (b) STBAR doesn't exist on v7 so it'd be a pain to use, and (c) from what I've heard (although again it's hard to nail down authoritative references here) all actual SPARC hardware is TSO or SC anyway so STBAR is a noop in all the silicon anyway. Either way, certainly this is better than what we had before, which was nothing implying ordering at all, just a store! To generate a diff of this commit: cvs rdiff -u -r1.5 -r1.6 src/common/lib/libc/arch/sparc/atomic/membar_ops.S Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.