Module Name: src
Committed By: riastradh
Date: Sat Apr 9 12:07:29 UTC 2022
Modified Files:
src/common/lib/libc/arch/i386/atomic: atomic.S
src/common/lib/libc/arch/x86_64/atomic: atomic.S
Log Message:
x86: Add a note on membar_sync and mfence.
To generate a diff of this commit:
cvs rdiff -u -r1.32 -r1.33 src/common/lib/libc/arch/i386/atomic/atomic.S
cvs rdiff -u -r1.25 -r1.26 src/common/lib/libc/arch/x86_64/atomic/atomic.S
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/common/lib/libc/arch/i386/atomic/atomic.S
diff -u src/common/lib/libc/arch/i386/atomic/atomic.S:1.32 src/common/lib/libc/arch/i386/atomic/atomic.S:1.33
--- src/common/lib/libc/arch/i386/atomic/atomic.S:1.32 Sat Apr 9 12:07:17 2022
+++ src/common/lib/libc/arch/i386/atomic/atomic.S Sat Apr 9 12:07:29 2022
@@ -1,4 +1,4 @@
-/* $NetBSD: atomic.S,v 1.32 2022/04/09 12:07:17 riastradh Exp $ */
+/* $NetBSD: atomic.S,v 1.33 2022/04/09 12:07:29 riastradh Exp $ */
/*-
* Copyright (c) 2007 The NetBSD Foundation, Inc.
@@ -197,6 +197,12 @@ ENTRY(_membar_producer)
END(_membar_producer)
ENTRY(_membar_sync)
+ /*
+ * MFENCE, or a serializing instruction like a locked addq,
+ * is necessary to order store-before-load. Every other
+ * ordering -- load-before-anything, anything-before-store --
+ * is already guaranteed without explicit barriers.
+ */
HOTPATCH_SSE2_MFENCE
/* 7 bytes of instructions */
LOCK
Index: src/common/lib/libc/arch/x86_64/atomic/atomic.S
diff -u src/common/lib/libc/arch/x86_64/atomic/atomic.S:1.25 src/common/lib/libc/arch/x86_64/atomic/atomic.S:1.26
--- src/common/lib/libc/arch/x86_64/atomic/atomic.S:1.25 Sat Apr 9 12:07:17 2022
+++ src/common/lib/libc/arch/x86_64/atomic/atomic.S Sat Apr 9 12:07:29 2022
@@ -1,4 +1,4 @@
-/* $NetBSD: atomic.S,v 1.25 2022/04/09 12:07:17 riastradh Exp $ */
+/* $NetBSD: atomic.S,v 1.26 2022/04/09 12:07:29 riastradh Exp $ */
/*-
* Copyright (c) 2007 The NetBSD Foundation, Inc.
@@ -272,6 +272,12 @@ ENTRY(_membar_producer)
END(_membar_producer)
ENTRY(_membar_sync)
+ /*
+ * MFENCE, or a serializing instruction like a locked addq,
+ * is necessary to order store-before-load. Every other
+ * ordering -- load-before-anything, anything-before-store --
+ * is already guaranteed without explicit barriers.
+ */
HOTPATCH_SSE2_MFENCE
/* 8 bytes of instructions */
LOCK
