Module Name: src
Committed By: jmcneill
Date: Sat Apr 16 23:20:47 UTC 2022
Modified Files:
src/sys/dev/ic: dwc_eqos.c
Log Message:
eqos: Freeze counters to prevent unhandled interrupts
To generate a diff of this commit:
cvs rdiff -u -r1.5 -r1.6 src/sys/dev/ic/dwc_eqos.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/dev/ic/dwc_eqos.c
diff -u src/sys/dev/ic/dwc_eqos.c:1.5 src/sys/dev/ic/dwc_eqos.c:1.6
--- src/sys/dev/ic/dwc_eqos.c:1.5 Sun Feb 13 18:29:15 2022
+++ src/sys/dev/ic/dwc_eqos.c Sat Apr 16 23:20:47 2022
@@ -1,4 +1,4 @@
-/* $NetBSD: dwc_eqos.c,v 1.5 2022/02/13 18:29:15 riastradh Exp $ */
+/* $NetBSD: dwc_eqos.c,v 1.6 2022/04/16 23:20:47 jmcneill Exp $ */
/*-
* Copyright (c) 2022 Jared McNeill <[email protected]>
@@ -33,7 +33,7 @@
#include "opt_net_mpsafe.h"
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: dwc_eqos.c,v 1.5 2022/02/13 18:29:15 riastradh Exp $");
+__KERNEL_RCSID(0, "$NetBSD: dwc_eqos.c,v 1.6 2022/04/16 23:20:47 jmcneill Exp $");
#include <sys/param.h>
#include <sys/bus.h>
@@ -565,6 +565,12 @@ eqos_init_locked(struct eqos_softc *sc)
val |= GMAC_DMA_CHAN0_RX_CONTROL_START;
WR4(sc, GMAC_DMA_CHAN0_RX_CONTROL, val);
+ /* Disable counters */
+ WR4(sc, GMAC_MMC_CONTROL,
+ GMAC_MMC_CONTROL_CNTFREEZ |
+ GMAC_MMC_CONTROL_CNTPRST |
+ GMAC_MMC_CONTROL_CNTPRSTLVL);
+
/* Configure operation modes */
WR4(sc, GMAC_MTL_TXQ0_OPERATION_MODE,
GMAC_MTL_TXQ0_OPERATION_MODE_TSF |
