Module Name: src Committed By: msaitoh Date: Wed May 11 15:20:54 UTC 2022
Modified Files: src/sys/dev/ic: mfireg.h Log Message: KNF. s/u_quad_t/uint64_t/. No functional change. To generate a diff of this commit: cvs rdiff -u -r1.16 -r1.17 src/sys/dev/ic/mfireg.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
Modified files: Index: src/sys/dev/ic/mfireg.h diff -u src/sys/dev/ic/mfireg.h:1.16 src/sys/dev/ic/mfireg.h:1.17 --- src/sys/dev/ic/mfireg.h:1.16 Sat May 7 04:47:25 2022 +++ src/sys/dev/ic/mfireg.h Wed May 11 15:20:54 2022 @@ -1,4 +1,4 @@ -/* $NetBSD: mfireg.h,v 1.16 2022/05/07 04:47:25 msaitoh Exp $ */ +/* $NetBSD: mfireg.h,v 1.17 2022/05/11 15:20:54 msaitoh Exp $ */ /* $OpenBSD: mfireg.h,v 1.24 2006/06/19 19:05:45 marco Exp $ */ /* * Copyright (c) 2006 Marco Peereboom <ma...@peereboom.us> @@ -75,7 +75,7 @@ #define MFI_IQP 0x40 /* inbound queue port */ #define MFI_OQP 0x44 /* outbound queue port */ #define MFI_ODC 0xa0 /* outbound doorbell clr */ -#define MFI_OSP 0xb0 /* outbound scratch pad */ +#define MFI_OSP 0xb0 /* outbound scratch pad */ /* ThunderBolt specific Register */ #define MFI_RPI 0x6c /* reply_post_host_index */ @@ -357,27 +357,27 @@ typedef enum { } mfi_evt_locale_t; typedef enum { - MR_EVT_ARGS_NONE = 0x00, - MR_EVT_ARGS_CDB_SENSE, - MR_EVT_ARGS_LD, - MR_EVT_ARGS_LD_COUNT, - MR_EVT_ARGS_LD_LBA, - MR_EVT_ARGS_LD_OWNER, - MR_EVT_ARGS_LD_LBA_PD_LBA, - MR_EVT_ARGS_LD_PROG, - MR_EVT_ARGS_LD_STATE, - MR_EVT_ARGS_LD_STRIP, - MR_EVT_ARGS_PD, - MR_EVT_ARGS_PD_ERR, - MR_EVT_ARGS_PD_LBA, - MR_EVT_ARGS_PD_LBA_LD, - MR_EVT_ARGS_PD_PROG, - MR_EVT_ARGS_PD_STATE, - MR_EVT_ARGS_PCI, - MR_EVT_ARGS_RATE, - MR_EVT_ARGS_STR, - MR_EVT_ARGS_TIME, - MR_EVT_ARGS_ECC + MR_EVT_ARGS_NONE = 0x00, + MR_EVT_ARGS_CDB_SENSE, + MR_EVT_ARGS_LD, + MR_EVT_ARGS_LD_COUNT, + MR_EVT_ARGS_LD_LBA, + MR_EVT_ARGS_LD_OWNER, + MR_EVT_ARGS_LD_LBA_PD_LBA, + MR_EVT_ARGS_LD_PROG, + MR_EVT_ARGS_LD_STATE, + MR_EVT_ARGS_LD_STRIP, + MR_EVT_ARGS_PD, + MR_EVT_ARGS_PD_ERR, + MR_EVT_ARGS_PD_LBA, + MR_EVT_ARGS_PD_LBA_LD, + MR_EVT_ARGS_PD_PROG, + MR_EVT_ARGS_PD_STATE, + MR_EVT_ARGS_PCI, + MR_EVT_ARGS_RATE, + MR_EVT_ARGS_STR, + MR_EVT_ARGS_TIME, + MR_EVT_ARGS_ECC } mfi_evt_args; /* XXX should be in mfi_evt_args ? */ @@ -543,7 +543,7 @@ struct mfi_stp_frame { union { struct mfi_sg32 sg32[2]; struct mfi_sg64 sg64[2]; - } msf_sgl; + } msf_sgl; } __packed; union mfi_frame { @@ -561,9 +561,9 @@ union mfi_frame { union mfi_evt_class_locale { struct { uint16_t locale; - uint8_t reserved; + uint8_t reserved; int8_t class; - } mec_members; + } mec_members; uint32_t mec_word; }; @@ -613,12 +613,12 @@ struct mfi_evtarg_pd_address { } encl_address; } address; - uint8_t scsi_dev_type; + uint8_t scsi_dev_type; union { uint8_t port_bitmap; uint8_t port_numbers; - } connected; + } connected; uint64_t sas_addr[2]; }; @@ -641,7 +641,7 @@ struct mfi_evt_detail { uint8_t sense[64]; } __packed cdb_sense; - struct mfi_evtarg_ld ld; + struct mfi_evtarg_ld ld; struct { struct mfi_evtarg_ld ld; @@ -762,12 +762,12 @@ struct mfi_ctrl_props { uint16_t mcp_ecc_bucket_leak_rate; uint8_t mcp_restore_hotspare_on_insertion; uint8_t mcp_expose_encl_devices; - uint8_t maintainPdFailHistory; - uint8_t disallowHostRequestReordering; + uint8_t maintainPdFailHistory; + uint8_t disallowHostRequestReordering; /* set TRUE to abort CC on detecting an inconsistency */ - uint8_t abortCCOnError; + uint8_t abortCCOnError; /* load balance mode (MR_LOAD_BALANCE_MODE) */ - uint8_t loadBalanceMode; + uint8_t loadBalanceMode; /* * 0 - use auto detect logic of backplanes like SGPIO, i2c SEP using * h/w mechanism like GPIO pins @@ -775,12 +775,12 @@ struct mfi_ctrl_props { * 2 - disable i2c SEP auto detect * 3 - disable both auto detect */ - uint8_t disableAutoDetectBackplane; + uint8_t disableAutoDetectBackplane; /* * % of source LD to be reserved for a VDs snapshot in snapshot * repository, for metadata and user data: 1=5%, 2=10%, 3=15% and so on */ - uint8_t snapVDSpace; + uint8_t snapVDSpace; /* * Add properties that can be controlled by a bit in the following @@ -789,24 +789,25 @@ struct mfi_ctrl_props { struct { /* set TRUE to disable copyBack (0=copback enabled) */ uint32_t copyBackDisabled :1; - uint32_t SMARTerEnabled :1; - uint32_t prCorrectUnconfiguredAreas :1; - uint32_t useFdeOnly :1; - uint32_t disableNCQ :1; - uint32_t SSDSMARTerEnabled :1; - uint32_t SSDPatrolReadEnabled :1; - uint32_t enableSpinDownUnconfigured :1; - uint32_t autoEnhancedImport :1; - uint32_t enableSecretKeyControl :1; - uint32_t disableOnlineCtrlReset :1; + uint32_t SMARTerEnabled :1; + uint32_t prCorrectUnconfiguredAreas :1; + uint32_t useFdeOnly :1; + uint32_t disableNCQ :1; + uint32_t SSDSMARTerEnabled :1; + uint32_t SSDPatrolReadEnabled :1; + uint32_t enableSpinDownUnconfigured :1; + uint32_t autoEnhancedImport :1; + uint32_t enableSecretKeyControl :1; + uint32_t disableOnlineCtrlReset :1; uint32_t allowBootWithPinnedCache :1; - uint32_t disableSpinDownHS :1; - uint32_t enableJBOD :1; + uint32_t disableSpinDownHS :1; + uint32_t enableJBOD :1; uint32_t reserved :18; } OnOffProperties; /* * % of source LD to be reserved for auto snapshot in snapshot - * repository, for metadata and user data: 1=5%, 2=10%, 3=15% and so on. + * repository, for metadata and user data: 1=5%, 2=10%, 3=15% and so + * on. */ uint8_t autoSnapVDSpace; /* @@ -854,10 +855,10 @@ struct mfi_info_device { /* firmware component info */ struct mfi_info_component { - char mic_name[8]; - char mic_version[32]; - char mic_build_date[16]; - char mic_build_time[16]; + char mic_name[8]; + char mic_version[32]; + char mic_build_date[16]; + char mic_build_time[16]; } __packed; /* controller info from MFI_DCMD_CTRL_GETINFO. */ @@ -914,7 +915,7 @@ struct mfi_ctrl_info { #define MFI_INFO_RAID_6 0x10 uint32_t mci_adapter_ops; -#define MFI_INFO_AOPS_RBLD_RATE 0x0001 +#define MFI_INFO_AOPS_RBLD_RATE 0x0001 #define MFI_INFO_AOPS_CC_RATE 0x0002 #define MFI_INFO_AOPS_BGI_RATE 0x0004 #define MFI_INFO_AOPS_RECON_RATE 0x0008 @@ -982,7 +983,7 @@ struct mfi_ld_list { uint8_t mll_res2; uint8_t mll_res3; uint8_t mll_res4; - u_quad_t mll_size; + uint64_t mll_size; } mll_list[MFI_MAX_LD]; } __packed; @@ -1029,8 +1030,8 @@ struct mfi_ld_parm { } __packed; struct mfi_ld_span { - u_quad_t mls_start_block; - u_quad_t mls_no_blocks; + uint64_t mls_start_block; + uint64_t mls_no_blocks; uint16_t mls_index; uint8_t mls_res[6]; } __packed; @@ -1056,7 +1057,7 @@ struct mfi_ld_progress { struct mfi_ld_details { struct mfi_ld_cfg mld_cfg; - u_quad_t mld_size; + uint64_t mld_size; struct mfi_ld_progress mld_progress; uint16_t mld_clust_own_id; uint8_t mld_res1; @@ -1073,7 +1074,7 @@ struct mfi_pd_address { uint8_t mpa_enc_slot; uint8_t mpa_scsi_type; uint8_t mpa_port; - u_quad_t mpa_sas_address[2]; + uint64_t mpa_sas_address[2]; } __packed; #define MFI_MAX_PD 256 @@ -1131,11 +1132,11 @@ struct mfi_pd_details { uint8_t mpp_cnt; uint8_t mpp_severed; uint8_t mpp_res[6]; - u_quad_t mpp_sas_addr[4]; + uint64_t mpp_sas_addr[4]; } __packed mpd_path; - u_quad_t mpd_size; - u_quad_t mpd_no_coerce_size; - u_quad_t mpd_coerce_size; + uint64_t mpd_size; + uint64_t mpd_no_coerce_size; + uint64_t mpd_coerce_size; uint16_t mpd_enc_id; uint8_t mpd_enc_idx; uint8_t mpd_enc_slot; @@ -1147,7 +1148,7 @@ struct mfi_pd_details { /* array configuration from MR_DCMD_CONF_GET */ struct mfi_array { - u_quad_t mar_smallest_pd; + uint64_t mar_smallest_pd; uint8_t mar_no_disk; uint8_t mar_res1; uint16_t mar_array_ref; @@ -1194,11 +1195,11 @@ struct mfi_bbu_design_info { uint16_t spec_info; uint16_t serial_number; uint16_t pack_stat_config; - uint8_t mfg_name[12]; - uint8_t device_name[8]; - uint8_t device_chemistry[8]; - uint8_t mfg_data[8]; - uint8_t reserved[17]; + uint8_t mfg_name[12]; + uint8_t device_name[8]; + uint8_t device_chemistry[8]; + uint8_t mfg_data[8]; + uint8_t reserved[17]; } __packed; struct mfi_ibbu_state { @@ -1224,15 +1225,15 @@ struct mfi_bbu_state { union mfi_bbu_status_detail { struct mfi_ibbu_state ibbu; - struct mfi_bbu_state bbu; + struct mfi_bbu_state bbu; }; /* informations from MR_DCMD_BBU_GET_STATUS */ struct mfi_bbu_status { uint8_t battery_type; -#define MFI_BBU_TYPE_NONE 0 -#define MFI_BBU_TYPE_IBBU 1 -#define MFI_BBU_TYPE_BBU 2 +#define MFI_BBU_TYPE_NONE 0 +#define MFI_BBU_TYPE_IBBU 1 +#define MFI_BBU_TYPE_BBU 2 uint8_t reserved; uint16_t voltage; int16_t current; @@ -1251,18 +1252,18 @@ struct mfi_bbu_status { #define MFI_BBU_STATE_REPLACE_PACK (1 << 10) #define MFI_BBU_STATE_CAPACITY_LOW (1 << 11) #define MFI_BBU_STATE_LEARN_REQUIRED (1 << 12) -#define MFI_BBU_STATE_BAD_IBBU ( \ - MFI_BBU_STATE_PACK_MISSING | \ - MFI_BBU_STATE_VOLTAGE_LOW | \ - MFI_BBU_STATE_DISCHARGE_ACTIVE | \ - MFI_BBU_STATE_LEARN_CYC_REQ | \ - MFI_BBU_STATE_LEARN_CYC_ACTIVE | \ - MFI_BBU_STATE_REPLACE_PACK | \ - MFI_BBU_STATE_CAPACITY_LOW) -#define MFI_BBU_STATE_BAD_BBU ( \ - MFI_BBU_STATE_PACK_MISSING | \ - MFI_BBU_STATE_REPLACE_PACK | \ - MFI_BBU_STATE_CAPACITY_LOW) +#define MFI_BBU_STATE_BAD_IBBU ( \ + MFI_BBU_STATE_PACK_MISSING | \ + MFI_BBU_STATE_VOLTAGE_LOW | \ + MFI_BBU_STATE_DISCHARGE_ACTIVE | \ + MFI_BBU_STATE_LEARN_CYC_REQ | \ + MFI_BBU_STATE_LEARN_CYC_ACTIVE | \ + MFI_BBU_STATE_REPLACE_PACK | \ + MFI_BBU_STATE_CAPACITY_LOW) +#define MFI_BBU_STATE_BAD_BBU ( \ + MFI_BBU_STATE_PACK_MISSING | \ + MFI_BBU_STATE_REPLACE_PACK | \ + MFI_BBU_STATE_CAPACITY_LOW) uint8_t pad[20]; union mfi_bbu_status_detail detail; } __packed; @@ -1334,40 +1335,40 @@ typedef struct _mpi2_scsi_io_vendor_uniq * *****************************************************************************/ -#define NA_MPI2_FUNCTION_SCSI_IO_REQUEST (0x00) /* SCSI IO */ -#define MPI2_FUNCTION_SCSI_TASK_MGMT (0x01) /* SCSI Task Management */ -#define MPI2_FUNCTION_IOC_INIT (0x02) /* IOC Init */ -#define MPI2_FUNCTION_IOC_FACTS (0x03) /* IOC Facts */ -#define MPI2_FUNCTION_CONFIG (0x04) /* Configuration */ -#define MPI2_FUNCTION_PORT_FACTS (0x05) /* Port Facts */ -#define MPI2_FUNCTION_PORT_ENABLE (0x06) /* Port Enable */ -#define MPI2_FUNCTION_EVENT_NOTIFICATION (0x07) /* Event Notification */ -#define MPI2_FUNCTION_EVENT_ACK (0x08) /* Event Acknowledge */ -#define MPI2_FUNCTION_FW_DOWNLOAD (0x09) /* FW Download */ -#define MPI2_FUNCTION_TARGET_ASSIST (0x0B) /* Target Assist */ -#define MPI2_FUNCTION_TARGET_STATUS_SEND (0x0C) /* Target Status Send */ -#define MPI2_FUNCTION_TARGET_MODE_ABORT (0x0D) /* Target Mode Abort */ -#define MPI2_FUNCTION_FW_UPLOAD (0x12) /* FW Upload */ -#define MPI2_FUNCTION_RAID_ACTION (0x15) /* RAID Action */ -#define MPI2_FUNCTION_RAID_SCSI_IO_PASSTHROUGH (0x16) /* SCSI IO RAID Passthrough */ -#define MPI2_FUNCTION_TOOLBOX (0x17) /* Toolbox */ -#define MPI2_FUNCTION_SCSI_ENCLOSURE_PROCESSOR (0x18) /* SCSI Enclosure Processor */ -#define MPI2_FUNCTION_SMP_PASSTHROUGH (0x1A) /* SMP Passthrough */ -#define MPI2_FUNCTION_SAS_IO_UNIT_CONTROL (0x1B) /* SAS IO Unit Control */ -#define MPI2_FUNCTION_SATA_PASSTHROUGH (0x1C) /* SATA Passthrough */ -#define MPI2_FUNCTION_DIAG_BUFFER_POST (0x1D) /* Diagnostic Buffer Post */ -#define MPI2_FUNCTION_DIAG_RELEASE (0x1E) /* Diagnostic Release */ -#define MPI2_FUNCTION_TARGET_CMD_BUF_BASE_POST (0x24) /* Target Command Buffer Post Base */ -#define MPI2_FUNCTION_TARGET_CMD_BUF_LIST_POST (0x25) /* Target Command Buffer Post List */ -#define MPI2_FUNCTION_RAID_ACCELERATOR (0x2C) /* RAID Accelerator */ -#define MPI2_FUNCTION_HOST_BASED_DISCOVERY_ACTION (0x2F) /* Host Based Discovery Action */ -#define MPI2_FUNCTION_PWR_MGMT_CONTROL (0x30) /* Power Management Control */ -#define MPI2_FUNCTION_MIN_PRODUCT_SPECIFIC (0xF0) /* beginning of product-specific range */ -#define MPI2_FUNCTION_MAX_PRODUCT_SPECIFIC (0xFF) /* end of product-specific range */ +#define NA_MPI2_FUNCTION_SCSI_IO_REQUEST (0x00) /* SCSI IO */ +#define MPI2_FUNCTION_SCSI_TASK_MGMT (0x01) /* SCSI Task Management */ +#define MPI2_FUNCTION_IOC_INIT (0x02) /* IOC Init */ +#define MPI2_FUNCTION_IOC_FACTS (0x03) /* IOC Facts */ +#define MPI2_FUNCTION_CONFIG (0x04) /* Configuration */ +#define MPI2_FUNCTION_PORT_FACTS (0x05) /* Port Facts */ +#define MPI2_FUNCTION_PORT_ENABLE (0x06) /* Port Enable */ +#define MPI2_FUNCTION_EVENT_NOTIFICATION (0x07) /* Event Notification */ +#define MPI2_FUNCTION_EVENT_ACK (0x08) /* Event Acknowledge */ +#define MPI2_FUNCTION_FW_DOWNLOAD (0x09) /* FW Download */ +#define MPI2_FUNCTION_TARGET_ASSIST (0x0B) /* Target Assist */ +#define MPI2_FUNCTION_TARGET_STATUS_SEND (0x0C) /* Target Status Send */ +#define MPI2_FUNCTION_TARGET_MODE_ABORT (0x0D) /* Target Mode Abort */ +#define MPI2_FUNCTION_FW_UPLOAD (0x12) /* FW Upload */ +#define MPI2_FUNCTION_RAID_ACTION (0x15) /* RAID Action */ +#define MPI2_FUNCTION_RAID_SCSI_IO_PASSTHROUGH (0x16) /* SCSI IO RAID Passthrough */ +#define MPI2_FUNCTION_TOOLBOX (0x17) /* Toolbox */ +#define MPI2_FUNCTION_SCSI_ENCLOSURE_PROCESSOR (0x18) /* SCSI Enclosure Processor */ +#define MPI2_FUNCTION_SMP_PASSTHROUGH (0x1A) /* SMP Passthrough */ +#define MPI2_FUNCTION_SAS_IO_UNIT_CONTROL (0x1B) /* SAS IO Unit Control */ +#define MPI2_FUNCTION_SATA_PASSTHROUGH (0x1C) /* SATA Passthrough */ +#define MPI2_FUNCTION_DIAG_BUFFER_POST (0x1D) /* Diagnostic Buffer Post */ +#define MPI2_FUNCTION_DIAG_RELEASE (0x1E) /* Diagnostic Release */ +#define MPI2_FUNCTION_TARGET_CMD_BUF_BASE_POST (0x24) /* Target Command Buffer Post Base */ +#define MPI2_FUNCTION_TARGET_CMD_BUF_LIST_POST (0x25) /* Target Command Buffer Post List */ +#define MPI2_FUNCTION_RAID_ACCELERATOR (0x2C) /* RAID Accelerator */ +#define MPI2_FUNCTION_HOST_BASED_DISCOVERY_ACTION (0x2F) /* Host Based Discovery Action */ +#define MPI2_FUNCTION_PWR_MGMT_CONTROL (0x30) /* Power Management Control */ +#define MPI2_FUNCTION_MIN_PRODUCT_SPECIFIC (0xF0) /* beginning of product-specific range */ +#define MPI2_FUNCTION_MAX_PRODUCT_SPECIFIC (0xFF) /* end of product-specific range */ /* Doorbell functions */ -#define MPI2_FUNCTION_IOC_MESSAGE_UNIT_RESET (0x40) -#define MPI2_FUNCTION_HANDSHAKE (0x42) +#define MPI2_FUNCTION_IOC_MESSAGE_UNIT_RESET (0x40) +#define MPI2_FUNCTION_HANDSHAKE (0x42) /***************************************************************************** *