Module Name: src
Committed By: ryo
Date: Sun May 29 23:39:59 UTC 2022
Modified Files:
src/sys/arch/aarch64/aarch64: idle_machdep.S vectors.S
Log Message:
ESR_EL1 and FAR_EL1 are not required in interrupt trapframe and their values
are meaningless.
To identify it as an interrupt trap frame, store -1 and 0.
To generate a diff of this commit:
cvs rdiff -u -r1.11 -r1.12 src/sys/arch/aarch64/aarch64/idle_machdep.S
cvs rdiff -u -r1.26 -r1.27 src/sys/arch/aarch64/aarch64/vectors.S
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/aarch64/aarch64/idle_machdep.S
diff -u src/sys/arch/aarch64/aarch64/idle_machdep.S:1.11 src/sys/arch/aarch64/aarch64/idle_machdep.S:1.12
--- src/sys/arch/aarch64/aarch64/idle_machdep.S:1.11 Sun Oct 10 08:59:45 2021
+++ src/sys/arch/aarch64/aarch64/idle_machdep.S Sun May 29 23:39:59 2022
@@ -1,4 +1,4 @@
-/* $NetBSD: idle_machdep.S,v 1.11 2021/10/10 08:59:45 skrll Exp $ */
+/* $NetBSD: idle_machdep.S,v 1.12 2022/05/29 23:39:59 ryo Exp $ */
/*-
* Copyright (c) 2014 The NetBSD Foundation, Inc.
@@ -36,7 +36,7 @@
#include <aarch64/locore.h>
#include "assym.h"
-RCSID("$NetBSD: idle_machdep.S,v 1.11 2021/10/10 08:59:45 skrll Exp $");
+RCSID("$NetBSD: idle_machdep.S,v 1.12 2022/05/29 23:39:59 ryo Exp $");
#ifdef ARM_INTR_IMPL
#include ARM_INTR_IMPL
@@ -68,6 +68,9 @@ ENTRY(cpu_idle)
stp x29, x30, [sp, #TF_X29] /* save x29,x30 */
#ifdef DDB
add x29, sp, #TF_X29 /* link frame for backtrace */
+ mov x0, #-1
+ str x0, [sp, #TF_ESR]
+ str xzr, [sp, #TF_FAR]
#endif
/* fill the minimum required trapframe */
Index: src/sys/arch/aarch64/aarch64/vectors.S
diff -u src/sys/arch/aarch64/aarch64/vectors.S:1.26 src/sys/arch/aarch64/aarch64/vectors.S:1.27
--- src/sys/arch/aarch64/aarch64/vectors.S:1.26 Fri May 6 06:09:50 2022
+++ src/sys/arch/aarch64/aarch64/vectors.S Sun May 29 23:39:59 2022
@@ -1,4 +1,4 @@
-/* $NetBSD: vectors.S,v 1.26 2022/05/06 06:09:50 ryo Exp $ */
+/* $NetBSD: vectors.S,v 1.27 2022/05/29 23:39:59 ryo Exp $ */
#include <aarch64/asm.h>
#include <aarch64/locore.h>
@@ -11,7 +11,7 @@
#include "opt_dtrace.h"
#include "opt_gic.h"
-RCSID("$NetBSD: vectors.S,v 1.26 2022/05/06 06:09:50 ryo Exp $")
+RCSID("$NetBSD: vectors.S,v 1.27 2022/05/29 23:39:59 ryo Exp $")
ARMV8_DEFINE_OPTIONS
@@ -29,7 +29,7 @@ RCSID("$NetBSD: vectors.S,v 1.26 2022/05
/*
* Template for the handler functions.
*/
-.macro vector_func, func, el, label, tpidr
+.macro vector_func, func, el, intr_p, label, tpidr
.align 7 /* cacheline-aligned */
ENTRY_NBTI(\func)
@@ -76,8 +76,13 @@ ENTRY_NBTI(\func)
mrs x22, spsr_el1
str x22, [sp, #TF_SPSR]
+ .if \intr_p == 1
+ mov x23, #-1
+ mov x24, xzr
+ .else
mrs x23, esr_el1
mrs x24, far_el1
+ .endif
.if TF_ESR + 8 == TF_FAR
stp x23, x24, [sp, #TF_ESR]
@@ -126,25 +131,25 @@ END(\func)
/*
* The functions.
*/
-vector_func el1t_sync_handler, 1, trap_el1t_sync
-vector_func el1t_irq_handler, 1, trap_el1t_irq
-vector_func el1t_fiq_handler, 1, trap_el1t_fiq
-vector_func el1t_error_handler, 1, trap_el1t_error
-
-vector_func el1h_sync_handler, 1, trap_el1h_sync
-vector_func el1h_intr_handler, 1, cpu_irq
-vector_func el1h_fiq_handler, 1, cpu_fiq
-vector_func el1h_error_handler, 1, trap_el1h_error
-
-vector_func el0_sync_handler, 0, trap_el0_sync
-vector_func el0_intr_handler, 0, cpu_irq
-vector_func el0_fiq_handler, 0, cpu_fiq
-vector_func el0_error_handler, 0, trap_el0_error
-
-vector_func el0_32sync_handler, 0, trap_el0_32sync, ro
-vector_func el0_32intr_handler, 0, cpu_irq, ro
-vector_func el0_32fiq_handler, 0, cpu_fiq, ro
-vector_func el0_32error_handler, 0, trap_el0_32error, ro
+vector_func el1t_sync_handler, 1, 0, trap_el1t_sync
+vector_func el1t_irq_handler, 1, 1, trap_el1t_irq
+vector_func el1t_fiq_handler, 1, 1, trap_el1t_fiq
+vector_func el1t_error_handler, 1, 0, trap_el1t_error
+
+vector_func el1h_sync_handler, 1, 0, trap_el1h_sync
+vector_func el1h_intr_handler, 1, 1, cpu_irq
+vector_func el1h_fiq_handler, 1, 1, cpu_fiq
+vector_func el1h_error_handler, 1, 0, trap_el1h_error
+
+vector_func el0_sync_handler, 0, 0, trap_el0_sync
+vector_func el0_intr_handler, 0, 1, cpu_irq
+vector_func el0_fiq_handler, 0, 1, cpu_fiq
+vector_func el0_error_handler, 0, 0, trap_el0_error
+
+vector_func el0_32sync_handler, 0, 0, trap_el0_32sync, ro
+vector_func el0_32intr_handler, 0, 1, cpu_irq, ro
+vector_func el0_32fiq_handler, 0, 1, cpu_fiq, ro
+vector_func el0_32error_handler, 0, 0, trap_el0_32error, ro
/*
* The vector table. Must be aligned to 2048.
