Module Name: src
Committed By: skrll
Date: Sun Jun 26 14:37:13 UTC 2022
Modified Files:
src/lib/libc/arch/hppa: genassym.cf
src/lib/libc/arch/hppa/sys: __sigtramp2.S
src/sys/arch/hppa/include: mcontext.h
Log Message:
Decorate the HPPA signal trampoline with the appropriate .cfi
directives to allow exception unwind / backtrace across a signal
handler.
To generate a diff of this commit:
cvs rdiff -u -r1.3 -r1.4 src/lib/libc/arch/hppa/genassym.cf
cvs rdiff -u -r1.6 -r1.7 src/lib/libc/arch/hppa/sys/__sigtramp2.S
cvs rdiff -u -r1.11 -r1.12 src/sys/arch/hppa/include/mcontext.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/lib/libc/arch/hppa/genassym.cf
diff -u src/lib/libc/arch/hppa/genassym.cf:1.3 src/lib/libc/arch/hppa/genassym.cf:1.4
--- src/lib/libc/arch/hppa/genassym.cf:1.3 Sat Oct 24 07:05:52 2020
+++ src/lib/libc/arch/hppa/genassym.cf Sun Jun 26 14:37:12 2022
@@ -1,4 +1,4 @@
-# $NetBSD: genassym.cf,v 1.3 2020/10/24 07:05:52 skrll Exp $
+# $NetBSD: genassym.cf,v 1.4 2022/06/26 14:37:12 skrll Exp $
#
# Copyright (c) 2014 The NetBSD Foundation, Inc.
@@ -30,12 +30,48 @@
#
include <sys/types.h>
+include <signal.h>
include <ucontext.h>
+include <machine/frame.h>
+define _REG_R1 _REG_R1
+define _REG_R2 _REG_R2
+define _REG_R3 _REG_R3
+define _REG_R4 _REG_R4
+define _REG_R5 _REG_R5
+define _REG_R6 _REG_R6
+define _REG_R7 _REG_R7
+define _REG_R8 _REG_R8
+define _REG_R9 _REG_R9
+define _REG_R10 _REG_R10
+define _REG_R11 _REG_R11
+define _REG_R12 _REG_R12
+define _REG_R13 _REG_R13
+define _REG_R14 _REG_R14
+define _REG_R15 _REG_R15
+define _REG_R16 _REG_R16
+define _REG_R17 _REG_R17
+define _REG_R18 _REG_R18
+define _REG_R19 _REG_R19
+define _REG_R20 _REG_R20
+define _REG_R21 _REG_R21
+define _REG_R22 _REG_R22
+define _REG_R23 _REG_R23
+define _REG_R24 _REG_R24
+define _REG_R25 _REG_R25
+define _REG_R26 _REG_R26
+define _REG_R27 _REG_R27
+define _REG_R28 _REG_R28
+define _REG_R29 _REG_R29
+define _REG_R30 _REG_R30
+define _REG_R31 _REG_R31
define _REG_PCOQH _REG_PCOQH
define _REG_PCOQT _REG_PCOQT
define _REG_RET0 _REG_RET0
+define SIZEOF_SIGTRAMP HPPA_FRAME_ROUND(sizeof(siginfo_t) + sizeof(ucontext_t))
+define SIZEOF_SIGINFO sizeof(siginfo_t)
+
define _UC_GREGS offsetof(ucontext_t, uc_mcontext.__gregs[0])
define _UC_GREGS_R1 offsetof(ucontext_t, uc_mcontext.__gregs[1])
define _UC_GREGS_R2 offsetof(ucontext_t, uc_mcontext.__gregs[2])
Index: src/lib/libc/arch/hppa/sys/__sigtramp2.S
diff -u src/lib/libc/arch/hppa/sys/__sigtramp2.S:1.6 src/lib/libc/arch/hppa/sys/__sigtramp2.S:1.7
--- src/lib/libc/arch/hppa/sys/__sigtramp2.S:1.6 Tue May 5 06:20:55 2020
+++ src/lib/libc/arch/hppa/sys/__sigtramp2.S Sun Jun 26 14:37:13 2022
@@ -1,4 +1,4 @@
-/* $NetBSD: __sigtramp2.S,v 1.6 2020/05/05 06:20:55 skrll Exp $ */
+/* $NetBSD: __sigtramp2.S,v 1.7 2022/06/26 14:37:13 skrll Exp $ */
/*
* Copyright (c) 1998-2001 Michael Shalayeff
@@ -57,6 +57,7 @@
*/
#include "SYS.h"
+#include "assym.h"
/*
* The hppa signal trampoline is required to call the handler
@@ -76,8 +77,68 @@
* siginfo_t sf_si;
* ucontext_t sf_uc;
* };
+ *
+ * The DWARF register numbers for the general purpose registers are the
+ * same as the architected register numbers. For HPPA, there is a DWARF
+ * pseudo-register for signal handler return addresses.
*/
+#if defined(__LIBGCC_DWARF_ALT_FRAME_RETURN_COLUMN__)
+#define DWARF_SIGRETURN_REG __LIBGCC_DWARF_ALT_FRAME_RETURN_COLUMN__
+#else
+#define DWARF_SIGRETURN_REG 89 /* 61 on hppa64 */
+#endif
+
+#define CFI_OFFSET_DWARF_REG(d, r) .cfi_offset d, r * 4
+#define CFI_OFFSET(r) CFI_OFFSET_DWARF_REG(r, r)
+
+ .text
+ .cfi_startproc
+ .cfi_signal_frame
+ .cfi_def_cfa _REG_R30, -SIZEOF_SIGTRAMP + SIZEOF_SIGINFO + _UC_GREGS
+ CFI_OFFSET(_REG_R1)
+ CFI_OFFSET(_REG_R2)
+ CFI_OFFSET(_REG_R3)
+ CFI_OFFSET(_REG_R4)
+ CFI_OFFSET(_REG_R5)
+ CFI_OFFSET(_REG_R6)
+ CFI_OFFSET(_REG_R7)
+ CFI_OFFSET(_REG_R8)
+ CFI_OFFSET(_REG_R9)
+ CFI_OFFSET(_REG_R10)
+ CFI_OFFSET(_REG_R11)
+ CFI_OFFSET(_REG_R12)
+ CFI_OFFSET(_REG_R13)
+ CFI_OFFSET(_REG_R14)
+ CFI_OFFSET(_REG_R15)
+ CFI_OFFSET(_REG_R16)
+ CFI_OFFSET(_REG_R17)
+ CFI_OFFSET(_REG_R18)
+ CFI_OFFSET(_REG_R19)
+ CFI_OFFSET(_REG_R20)
+ CFI_OFFSET(_REG_R21)
+ CFI_OFFSET(_REG_R22)
+ CFI_OFFSET(_REG_R23)
+ CFI_OFFSET(_REG_R24)
+ CFI_OFFSET(_REG_R25)
+ CFI_OFFSET(_REG_R26)
+ CFI_OFFSET(_REG_R27)
+ CFI_OFFSET(_REG_R28)
+ CFI_OFFSET(_REG_R29)
+ CFI_OFFSET(_REG_R30)
+ CFI_OFFSET(_REG_R31)
+ .cfi_return_column DWARF_SIGRETURN_REG
+ CFI_OFFSET_DWARF_REG(DWARF_SIGRETURN_REG, _REG_PCOQH)
+
+/*
+ * The unwind entry includes one instruction slot prior to the trampoline
+ * because the unwinder will look up to (return PC - 1 insn) while unwinding.
+ * Normally this would be the jump / branch, but since there isn't one in
+ * this case, we place an explicit nop there instead.
+ */
+
+ nop
+
ENTRY_NOPROFILE(__sigtramp_siginfo_2, 0)
.call
@@ -130,4 +191,5 @@ L$sigcode_bounce:
.call
ble 4(%sr2, %r1)
ldi SYS_exit, %t1
+ .cfi_endproc
EXIT(__sigtramp_siginfo_2)
Index: src/sys/arch/hppa/include/mcontext.h
diff -u src/sys/arch/hppa/include/mcontext.h:1.11 src/sys/arch/hppa/include/mcontext.h:1.12
--- src/sys/arch/hppa/include/mcontext.h:1.11 Fri Dec 27 00:32:17 2019
+++ src/sys/arch/hppa/include/mcontext.h Sun Jun 26 14:37:13 2022
@@ -1,4 +1,4 @@
-/* $NetBSD: mcontext.h,v 1.11 2019/12/27 00:32:17 kamil Exp $ */
+/* $NetBSD: mcontext.h,v 1.12 2022/06/26 14:37:13 skrll Exp $ */
#ifndef _HPPA_MCONTEXT_H_
#define _HPPA_MCONTEXT_H_
@@ -8,6 +8,38 @@
*/
#define _NGREG 44
+#define _REG_R1 1
+#define _REG_R2 2
+#define _REG_R3 3
+#define _REG_R4 4
+#define _REG_R5 5
+#define _REG_R6 6
+#define _REG_R7 7
+#define _REG_R8 8
+#define _REG_R9 9
+#define _REG_R10 10
+#define _REG_R11 11
+#define _REG_R12 12
+#define _REG_R13 13
+#define _REG_R14 14
+#define _REG_R15 15
+#define _REG_R16 16
+#define _REG_R17 17
+#define _REG_R18 18
+#define _REG_R19 19
+#define _REG_R20 20
+#define _REG_R21 21
+#define _REG_R22 22
+#define _REG_R23 23
+#define _REG_R24 24
+#define _REG_R25 25
+#define _REG_R26 26
+#define _REG_R27 27
+#define _REG_R28 28
+#define _REG_R29 29
+#define _REG_R30 30
+#define _REG_R31 31
+
#define _REG_PSW 0
#define _REG_RP 2
#define _REG_R19 19
