Module Name:    src
Committed By:   msaitoh
Date:           Wed Jun 29 13:03:20 UTC 2022

Modified Files:
        src/sys/dev/ic: mfireg.h
        src/sys/dev/pci: mfii.c

Log Message:
Add CVPM02 BBU support.


To generate a diff of this commit:
cvs rdiff -u -r1.21 -r1.22 src/sys/dev/ic/mfireg.h
cvs rdiff -u -r1.19 -r1.20 src/sys/dev/pci/mfii.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/sys/dev/ic/mfireg.h
diff -u src/sys/dev/ic/mfireg.h:1.21 src/sys/dev/ic/mfireg.h:1.22
--- src/sys/dev/ic/mfireg.h:1.21	Thu May 12 12:05:04 2022
+++ src/sys/dev/ic/mfireg.h	Wed Jun 29 13:03:20 2022
@@ -1,4 +1,4 @@
-/* $NetBSD: mfireg.h,v 1.21 2022/05/12 12:05:04 msaitoh Exp $ */
+/* $NetBSD: mfireg.h,v 1.22 2022/06/29 13:03:20 msaitoh Exp $ */
 /* $OpenBSD: mfireg.h,v 1.24 2006/06/19 19:05:45 marco Exp $ */
 /*
  * Copyright (c) 2006 Marco Peereboom <ma...@peereboom.us>
@@ -1267,6 +1267,7 @@ struct mfi_bbu_status {
 #define MFI_BBU_TYPE_IBBU	1
 #define MFI_BBU_TYPE_BBU	2
 #define MFI_BBU_TYPE_IBBU09	5
+#define MFI_BBU_TYPE_CVPM02	6
 	uint8_t			reserved;
 	uint16_t		voltage; /* mV */
 	int16_t			current; /* mA */

Index: src/sys/dev/pci/mfii.c
diff -u src/sys/dev/pci/mfii.c:1.19 src/sys/dev/pci/mfii.c:1.20
--- src/sys/dev/pci/mfii.c:1.19	Mon Jun 27 15:55:11 2022
+++ src/sys/dev/pci/mfii.c	Wed Jun 29 13:03:20 2022
@@ -1,4 +1,4 @@
-/* $NetBSD: mfii.c,v 1.19 2022/06/27 15:55:11 msaitoh Exp $ */
+/* $NetBSD: mfii.c,v 1.20 2022/06/29 13:03:20 msaitoh Exp $ */
 /* $OpenBSD: mfii.c,v 1.58 2018/08/14 05:22:21 jmatthew Exp $ */
 
 /*
@@ -19,7 +19,7 @@
  */
 
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: mfii.c,v 1.19 2022/06/27 15:55:11 msaitoh Exp $");
+__KERNEL_RCSID(0, "$NetBSD: mfii.c,v 1.20 2022/06/29 13:03:20 msaitoh Exp $");
 
 #include "bio.h"
 
@@ -3742,6 +3742,7 @@ mfii_bbu(struct mfii_softc *sc, envsys_d
 	switch (bbu.battery_type) {
 	case MFI_BBU_TYPE_IBBU:
 	case MFI_BBU_TYPE_IBBU09:
+	case MFI_BBU_TYPE_CVPM02:
 		mask = MFI_BBU_STATE_BAD_IBBU;
 		soh_bad = 0;
 		break;

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