Module Name: src
Committed By: rin
Date: Fri Sep 2 12:40:49 UTC 2022
Modified Files:
src/sys/arch/powerpc/fpu: fpu_emu.c fpu_emu.h fpu_explode.c
fpu_extern.h fpu_implode.c
Log Message:
Make fpu_explode() and fpu_implode() take uint64_t and uint64_t *,
instead of register number, respectively. NFC.
To generate a diff of this commit:
cvs rdiff -u -r1.44 -r1.45 src/sys/arch/powerpc/fpu/fpu_emu.c
cvs rdiff -u -r1.7 -r1.8 src/sys/arch/powerpc/fpu/fpu_emu.h
cvs rdiff -u -r1.11 -r1.12 src/sys/arch/powerpc/fpu/fpu_explode.c
cvs rdiff -u -r1.8 -r1.9 src/sys/arch/powerpc/fpu/fpu_extern.h
cvs rdiff -u -r1.16 -r1.17 src/sys/arch/powerpc/fpu/fpu_implode.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/powerpc/fpu/fpu_emu.c
diff -u src/sys/arch/powerpc/fpu/fpu_emu.c:1.44 src/sys/arch/powerpc/fpu/fpu_emu.c:1.45
--- src/sys/arch/powerpc/fpu/fpu_emu.c:1.44 Thu Sep 1 06:08:16 2022
+++ src/sys/arch/powerpc/fpu/fpu_emu.c Fri Sep 2 12:40:49 2022
@@ -1,4 +1,4 @@
-/* $NetBSD: fpu_emu.c,v 1.44 2022/09/01 06:08:16 rin Exp $ */
+/* $NetBSD: fpu_emu.c,v 1.45 2022/09/02 12:40:49 rin Exp $ */
/*
* Copyright 2001 Wasabi Systems, Inc.
@@ -76,7 +76,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: fpu_emu.c,v 1.44 2022/09/01 06:08:16 rin Exp $");
+__KERNEL_RCSID(0, "$NetBSD: fpu_emu.c,v 1.45 2022/09/02 12:40:49 rin Exp $");
#ifdef _KERNEL_OPT
#include "opt_ddb.h"
@@ -159,6 +159,7 @@ FPU_EMU_EVCNT_DECL(fnmadd);
FPSCR_VXSOFT | FPSCR_VXSQRT | FPSCR_VXCVI \
)
+#define FR(reg) (fs->fpreg[reg])
int fpe_debug = 0;
@@ -414,8 +415,9 @@ fpu_execute(struct trapframe *tf, struct
DPRINTF(FPE_INSN,
("fpu_execute: Store SNG at %p\n",
(void *)addr));
- fpu_explode(fe, fp = &fe->fe_f1, FTYPE_DBL, rt);
- fpu_implode(fe, fp, type, (void *)&buf);
+ fpu_explode(fe, fp = &fe->fe_f1, FTYPE_DBL,
+ FR(rt));
+ fpu_implode(fe, fp, type, &buf);
if (copyout(&buf, (void *)addr, size)) {
fe->fe_addr = addr;
return (FAULT);
@@ -439,9 +441,8 @@ fpu_execute(struct trapframe *tf, struct
return (FAULT);
}
if (type != FTYPE_DBL) {
- fpu_explode(fe, fp = &fe->fe_f1, type, rt);
- fpu_implode(fe, fp, FTYPE_DBL,
- (u_int *)&fs->fpreg[rt]);
+ fpu_explode(fe, fp = &fe->fe_f1, type, FR(rt));
+ fpu_implode(fe, fp, FTYPE_DBL, &FR(rt));
}
}
if (update)
@@ -471,8 +472,8 @@ fpu_execute(struct trapframe *tf, struct
FPU_EMU_EVCNT_INCR(fcmpu);
DPRINTF(FPE_INSN, ("fpu_execute: FCMPU\n"));
rt >>= 2;
- fpu_explode(fe, &fe->fe_f1, type, ra);
- fpu_explode(fe, &fe->fe_f2, type, rb);
+ fpu_explode(fe, &fe->fe_f1, type, FR(ra));
+ fpu_explode(fe, &fe->fe_f2, type, FR(rb));
fpu_compare(fe, 0);
/* Make sure we do the condition regs. */
cond = 0;
@@ -492,17 +493,18 @@ fpu_execute(struct trapframe *tf, struct
*/
FPU_EMU_EVCNT_INCR(frsp);
DPRINTF(FPE_INSN, ("fpu_execute: FRSP\n"));
- fpu_explode(fe, fp = &fe->fe_f1, FTYPE_DBL, rb);
- fpu_implode(fe, fp, FTYPE_SNG,
- (u_int *)&fs->fpreg[rt]);
- fpu_explode(fe, fp = &fe->fe_f1, FTYPE_SNG, rt);
+ fpu_explode(fe, fp = &fe->fe_f1, FTYPE_DBL,
+ FR(rb));
+ fpu_implode(fe, fp, FTYPE_SNG, &FR(rt));
+ fpu_explode(fe, fp = &fe->fe_f1, FTYPE_SNG,
+ FR(rt));
type = FTYPE_DBL | FTYPE_FPRF;
break;
case OPC63_FCTIW:
case OPC63_FCTIWZ:
FPU_EMU_EVCNT_INCR(fctiw);
DPRINTF(FPE_INSN, ("fpu_execute: FCTIW\n"));
- fpu_explode(fe, fp = &fe->fe_f1, type, rb);
+ fpu_explode(fe, fp = &fe->fe_f1, type, FR(rb));
type = FTYPE_INT;
if (instr.i_x.i_xo == OPC63_FCTIWZ)
type |= FTYPE_RD_RZ;
@@ -511,8 +513,8 @@ fpu_execute(struct trapframe *tf, struct
FPU_EMU_EVCNT_INCR(fcmpo);
DPRINTF(FPE_INSN, ("fpu_execute: FCMPO\n"));
rt >>= 2;
- fpu_explode(fe, &fe->fe_f1, type, ra);
- fpu_explode(fe, &fe->fe_f2, type, rb);
+ fpu_explode(fe, &fe->fe_f1, type, FR(ra));
+ fpu_explode(fe, &fe->fe_f2, type, FR(rb));
fpu_compare(fe, 1);
/* Make sure we do the condition regs. */
cond = 0;
@@ -614,7 +616,7 @@ fpu_execute(struct trapframe *tf, struct
case OPC63_FCTIDZ:
FPU_EMU_EVCNT_INCR(fctid);
DPRINTF(FPE_INSN, ("fpu_execute: FCTID\n"));
- fpu_explode(fe, fp = &fe->fe_f1, type, rb);
+ fpu_explode(fe, fp = &fe->fe_f1, type, FR(rb));
type = FTYPE_LNG;
if (instr.i_x.i_xo == OPC63_FCTIDZ)
type |= FTYPE_RD_RZ;
@@ -623,7 +625,7 @@ fpu_execute(struct trapframe *tf, struct
FPU_EMU_EVCNT_INCR(fcfid);
DPRINTF(FPE_INSN, ("fpu_execute: FCFID\n"));
type = FTYPE_LNG;
- fpu_explode(fe, fp = &fe->fe_f1, type, rb);
+ fpu_explode(fe, fp = &fe->fe_f1, type, FR(rb));
type = FTYPE_DBL | FTYPE_FPRF;
break;
default:
@@ -646,28 +648,28 @@ fpu_execute(struct trapframe *tf, struct
case OPC59_FDIVS:
FPU_EMU_EVCNT_INCR(fdiv);
DPRINTF(FPE_INSN, ("fpu_execute: FDIV\n"));
- fpu_explode(fe, &fe->fe_f1, type, ra);
- fpu_explode(fe, &fe->fe_f2, type, rb);
+ fpu_explode(fe, &fe->fe_f1, type, FR(ra));
+ fpu_explode(fe, &fe->fe_f2, type, FR(rb));
fp = fpu_div(fe);
break;
case OPC59_FSUBS:
FPU_EMU_EVCNT_INCR(fsub);
DPRINTF(FPE_INSN, ("fpu_execute: FSUB\n"));
- fpu_explode(fe, &fe->fe_f1, type, ra);
- fpu_explode(fe, &fe->fe_f2, type, rb);
+ fpu_explode(fe, &fe->fe_f1, type, FR(ra));
+ fpu_explode(fe, &fe->fe_f2, type, FR(rb));
fp = fpu_sub(fe);
break;
case OPC59_FADDS:
FPU_EMU_EVCNT_INCR(fadd);
DPRINTF(FPE_INSN, ("fpu_execute: FADD\n"));
- fpu_explode(fe, &fe->fe_f1, type, ra);
- fpu_explode(fe, &fe->fe_f2, type, rb);
+ fpu_explode(fe, &fe->fe_f1, type, FR(ra));
+ fpu_explode(fe, &fe->fe_f2, type, FR(rb));
fp = fpu_add(fe);
break;
case OPC59_FSQRTS:
FPU_EMU_EVCNT_INCR(fsqrt);
DPRINTF(FPE_INSN, ("fpu_execute: FSQRT\n"));
- fpu_explode(fe, &fe->fe_f1, type, rb);
+ fpu_explode(fe, &fe->fe_f1, type, FR(rb));
fp = fpu_sqrt(fe);
break;
case OPC63M_FSEL:
@@ -688,60 +690,56 @@ fpu_execute(struct trapframe *tf, struct
case OPC59_FRES:
FPU_EMU_EVCNT_INCR(fpres);
DPRINTF(FPE_INSN, ("fpu_execute: FPRES\n"));
- fpu_explode(fe, &fe->fe_f1, type, rb);
+ fpu_explode(fe, &fe->fe_f2, type, FR(rb));
fp = fpu_sqrt(fe);
- /* now we've gotta overwrite the dest reg */
- *((int *)&fe->fe_fpstate->fpreg[rt]) = 1;
- fpu_explode(fe, &fe->fe_f1, FTYPE_INT, rt);
+ fpu_explode(fe, &fe->fe_f1, FTYPE_INT, 1);
fpu_div(fe);
break;
case OPC59_FMULS:
FPU_EMU_EVCNT_INCR(fmul);
DPRINTF(FPE_INSN, ("fpu_execute: FMUL\n"));
- fpu_explode(fe, &fe->fe_f1, type, ra);
- fpu_explode(fe, &fe->fe_f2, type, rc);
+ fpu_explode(fe, &fe->fe_f1, type, FR(ra));
+ fpu_explode(fe, &fe->fe_f2, type, FR(rc));
fp = fpu_mul(fe);
break;
case OPC63M_FRSQRTE:
/* Reciprocal sqrt() estimate */
FPU_EMU_EVCNT_INCR(frsqrte);
DPRINTF(FPE_INSN, ("fpu_execute: FRSQRTE\n"));
- fpu_explode(fe, &fe->fe_f1, type, rb);
+ fpu_explode(fe, &fe->fe_f1, type, FR(rb));
fp = fpu_sqrt(fe);
fe->fe_f2 = *fp;
- /* now we've gotta overwrite the dest reg */
- *((int *)&fe->fe_fpstate->fpreg[rt]) = 1;
- fpu_explode(fe, &fe->fe_f1, FTYPE_INT, rt);
+ fpu_explode(fe, &fe->fe_f1, FTYPE_INT, 1);
fpu_div(fe);
break;
case OPC59_FMSUBS:
FPU_EMU_EVCNT_INCR(fmulsub);
DPRINTF(FPE_INSN, ("fpu_execute: FMULSUB\n"));
- fpu_explode(fe, &fe->fe_f1, type, ra);
- fpu_explode(fe, &fe->fe_f2, type, rc);
+ fpu_explode(fe, &fe->fe_f1, type, FR(ra));
+ fpu_explode(fe, &fe->fe_f2, type, FR(rc));
fp = fpu_mul(fe);
fe->fe_f1 = *fp;
- fpu_explode(fe, &fe->fe_f2, type, rb);
+ fpu_explode(fe, &fe->fe_f2, type, FR(rb));
fp = fpu_sub(fe);
break;
case OPC59_FMADDS:
FPU_EMU_EVCNT_INCR(fmuladd);
DPRINTF(FPE_INSN, ("fpu_execute: FMULADD\n"));
- fpu_explode(fe, &fe->fe_f1, type, ra);
- fpu_explode(fe, &fe->fe_f2, type, rc);
+ fpu_explode(fe, &fe->fe_f1, type, FR(ra));
+ fpu_explode(fe, &fe->fe_f2, type, FR(rc));
fp = fpu_mul(fe);
fe->fe_f1 = *fp;
- fpu_explode(fe, &fe->fe_f2, type, rb);
+ fpu_explode(fe, &fe->fe_f2, type, FR(rb));
fp = fpu_add(fe);
break;
case OPC59_FNMSUBS:
FPU_EMU_EVCNT_INCR(fnmsub);
DPRINTF(FPE_INSN, ("fpu_execute: FNMSUB\n"));
- fpu_explode(fe, &fe->fe_f1, type, ra);
- fpu_explode(fe, &fe->fe_f2, type, rc);
+ fpu_explode(fe, &fe->fe_f1, type, FR(ra));
+ fpu_explode(fe, &fe->fe_f2, type, FR(rc));
fp = fpu_mul(fe);
fe->fe_f1 = *fp;
- fpu_explode(fe, &fe->fe_f2, type, rb);
+ fpu_explode(fe, &fe->fe_f2, type, FR(rb));
fp = fpu_sub(fe);
/* Negate */
fp->fp_sign ^= 1;
@@ -749,11 +747,11 @@ fpu_execute(struct trapframe *tf, struct
case OPC59_FNMADDS:
FPU_EMU_EVCNT_INCR(fnmadd);
DPRINTF(FPE_INSN, ("fpu_execute: FNMADD\n"));
- fpu_explode(fe, &fe->fe_f1, type, ra);
- fpu_explode(fe, &fe->fe_f2, type, rc);
+ fpu_explode(fe, &fe->fe_f1, type, FR(ra));
+ fpu_explode(fe, &fe->fe_f2, type, FR(rc));
fp = fpu_mul(fe);
fe->fe_f1 = *fp;
- fpu_explode(fe, &fe->fe_f2, type, rb);
+ fpu_explode(fe, &fe->fe_f2, type, FR(rb));
fp = fpu_add(fe);
/* Negate */
fp->fp_sign ^= 1;
@@ -766,8 +764,9 @@ fpu_execute(struct trapframe *tf, struct
/* If the instruction was single precision, round */
if (!(instr.i_any.i_opcd & 0x4)) {
fpu_implode(fe, fp, FTYPE_SNG | FTYPE_FPRF,
- (u_int *)&fs->fpreg[rt]);
- fpu_explode(fe, fp = &fe->fe_f1, FTYPE_SNG, rt);
+ &FR(rt));
+ fpu_explode(fe, fp = &fe->fe_f1, FTYPE_SNG,
+ FR(rt));
} else
type |= FTYPE_FPRF;
}
@@ -782,7 +781,7 @@ fpu_execute(struct trapframe *tf, struct
* Otherwise set new current exceptions and accrue.
*/
if (fp)
- fpu_implode(fe, fp, type, (u_int *)&fs->fpreg[rt]);
+ fpu_implode(fe, fp, type, &FR(rt));
cx = fe->fe_cx;
fsr = fe->fe_fpscr & ~(FPSCR_FEX|FPSCR_VX);
if (cx != 0) {
Index: src/sys/arch/powerpc/fpu/fpu_emu.h
diff -u src/sys/arch/powerpc/fpu/fpu_emu.h:1.7 src/sys/arch/powerpc/fpu/fpu_emu.h:1.8
--- src/sys/arch/powerpc/fpu/fpu_emu.h:1.7 Thu Sep 1 06:08:16 2022
+++ src/sys/arch/powerpc/fpu/fpu_emu.h Fri Sep 2 12:40:49 2022
@@ -1,4 +1,4 @@
-/* $NetBSD: fpu_emu.h,v 1.7 2022/09/01 06:08:16 rin Exp $ */
+/* $NetBSD: fpu_emu.h,v 1.8 2022/09/02 12:40:49 rin Exp $ */
/*
* Copyright (c) 1992, 1993
@@ -185,8 +185,8 @@ struct fpn *fpu_newnan(struct fpemu *);
*/
int fpu_shr(struct fpn *, int);
-void fpu_explode(struct fpemu *, struct fpn *, int, int);
-void fpu_implode(struct fpemu *, struct fpn *, int, u_int *);
+void fpu_explode(struct fpemu *, struct fpn *, int, uint64_t);
+void fpu_implode(struct fpemu *, struct fpn *, int, uint64_t *);
#ifdef DEBUG
#define FPE_EX 0x1
Index: src/sys/arch/powerpc/fpu/fpu_explode.c
diff -u src/sys/arch/powerpc/fpu/fpu_explode.c:1.11 src/sys/arch/powerpc/fpu/fpu_explode.c:1.12
--- src/sys/arch/powerpc/fpu/fpu_explode.c:1.11 Fri Sep 2 12:30:48 2022
+++ src/sys/arch/powerpc/fpu/fpu_explode.c Fri Sep 2 12:40:49 2022
@@ -1,4 +1,4 @@
-/* $NetBSD: fpu_explode.c,v 1.11 2022/09/02 12:30:48 rin Exp $ */
+/* $NetBSD: fpu_explode.c,v 1.12 2022/09/02 12:40:49 rin Exp $ */
/*
* Copyright (c) 1992, 1993
@@ -46,7 +46,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: fpu_explode.c,v 1.11 2022/09/02 12:30:48 rin Exp $");
+__KERNEL_RCSID(0, "$NetBSD: fpu_explode.c,v 1.12 2022/09/02 12:40:49 rin Exp $");
#include <sys/types.h>
#include <sys/systm.h>
@@ -206,40 +206,38 @@ fpu_dtof(struct fpn *fp, u_int hi, u_int
* operations are performed.)
*/
void
-fpu_explode(struct fpemu *fe, struct fpn *fp, int type, int reg)
+fpu_explode(struct fpemu *fe, struct fpn *fp, int type, uint64_t i)
{
- u_int s, *space;
- uint64_t l, *xspace;
+ u_int hi, lo;
+ int class;
- xspace = (uint64_t *)&fe->fe_fpstate->fpreg[reg];
- l = xspace[0];
- space = (u_int *)&fe->fe_fpstate->fpreg[reg];
- s = space[0];
- fp->fp_sign = s >> 31;
+ hi = (u_int)(i >> 32);
+ lo = (u_int)i;
+ fp->fp_sign = hi >> 31;
fp->fp_sticky = 0;
switch (type) {
case FTYPE_LNG:
- s = fpu_xtof(fp, l);
+ class = fpu_xtof(fp, i);
break;
case FTYPE_INT:
- s = fpu_itof(fp, space[1]);
+ class = fpu_itof(fp, lo);
break;
case FTYPE_SNG:
- s = fpu_stof(fp, s);
+ class = fpu_stof(fp, hi);
break;
case FTYPE_DBL:
- s = fpu_dtof(fp, s, space[1]);
+ class = fpu_dtof(fp, hi, lo);
break;
default:
panic("fpu_explode: invalid type %d", type);
}
- if (s == FPC_QNAN && (fp->fp_mant[0] & FP_QUIETBIT) == 0) {
+ if (class == FPC_QNAN && (fp->fp_mant[0] & FP_QUIETBIT) == 0) {
/*
* Input is a signalling NaN. All operations that return
* an input NaN operand put it through a ``NaN conversion'',
@@ -249,13 +247,8 @@ fpu_explode(struct fpemu *fe, struct fpn
*/
fp->fp_mant[0] |= FP_QUIETBIT;
fe->fe_cx = FPSCR_VXSNAN; /* assert invalid operand */
- s = FPC_SNAN;
+ class = FPC_SNAN;
}
- fp->fp_class = s;
- DPRINTF(FPE_REG, ("fpu_explode: %%%c%d => ", (type == FTYPE_LNG) ? 'x' :
- ((type == FTYPE_INT) ? 'i' :
- ((type == FTYPE_SNG) ? 's' :
- ((type == FTYPE_DBL) ? 'd' : '?'))),
- reg));
+ fp->fp_class = class;
DUMPFPN(FPE_REG, fp);
}
Index: src/sys/arch/powerpc/fpu/fpu_extern.h
diff -u src/sys/arch/powerpc/fpu/fpu_extern.h:1.8 src/sys/arch/powerpc/fpu/fpu_extern.h:1.9
--- src/sys/arch/powerpc/fpu/fpu_extern.h:1.8 Thu Sep 1 05:58:19 2022
+++ src/sys/arch/powerpc/fpu/fpu_extern.h Fri Sep 2 12:40:49 2022
@@ -1,4 +1,4 @@
-/* $NetBSD: fpu_extern.h,v 1.8 2022/09/01 05:58:19 rin Exp $ */
+/* $NetBSD: fpu_extern.h,v 1.9 2022/09/02 12:40:49 rin Exp $ */
/*-
* Copyright (c) 1995 The NetBSD Foundation, Inc.
@@ -60,10 +60,10 @@ int fpu_itof(struct fpn *, u_int);
int fpu_xtof(struct fpn *, uint64_t);
int fpu_stof(struct fpn *, u_int);
int fpu_dtof(struct fpn *, u_int, u_int);
-void fpu_explode(struct fpemu *, struct fpn *, int, int);
+void fpu_explode(struct fpemu *, struct fpn *, int, uint64_t);
/* fpu_implode.c */
-void fpu_implode(struct fpemu *, struct fpn *, int, u_int *);
+void fpu_implode(struct fpemu *, struct fpn *, int, uint64_t *);
/* fpu_mul.c */
struct fpn *fpu_mul(struct fpemu *);
Index: src/sys/arch/powerpc/fpu/fpu_implode.c
diff -u src/sys/arch/powerpc/fpu/fpu_implode.c:1.16 src/sys/arch/powerpc/fpu/fpu_implode.c:1.17
--- src/sys/arch/powerpc/fpu/fpu_implode.c:1.16 Fri Sep 2 12:24:54 2022
+++ src/sys/arch/powerpc/fpu/fpu_implode.c Fri Sep 2 12:40:49 2022
@@ -1,4 +1,4 @@
-/* $NetBSD: fpu_implode.c,v 1.16 2022/09/02 12:24:54 rin Exp $ */
+/* $NetBSD: fpu_implode.c,v 1.17 2022/09/02 12:40:49 rin Exp $ */
/*
* Copyright (c) 1992, 1993
@@ -46,7 +46,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: fpu_implode.c,v 1.16 2022/09/02 12:24:54 rin Exp $");
+__KERNEL_RCSID(0, "$NetBSD: fpu_implode.c,v 1.17 2022/09/02 12:40:49 rin Exp $");
#include <sys/types.h>
#include <sys/systm.h>
@@ -516,11 +516,15 @@ done:
* Implode an fpn, writing the result into the given space.
*/
void
-fpu_implode(struct fpemu *fe, struct fpn *fp, int type, u_int *space)
+fpu_implode(struct fpemu *fe, struct fpn *fp, int type, uint64_t *p)
{
+ u_int *hi, *lo;
int rn;
bool fprf;
+ hi = (u_int *)p;
+ lo = hi + 1;
+
if (type & FTYPE_RD_RZ)
rn = FSR_RD_RZ;
else
@@ -532,27 +536,27 @@ fpu_implode(struct fpemu *fe, struct fpn
case FTYPE_LNG:
/* FPRF is undefined. */
- *(uint64_t *)space = fpu_ftox(fe, fp, rn);
+ *p = fpu_ftox(fe, fp, rn);
DPRINTF(FPE_REG, ("fpu_implode: long %x %x\n",
space[0], space[1]));
break;
case FTYPE_INT:
/* FPRF is undefined. */
- space[0] = 0;
- space[1] = fpu_ftoi(fe, fp, rn);
+ *hi = 0;
+ *lo = fpu_ftoi(fe, fp, rn);
DPRINTF(FPE_REG, ("fpu_implode: int %x\n",
space[1]));
break;
case FTYPE_SNG:
- space[0] = fpu_ftos(fe, fp, fprf);
+ *hi = fpu_ftos(fe, fp, fprf);
DPRINTF(FPE_REG, ("fpu_implode: single %x\n",
space[0]));
break;
case FTYPE_DBL:
- *(uint64_t *)space = fpu_ftod(fe, fp, fprf);
+ *p = fpu_ftod(fe, fp, fprf);
DPRINTF(FPE_REG, ("fpu_implode: double %x %x\n",
space[0], space[1]));
break; break;
