CVS commit: src/sys/arch/powerpc/fpu

[Rin Okuyama]

Module Name:    src
Committed By:   rin
Date:           Wed Sep 14 05:54:07 UTC 2022

Modified Files:
        src/sys/arch/powerpc/fpu: fpu_implode.c

Log Message:
Fix logic for FPSCR[UX]:
- Correct FPSCR[FPRF] field when round to 0.0 or 0.0f.
- Simplify.


To generate a diff of this commit:
cvs rdiff -u -r1.22 -r1.23 src/sys/arch/powerpc/fpu/fpu_implode.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.


Modified files:

Index: src/sys/arch/powerpc/fpu/fpu_implode.c
diff -u src/sys/arch/powerpc/fpu/fpu_implode.c:1.22 src/sys/arch/powerpc/fpu/fpu_implode.c:1.23
--- src/sys/arch/powerpc/fpu/fpu_implode.c:1.22	Sun Sep  4 13:17:33 2022
+++ src/sys/arch/powerpc/fpu/fpu_implode.c	Wed Sep 14 05:54:07 2022
@@ -1,4 +1,4 @@
-/*	$NetBSD: fpu_implode.c,v 1.22 2022/09/04 13:17:33 rin Exp $ */
+/*	$NetBSD: fpu_implode.c,v 1.23 2022/09/14 05:54:07 rin Exp $ */
 
 /*
  * Copyright (c) 1992, 1993
@@ -46,7 +46,7 @@
  */
 
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: fpu_implode.c,v 1.22 2022/09/04 13:17:33 rin Exp $");
+__KERNEL_RCSID(0, "$NetBSD: fpu_implode.c,v 1.23 2022/09/14 05:54:07 rin Exp $");
 
 #include <sys/types.h>
 #include <sys/systm.h>
@@ -397,10 +397,14 @@ fpu_ftos(struct fpemu *fe, struct fpn *f
 			*cx |= FPRF_SIGN(sign);
 			return (sign | SNG_EXP(1) | 0);
 		}
-		*cx |= FPSCR_C | FPRF_SIGN(sign);
-		if (((fe->fe_cx | *cx) & FPSCR_FI) ||
-		    (fe->fe_fpscr & FPSCR_UX))
+		if (*cx & FPSCR_FI) {
 			*cx |= FPSCR_UX;
+			if (fp->fp_mant[3] == 0) {
+				*cx |= FPSCR_FE;
+				return sign;
+			}
+		}
+		*cx |= FPSCR_C | FPRF_SIGN(sign);
 		return (sign | SNG_EXP(0) | fp->fp_mant[3]);
 	}
 	/* -FP_NG for g,r; -1 for implied 1; -SNG_FRACBITS for fraction */
@@ -466,10 +470,15 @@ fpu_ftod(struct fpemu *fe, struct fpn *f
 			*cx |= FPRF_SIGN(sign);
 			return HI_WORD(sign | DBL_EXP(1) | 0);
 		}
-		*cx |= FPSCR_C | FPRF_SIGN(sign);
-		if (((fe->fe_cx | *cx) & FPSCR_FI) ||
-		    (fe->fe_fpscr & FPSCR_UX))
+		if (*cx & FPSCR_FI) {
 			*cx |= FPSCR_UX;
+			if ((fp->fp_mant[2] & DBL_MASK) == 0 &&
+			     fp->fp_mant[3] == 0) {
+				*cx |= FPSCR_FE;
+				return HI_WORD(sign);
+			}
+		}
+		*cx |= FPSCR_C | FPRF_SIGN(sign);
 		exp = 0;
 		goto done;
 	}